Data Sheet

74AUP1T98-Q100
Low-power configurable gate with voltage-level translator
Rev. 1 — 19 May 2014
Product data sheet
1. General description
The 74AUP1T98-Q100 provides low-power, low-voltage configurable logic gate functions.
Eight patterns of 3-bit input determine the output state. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to
VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 2.3 V to 3.6 V.
The 74AUP1T98-Q100 is designed for logic-level translation applications. The input
switching levels accept 1.8 V low-voltage CMOS signals, while operating from either a
single 2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire VCC range.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide supply voltage range from 2.3 V to 3.6 V
 High noise immunity
 ESD protection:
 MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
 HBM JESD22-A114F Class 3A. Exceeds 5000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
 Low static power consumption; ICC = 1.5 A (maximum)
 Latch-up performance exceeds 100 mA per JESD 78 Class II
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of VCC
 IOFF circuitry provides partial power-down mode operation
74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
74AUP1T98GW-Q100 40 C to +125 C
SC-88
Description
Version
plastic surface-mounted package; 6 leads
SOT363
4. Marking
Table 2.
Marking
Type number
Marking code
74AUP1T98GW-Q100
aR
5. Functional diagram
$
%
&
Fig 1.
<
DDG
Logic symbol
6. Pinning information
6.1 Pinning
$8374
%
&
*1'
9&&
$
<
DDD
Fig 2.
Pin configuration SOT363
74AUP1T98-Q100
Product data sheet
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Rev. 1 — 19 May 2014
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74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
B
1
data input
GND
2
ground (0 V)
A
3
data input
Y
4
data output
VCC
5
supply voltage
C
6
data input
7. Functional description
Table 4.
Function table[1]
Input
Output
C
B
A
Y
L
L
L
H
L
L
H
H
L
H
L
L
L
H
H
L
H
L
L
H
H
L
H
L
H
H
L
H
H
H
H
L
[1]
H = HIGH voltage level; L = LOW voltage level.
7.1 Logic configurations
Table 5.
Function selection table
Logic function
Figure
2-input MUX (inverting)
see Figure 3
2-input NAND
see Figure 4
2-input NOR with one input inverted
see Figure 5
2-input AND with one input inverted
see Figure 5
2-input NAND with one input inverted
see Figure 6
2-input OR with one input inverted
see Figure 6
2-input NOR
see Figure 7
Buffer
see Figure 8
Inverter
see Figure 9
74AUP1T98-Q100
Product data sheet
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Rev. 1 — 19 May 2014
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3 of 16
74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
9&&
9&&
%
%
&
<
$
&
$
$
&
<
<
$
DDG
Fig 3.
&
<
DDG
2-input MUX (inverting)
Fig 4.
2-input NAND gate
9&&
$
&
<
$
&
<
$
9&&
&
<
%
&
<
%
&
<
%
<
DDG
DDG
Fig 5.
&
2-input AND gate with input A inverted or
2-input NOR gate with input C inverted
Fig 6.
2-input OR gate with input B inverted or
2-input NAND gate with input C inverted
9&&
%
%
&
<
9&&
&
&
<
&
<
DDG
Fig 7.
<
DDG
2-input NOR gate
Fig 8.
Buffer
9&&
%
%
<
<
DDG
Fig 9.
Inverter
74AUP1T98-Q100
Product data sheet
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Rev. 1 — 19 May 2014
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74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
VO < 0 V
[1]
Min
Max
Unit
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
VO
output voltage
Active mode and Power-down mode
IO
output current
VO = 0 V to VCC
-
20
mA
ICC
supply current
-
+50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
-
250
mW
total power dissipation
Ptot
Tamb = 40 C to +125 C
[2]
[1]
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SC-88 package: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 7.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Tamb
Conditions
Product data sheet
Max
Unit
2.3
3.6
V
0
3.6
V
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
3.6
V
40
+125
C
ambient temperature
74AUP1T98-Q100
Min
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Rev. 1 — 19 May 2014
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74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
VT+
VT
VH
VOH
VOL
positive-going threshold
voltage
negative-going threshold
voltage
hysteresis voltage
HIGH-level output voltage
LOW-level output voltage
VCC = 2.3 V to 2.7 V
0.60
-
1.10
V
VCC = 3.0 V to 3.6 V
0.75
-
1.16
V
VCC = 2.3 V to 2.7 V
0.35
-
0.60
V
VCC = 3.0 V to 3.6 V
0.50
-
0.85
V
VCC = 2.3 V to 2.7 V
0.23
-
0.60
V
VCC = 3.0 V to 3.6 V
0.25
-
0.56
V
(VH = VT+  VT)
VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V
VCC  0.1
-
-
V
IO = 2.3 mA; VCC = 2.3 V
2.05
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.9
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.72
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.6
-
-
V
IO = 20 A; VCC = 2.3 V to 3.6 V
-
-
0.10
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.44
V
-
-
0.1
A
VI = VT+ or VT
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.1
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.2
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
1.2
A
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
0.8
-
pF
CO
output capacitance
VO = GND; VCC = 0 V
-
1.7
-
pF
Tamb = 40 C to +85 C
VT+
VT
VH
positive-going threshold
voltage
negative-going threshold
voltage
hysteresis voltage
74AUP1T98-Q100
Product data sheet
VCC = 2.3 V to 2.7 V
0.60
-
1.10
V
VCC = 3.0 V to 3.6 V
0.75
-
1.19
V
VCC = 2.3 V to 2.7 V
0.35
-
0.60
V
VCC = 3.0 V to 3.6 V
0.50
-
0.85
V
VCC = 2.3 V to 2.7 V
0.10
-
0.60
V
VCC = 3.0 V to 3.6 V
0.15
-
0.56
V
(VH = VT+  VT)
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Rev. 1 — 19 May 2014
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74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VOH
VI = VT+ or VT
VOL
HIGH-level output voltage
LOW-level output voltage
Min
Typ
Max
Unit
IO = 20 A; VCC = 2.3 V to 3.6 V
VCC  0.1
-
-
V
IO = 2.3 mA; VCC = 2.3 V
1.97
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.85
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.67
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.55
-
-
V
IO = 20 A; VCC = 2.3 V to 3.6 V
-
-
0.1
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.45
V
VI = VT+ or VT
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.5
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.5
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.5
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
1.5
A
ICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
[1]
-
-
4
A
VCC = 3.0 V to 3.6 V; IO = 0 A
[2]
-
-
12
A
VCC = 2.3 V to 2.7 V
0.60
-
1.10
V
VCC = 3.0 V to 3.6 V
0.75
-
1.19
V
VCC = 2.3 V to 2.7 V
0.33
-
0.64
V
VCC = 3.0 V to 3.6 V
0.46
-
0.85
V
VCC = 2.3 V to 2.7 V
0.10
-
0.60
V
VCC = 3.0 V to 3.6 V
0.15
-
0.56
V
Tamb = 40 C to +125 C
VT+
positive-going threshold
voltage
VT
negative-going threshold
voltage
VH
VOH
VOL
II
hysteresis voltage
HIGH-level output voltage
LOW-level output voltage
input leakage current
74AUP1T98-Q100
Product data sheet
(VH = VT+  VT)
VI = VT+ or VT
IO = 20 A; VCC = 2.3 V to 3.6 V
VCC  0.11 -
-
V
IO = 2.3 mA; VCC = 2.3 V
1.77
-
-
V
IO = 3.1 mA; VCC = 2.3 V
1.67
-
-
V
IO = 2.7 mA; VCC = 3.0 V
2.40
-
-
V
IO = 4.0 mA; VCC = 3.0 V
2.30
-
-
V
IO = 20 A; VCC = 2.3 V to 3.6 V
-
-
0.11
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.50
V
-
-
0.75
A
VI = VT+ or VT
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
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Rev. 1 — 19 May 2014
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74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
Table 8.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.75
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.75
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
3.5
A
ICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
[1]
-
-
7
A
VCC = 3.0 V to 3.6 V; IO = 0 A
[2]
-
-
22
A
[1]
One input at 0.3 V or 1.1 V, other input at VCC or GND.
[2]
One input at 0.45 V or 1.2 V, other input at VCC or GND.
11. Dynamic characteristics
Table 9.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter
25 C
Conditions
Min
40 C to +125 C
Typ[1]
Max
Min
Max
(85 C)
Max
(125 C)
Unit
VCC = 2.3 V to 2.7 V; VI = 1.65 V to 1.95 V
tpd
propagation delay A, B, C to Y; see Figure 10
[2]
CL = 5 pF
2.0
3.6
5.7
0.5
6.8
7.5
ns
CL = 10 pF
2.5
4.2
6.3
1.0
7.9
8.7
ns
CL = 15 pF
2.9
4.6
6.9
1.0
8.7
9.6
ns
CL = 30 pF
3.9
5.8
8.3
1.5
10.8
11.9
ns
CL = 5 pF
1.7
3.4
5.6
0.5
6.0
6.6
ns
CL = 10 pF
2.1
4.0
6.3
1.0
7.1
7.9
ns
CL = 15 pF
2.5
4.5
6.9
1.0
7.9
8.7
ns
CL = 30 pF
3.4
5.6
8.4
1.5
10.0
11.0
ns
VCC = 2.3 V to 2.7 V; VI = 2.3 V to 2.7 V
tpd
propagation delay A, B, C to Y; see Figure 10
[2]
VCC = 2.3 V to 2.7 V; VI = 3.0 V to 3.6 V
tpd
propagation delay A, B, C to Y; see Figure 10
[2]
CL = 5 pF
1.3
3.2
5.2
0.5
5.5
6.1
ns
CL = 10 pF
1.8
3.7
5.9
1.0
6.5
7.2
ns
CL = 15 pF
2.2
4.2
6.5
1.0
7.4
8.2
ns
CL = 30 pF
3.1
5.4
7.9
1.5
9.5
10.5
ns
CL = 5 pF
2.0
2.9
4.1
0.5
8.0
8.8
ns
CL = 10 pF
2.4
3.5
4.8
1.0
8.5
9.4
ns
CL = 15 pF
2.8
3.9
5.4
1.0
9.1
10.1
ns
CL = 30 pF
3.6
5.1
6.9
1.5
9.8
10.8
ns
VCC = 3.0 V to 3.6 V; VI = 1.65 V to 1.95 V
tpd
propagation delay A, B, C to Y; see Figure 10
74AUP1T98-Q100
Product data sheet
[2]
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Rev. 1 — 19 May 2014
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74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
(85 C)
Max
(125 C)
CL = 5 pF
1.5
2.8
4.4
0.5
5.3
5.9
ns
CL = 10 pF
2.0
3.4
5.1
1.0
6.1
6.8
ns
CL = 15 pF
2.4
3.9
5.7
1.0
6.8
7.5
ns
CL = 30 pF
3.4
5.0
7.2
1.5
8.5
9.4
ns
VCC = 3.0 V to 3.6 V; VI = 2.3 V to 2.7 V
propagation delay A, B, C to Y; see Figure 10
tpd
[2]
VCC = 3.0 V to 3.6 V; VI = 3.0 V to 3.6 V
propagation delay A, B, C to Y; see Figure 10
tpd
[2]
CL = 5 pF
1.3
2.8
4.4
0.5
4.7
5.2
ns
CL = 10 pF
1.7
3.3
5.2
1.0
5.7
6.3
ns
CL = 15 pF
2.1
3.8
5.8
1.0
6.2
6.9
ns
CL = 30 pF
3.1
5.0
7.2
1.5
7.8
8.6
ns
VCC = 2.3 V to 2.7 V
-
3.6
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
4.3
-
-
-
-
pF
Tamb = 25 C
power dissipation
capacitance
CPD
fi = 1 MHz; VI = GND to VCC
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPLH and tPHL
[3]
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of the outputs.
74AUP1T98-Q100
Product data sheet
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Rev. 1 — 19 May 2014
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Low-power configurable gate with voltage-level translator
12. Waveforms
VI
A, B, C input
VM
VM
GND
t PHL
t PLH
VOH
VM
Y output
VM
VOL
t PLH
t PHL
VOH
Y output
VM
VM
VOL
001aab593
Measurement points are given in Table 10.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Input A, B and C to output Y propagation delay times
Table 10.
Measurement points
Supply voltage
Output
Input
VCC
VM
VM
VI
tr = tf
2.3 V to 3.6 V
0.5  VCC
0.5  VI
1.65 V to 3.6 V
 3.0 ns
74AUP1T98-Q100
Product data sheet
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Rev. 1 — 19 May 2014
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74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
9&&
9(;7
Nȍ
*
9,
92
'87
&/
57
5/
DDF
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 11. Test circuit for measuring switching times
Table 11.
Test data
Supply voltage
Load
VEXT
[1]
VCC
CL
RL
2.3 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
5 k or 1 M
[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
open
GND
2  VCC
For measuring enable and disable times, RL = 5 k. For measuring propagation delays, setup and hold times, and pulse width,
RL = 1 M.
74AUP1T98-Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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Low-power configurable gate with voltage-level translator
13. Package outline
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74AUP1T98-Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
12 of 16
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NXP Semiconductors
Low-power configurable gate with voltage-level translator
14. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
15. Revision history
Table 13.
Revision history
Document ID
Release date
74AUP1T98_Q100 v.1 20140519
74AUP1T98-Q100
Product data sheet
Data sheet status
Change notice
Supersedes
Product data sheet
-
-
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 16
74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74AUP1T98-Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 16
74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74AUP1T98-Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
15 of 16
74AUP1T98-Q100
NXP Semiconductors
Low-power configurable gate with voltage-level translator
18. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Logic configurations . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 19 May 2014
Document identifier: 74AUP1T98-Q100