oH V SC AV ER OM AI SIO PL LA N IA BL S NT E Features ■ *R ■ ■ ■ ■ Lead free versions available RoHS compliant (lead free version)* New Product Development Integrated Passive Device ESD Protection to IEC61000-4-2 Spec. 2FAH-C20R Series - Integrated Passive & Active Device using CSP General Information This application specific integrated passive component is designed to provide all of the necessary ESD protection and line resistance required on the data port of a custom portable electronic device. The ESD protection provided by the component enables the data port to withstand ±8 KV Contact / ±15 KV Air Discharge when tested according to the method specified in IEC 61000-4-2. The component incorporates 7 identical channels and is supplied in a 20 pin CSP package which is intended to be mounted directly onto an FR4 printed circuit board. This package will meet typical thermal cycle and bend test specifications without the use of an underfill material. SOLDER BUMPS SILICON DIE E T E L O S B O Figure 1 – CSP Format Electrical & Thermal Characteristics Electrical Characteristics (TA = 25 °C unless otherwise noted) Zener Diode Breakdown Voltage @ 1 mA Leakage Current @ 3 V ESD Performance (Note 1) Withstand Contact Discharge Air Discharge Let Through (Note 2) Contact Discharge Air Discharge Channel Specification Resistance Capacitance @ 1 V & 1 MHz Symbol Minimum Nominal Maximum Unit VBR IR 6 7.2 8 1 V µA ±8 ±15 kV kV ±150 ±150 V V R C 90 8.5 100 10.5 110 12.5 Ω pF TJ Tstg PD -40 -60 25 25 +85 +125 100 °C °C mW Thermal Characteristics (TA = 25 °C unless otherwise noted) Operating Temperature Storage Temperature Total Power Dissipation @ 70 °C Note: 1. The IEC 61000-4-2 test method will be adapted for component level testing. The device will provide the specified ESD protection performance on the “IN 1-7” pins only. 2. “Let Through” is a measure of the component of an incident ESD transient that the protection device allows through to the down stream circuitry. *RoHS Directive 2002/95/EC Jan 27 2003 including Annex Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. 2FAH-C20R Series - Integrated Passive & Active Device using CSP Mechanical Characteristics This is a Silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the Silicon die, provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is 0.5mm. The dimensions for the CSP packaged device are shown in Fig. 2 below. 248.5 ± 45 (9.78 ± 1.78) 858 ± 40 (33.78 ± 1.57) BUMP A1/PIN 1 INDICATOR A1 BOURNS LOGO B1 A2 B2 C1 D1 C2 D2 300 DIA. (11.81) E T E L O S B O 500 (19.69) A3 B3 C3 D3 A4 B4 C4 D4 2597 ± 45 (102.24 ± 1.78) 500 (19.69) A5 225 ± 20 (8.86 ± 0.79) 348.5 ± 45 (13.72 ± 1.78) B5 248.5 ± 45 (9.78 ± 1.78) C5 D5 45 ± 45 (1.78 ± 1.78) 45 ± 45 (1.78 ± 1.78) 1997 ± 45 (78.62 ± 1.78) DIMENSIONS = MICRONS (MILS) Fig. 2 – Device Mechanical Drawing Reliability Reliability data exists and continues to be gathered on an ongoing basis for Bourns Integrated Passive and Active Devices using CSP packaging. “Package level” testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy Chain component is available from Bourns for this purpose (part number 2TAD-C25R). This is a 5 x 5 array featuring 0.5mm pitch solder bumps. The Distance to Neutral Point (DNP) on that component is larger than that of the 2FAH-C20R and is thus deemed a worse case for Thermal Cycle testing. “Silicon level” reliability performance will be assured by similarity to other Integrated Passive and Active Devices using CSP product from Bourns. Individual Channel Schematic This section contains the schematic (See Fig. 3 below) for the single channel in the integrated passive device. Note that the electrical parameters of primary interest are (a) DC Resistance and (b) ESD performance. In terms of DC parameters it should be noted that all resistor values have a tolerance of ±10 %. This schematic consists of a series 100ohm resistance and Back to Back Zener 6.5 Volt diodes for ESD protection. IN OUT 100Ω ±6.5V Key Design Parameters DC Channel Resistance: 100 Ω ±10 % DC Channel Capacitance: 12.5 pF Maximum VBR: 6 V Min, 8 V Max @ IBR = 1 mA. IR: 1 uA Max @ VR =3 V. Fig. 3 – Channel Schematic Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. 2FAH-C20R Series - Integrated Passive & Active Device using CSP Block Diagram Marking Figure 4 contains a block diagram of the CSP device. This diagram includes the pin names and basic electrical connections associated with each channel. IN1 OUT1 100Ω The device will be laser marked on the backside according to the following Fig. 5 scheme below. Position A1, on the Bump Grid is located at the top left of the die when the die is orientated so that the mark is read in the normal fashion. PIN A1 LOCATION ±6.5V 1 2 3 4 5 A IN2 OUT2 100Ω B E T E L O S B O ±6.5V IN3 C FAH Lotcode D OUT3 100Ω ±6.5V IN4 Fig. 5 – Backside Laser Mark OUT4 100Ω ±6.5V IN5 PCB Design and SMT Processing Please consult Bourns’ Thin Film on Silicon using CSP Users Guide Application Note for notes on PCB design and SMT processing. OUT5 100Ω ±6.5V How to Order IN6 OUT6 100Ω 2 FAH - C20R ____ ±6.5V Thinfilm Model IN7 Chipscale OUT7 100Ω No. of Solder Bumps Packaging Option R = Tape and Reel Packaged 3000 pcs. / 7 ” reel ±6.5V GROUND GROUND Fig. 4 – Device Block Diagram Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. Terminations LF = Sn/Ag/Cu (lead free) Blank = Sn/Pb 2FAH-C20R Series - Integrated Passive & Active Device using CSP Device Pin Out The Pin-Out for the device is shown in Fig. 6. Note also that the device is shown with bumps facing up. OUT 3 OUT 4 OUT 5 D OUT 2 OUT 6 C OUT 1 OUT 7 B GROUND X6 IN 1 A IN 6 1 IN 3 2 3 4 IN 4 Function OUT4 OUT5 OUT6 OUT7 Ground Ground Ground Ground Ground Ground Pin Out D3 D4 D5 C5 B2 B3 B4 C2 C3 C4 5 IN 5 Fig. 6 (a) - Device Pin Out “Bumps Up” View Packaging Pin Out B1 A1 A2 A3 A4 A5 B5 C1 D1 D2 E T E L O S B O IN 7 IN 2 Function IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT1 OUT2 OUT3 Fig. 6 (b) - Pin Listings The product will be dispensed in an 8mm x 4mm Tape and Reel format - see Fig. 7 diagram below. The Tape and Reel package will conform to customer specification. 0.3 ± 0.05 (.01 ± .002) 4.0 ± 0.1 (.16 ± .004) 1.5 ± 0.1/-0 (.06 ± .004/-0) DIA. 2.0 ± 0.05 (.08 ± .002) R 1.75 ± 0.1 (.07 ± .004) 0.3 MAX. (0.01) 0.9 ± 0.05 (.04 ± .002) 8.0 ± 0.3 (.31 ± .01) 2.77 ± 0.05 (.11 ± .002) 3.5 ± 0.05 (.14 ± .002) 2.19 ± 0.05 (.09 ± .002) 4.0 ± 0.1 (.16 ± .004) ORIENTATION OF COMPONENT IN POCKET R 0.25 TYP. (0.001) DIMENSIONS = Fig. 7 - Tape and Reel Drawing BACKSIDE FACING UP MILLIMETERS (INCHES) Reliable Electronic Solutions Asia-Pacific: TEL +886- (0)2 25624117 • FAX +886- (0)2 25624116 Europe: TEL +353 214 515 225 • FAX +353 214 515 292 The Americas: TEL +1-951 781-5492 • FAX +1-951 781-5700 www.bourns.com Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. COPYRIGHT© 2001, BOURNS, INC. LITHO IN U.S.A. IP 5/02 .5M/CS0202 2FAH-C20R REV. G, 02/05