2FAG-C15R

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V SC
AV ER OM
AI SIO PL
LA N IA
BL S NT
E
Features
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Applications
Lead free versions available
RoHS compliant (lead free version)*
Bidirectional EMI filtering
Low capacitance per line
ESD protection
Protects 6 data lines
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Cell phones
PDAs and notebooks
Digital cameras
MP3 players and GPS
2FAG-C15R - Integrated Passive & Active Device using CSP
General Information
The 2FAG-C15R device, manufactured using Thin Film on
Silicon technology, provides ESD protection and EMI
filtering for the LCD displays of portable electronic
devices such as cell phones, modems and PDAs. The
device incorporates six low pass filter channels where
each channel has a series 100 ohm resistor assuring a
minimum of -25 dB attenuation from 800 MHz to 3 GHz.
Each internal and external port of the six channels
includes a TVS diode for ESD protection. The ESD
protection provided by the component enables a data
port to withstand a minimum ±8 KV Contact / ±15 KV Air
Discharge per the ESD test method specified in IEC
61000-4-2. The device measures 1.33 mm x 2.96 mm and
is available in a 15 bump CSP package intended to be
mounted directly onto an FR4 printed circuit board. The
CSP device meets typical thermal cycle and bend test
specifications without the use of an underfill material.
SOLDER
BUMPS
SILICON
DIE
E
T
E
L
O
S
B
O
Electrical & Thermal Characteristics
Electrical Characteristics
(TA = 25 °C unless otherwise noted)
Per Line Specification
Resistance
Capacitance @ 2.5 V 1 MHz
Rated Standoff Voltage
Breakdown Voltage @ 1 mA
Forward Voltage @ 10 mA
Leakage Current @ 3.3 V
Filter Attenuation @ 800 - 3000 MHz
ESD Protection: IEC 61000-4-2
Contact Discharge
Air Discharge
Symbol
Minimum
Nominal
Maximum
Unit
R
C
VWM
VBR
VF
IR
S21
80
24
100
30
5.0
120
36
Ω
pF
V
V
V
µA
dB
6.0
-25
0.8
0.1
-30
0.5
±8
±15
kV
kV
Thermal Characteristics
(TA = 25 °C unless otherwise noted)
Operating Temperature Range
Storage Temperature Range
Power Dissipation Per Resistor
TJ
TSTG
PD
-40
-55
25
25
+85
+150
100
Reliable Electronic Solutions
Asia-Pacific:
TEL +886- (0)2 25624117 • FAX +886- (0)2 25624116
Europe:
TEL +41-41 768 5555 • FAX +41-41 768 5510
The Americas: TEL +1-951 781-5492 • FAX +1-951 781-5700
www.bourns.com
*RoHS Directive 2002/95/EC Jan 27 2003 including Annex
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
°C
°C
mW
2FAG-C15R - Integrated Passive & Active Device using CSP
Mechanical Characteristics
This is a Silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the Silicon die,
provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is
0.5 mm and the dimensions for the packaged device are shown below.
2.915 - 3.005
(0.115 - 0.118)
0.432 - 0.559
(0.017 - 0.022)
0.3
(0.012)
DIA.
C1
C2
C3
C4
0.435
(0.017)
C5
C6
1.285 - 1.375
(0.051 - 0.054)
B2
B1
E
T
E
L
O
S
B
O
A1
0.330 - 0.457
(0.013 - 0.018)
B3
A2
0.50
(0.020)
A3
A4
A5
0.435
(0.017)
0.25
(0.01)
0.180 - 0.280
(0.007 - 0.011)
Reliability Data
A6
0.180 - 0.280
(0.007 - 0.011)
DIMENSIONS =
MILLIMETERS
(INCHES)
Reliability data exists and continues to be gathered on an ongoing basis for Bourns Integrated Passive and Active Devices.
“Package level” testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy
Chain component is available from Bourns for this purpose (part number 2TAD-C25R). This is a 5 x 5 array featuring 0.5 mm pitch
solder bumps. The Distance to Neutral Point (DNP) on that component is similar to that of the 2FAG-C15R and is thus deemed a
comparable case for Thermal Cycle testing.
“Silicon level” reliability performance will be assured by similarity to other integrated passive CSP devices from Bourns.
Frequency Response
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2FAG-C15R - Integrated Passive & Active Device using CSP
Block Diagram
PCB Design and SMT Processing
The CSP device block diagram below includes the pin names and basic electrical
connections associated with each channel.
EXT1
R1:
100 ohms
Please consult the “Bourns Design
Guide Using CSP” for notes on PCB
design and SMT Processing.
INT1
How to Order
2 FAG - C15R ____
GND
Thinfilm
Model
E
T
E
L
O
S
B
O
Chipscale
No. of Solder Bumps
EXT2
INT2
R2:
100 ohms
EXT3
GND
EXT4
R3:
100 ohms
INT3
INT4
R4:
100 ohms
EXT5
R5:
100 ohms
INT5
GND
EXT6
INT6
R6:
100 ohms
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
Packaging Option
R = Tape and Reel
Packaged 3000 pcs. / 7 ” reel
Terminations
LF = Sn/Ag/Cu (lead free)
Blank = Sn/Pb
2FAG-C15R - Integrated Passive & Active Device using CSP
Device Pin Out
The Pin-Out for the device is shown below with the bumps facing up.
A
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
B
C
1
INT1
2
Pin Out
A1
A2
A3
A4
A5
A6
B1
B2
B3
INT2
3
Pin Out
C1
C2
C3
C4
C5
C6
Function
INT1
INT2
INT3
INT4
INT5
INT6
E
T
E
L
O
S
B
O
INT3
4
Function
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
GND
GND
GND
INT4
5
INT5
6
INT6
GND x 3
Packaging
The surface mount product will be dispensed in an 8 mm x 4 mm Tape and Reel format per EIA-481 standard.
TOP SIDE VIEW
(INTO COMPONENT POCKET)
DIMENSIONS =
0.3 ± 0.05
(.01 ± .002)
1.5 ± 0.1/-0
(.06 ± .004/-0)
DIA.
2.00 ± 0.05
(.08 ± .002)
R
MILLIMETERS
(INCHES)
4.0 ± 0.1
(.16 ± .004)
1.75 ± 0.10
(.07 ± .004)
0.3
MAX.
(0.01)
0.76 ± 0.1
(.03 ± .004)
8.0 ± 0.3
(.31 ± .01)
3.18 ± 0.1
(0.13 ± 0.004)
3.5 ± 0.05
(.14 ± .002)
1.52 ± 0.1
(.06 ± .004)
4.0 ± 0.1
(.16 ± .004)
ORIENTATION
OF COMPONENT
IN POCKET
R 0.25 TYP.
(0.010)
BACKSIDE FACING UP
COPYRIGHT© 2004, BOURNS, INC. LITHO IN U.S.A. 06/05 e/IPA0507
2FAG-C15R REV. B, 02/05
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.