isl78229ev1z user guide

User Guide 065
ISL78229EV1Z Evaluation Board User Guide
Description
Key Features
The ISL78229EV1Z board demonstrates the 2-phase
synchronous boost operation and PMBus™ functionalities of
the ISL78229. It verifies the high efficiency of synchronous
boost operation and all the features of the IC including input
Constant Current (CC) control, analog/digital tracking, diode
emulation, phase dropping, PMBus™ functions, etc.
• Input/output voltage withstands 55V DC and 60V transients
Specifications
• Selectable Continuous Conduction Mode (CCM), Diode
Emulation (DE) and Phase Dropping (PH_DROP) modes
This board has been configured and optimized for the following
operating conditions. Refer to “Operating Range” on page 3 for
more detailed descriptions.
• Comprehensive protections
• Input average Constant Current (CC) control loop
• PWM and analog track functions
• Forced PWM operation with negative current limiting
• External synchronization
• Selectable Hiccup or Latch-off fault responses
• I2C/PMBus™ compatible digital interface to control/monitor
operation parameters
• VIN_MIN = 7.5V (or lower, refer to “Operating Range”)
• VIN_TYP = 12V
• Boards can be stacked for parallel operations
• VIN_MAX = 30V (typical)
• Monitoring test points for key signals
• VOUT = 36V (typical)
• IOUT_MAX = 12A (typical)
References
• IIN_AVG_MAX = 41.5A (typical)
• ISL78229 Datasheet
• fSW = 200kHz
• AN1900, “USB to PMBus™ Adapter User Guide”
• PowerNavigator™ Software
Ordering Information
PART NUMBER
ISL78229EV1Z
• PowerNavigator User Guide
DESCRIPTION
ISL78229 Evaluation Board, ZLUSBEVAL3Z
adapter, USB cable
T1: VIN
VCC
J1
T2: GND
VCC
SGND
PVCC
VIN
PVCC
PGND
T3: VOUT
EN
J29
BOOT1
NTC
PMBus
signals
J50
UG1
PH1
SDA
SCL
SALERT
T4: GND
LG1
VCC
J7
RSEN1
ISEN1N
ISEN1P
TRACK
ISL78229
BOOT2
VCC
ATRK/DTRK
J17
UG2
PH2
VCC
RSEN2
LG2
HIC/LATCH
J18
ISEN2N
VCC
J23
ISEN2P
DE/PHDRP
FB
FIGURE 1. ISL78229EV1Z BLOCK DIAGRAM
January 6, 2016
UG065.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved
Intersil (and design) and PowerNavigator are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
User Guide 065
ISL78229EV1Z Evaluation Board
J56 (PIN 5-12): FOR BOARD STACKING TO CONNECT CONTROL SIGNALS
T1: VIN
J54: FOR BOARD STACKING TO CONNECT
POWER VIN AND GND
T2: GND
J23: GND-DE/PHDRP-VCC
J29: GND-EN- PIN3
(VIN_UVLO)
J21: PH1- GND
J20: PH2- GND
J50: CONNECT TO INTERSIL
PMBus™ DONGLE ZLUSBEVAL3Z
J39: OPTIONAL CONNECTOR FOR PMBus™ SIGNALS
T3: VOUT
T4: GND
J55: FOR BOARD STACKING
TO CONNECT
POWER VOUT AND GND
FIGURE 2. TOP VIEW OF THE ISL78229EV1Z
J52: FOR BOARD STACKING TO CONNECT POWER VIN AND GND
J57: FOR BOARD STACK TO CONNECT CONTROL SIGNALS
J53: FOR BOARD STACKING TO CONNECT POWER VOUT AND GND
FIGURE 3. BOTTOM VIEW OF THE ISL78229EV1Z
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UG065.1
January 6, 2016
User Guide 065
Recommended Equipment
• VIN_TYP = 12V
• 0V to 5V power supply with 0.5A source current capability
• VIN_MAX = 30V (typical). To keep VOUT regulated at 36V, the
maximum input voltage is typically 30V determined by the
minimum duty cycle.
• Load capable of 20A (or up to 30A)
• VOUT = 36V (typical)
• Function generator
• IOUT_MAX = 12A (typical at 12V VIN, depending on VIN due to
the IIN_AVG_MAX being 41.5A controlled by the input CC
control)
• 0V to 60V power supply with 45A source current capability
• 2 to 4 Digital Multimeters (DMM)
• 1 oscilloscope
Functional Description
The ISL78229EV1Z evaluation board pictures are shown in
Figures 2 and 3. The board supports a quick evaluation of various
features of the ISL78229.
• IIN_AVG_MAX = 41.5A (typical, controlled by the input CC
control)
• fSW = 200kHz
• The board is set in CCM mode by default with J23’s Pin 2
(DE/PHDRP) shorted to Pin 3 (GND) by the jumper.
The ISL78229EV1Z demonstrates ISL78229 as the controller of
a high efficiency 2-phase synchronous boost.
• The board is set to have Hiccup mode as the fault protection
response by default (can be changed via PMBus™) with J18’s
Pin 2 (HIC/LATCH) connected to VCC by the jumper.
The ISL78229EV1Z demonstrates the IC’s unique function of
accepting either digital or analog signals for the user to adjust
the reference voltage externally.
• Per phase inductor’s peak current limit is set at 38.5A (OC1:
cycle-by-cycle, continuously switching).
The ISL78229EV1Z demonstrates the ISL78229’s unique feature
of average Constant Current (CC) control for the input current. The
board can have the average input current as a controlled constant
without shutdown, which helps the user to optimize the system
with the power devices’ capability that is fully utilized by the
well-controlled constant input current.
• The board is set to accept an analog signal as the input (J17’s
Pin 2 (ATRK/DTRK) shorted to VCC by the jumper).
The ISL78229EV1Z has connector options to select Continuous
Conduction Mode (CCM), Diode Emulation (DE) and Phase
Dropping (PH_DROP) modes.
Combined with the Intersil PowerNavigator™ Software as the GUI
and the included USB to PMBus™ Adapter (dongle,
ZLUSBEVAL3Z), the user can conveniently evaluate the
ISL78229’s PMBus™ functionalities, which provides access to a
number of useful system control parameters and diagnostic
features.
Two ISL78229EV1Z evaluation boards can be stacked to
demonstrate 2 ICs operating in parallel to control a 4-phase
boost regulator.
Operating Range
• VIN_MIN = 7.5V or lower.
- The board starts up when the input voltage, VIN, rises above
10V and shuts down when VIN falls below 7.5V. This
10V/7.5V input voltage UVLO is determined by the resistor
divider (R36, R37) from the input voltage to the EN pin. These
VIN UVLO thresholds can be modified by changing the
resistor divider values.
- With the ISL78229’s EN pin (through J29’s center pin)
directly controlled by the external supply instead of the VIN
UVLO described above, the board can operate at VIN as low
as 5V to 6V while the output power is limited by IIN_MAX
(41.5A typical, controlled by the input CC control).
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• Per phase inductor’s peak current fault protection is set at
48.5A (OC2_PEAK fault, Hiccup response set by J18’s default
setting).
Quick Guide for Configurations
and Test Points
Figures 4 and 5 show the schematics of this evaluation board.
The “Bill of Materials” are listed on page 13. The layout
information of the board can be found in Figures 12 through 21.
Table 1 on page 11 shows the detailed descriptions for all the
connectors/monitor pins.
Key signals such as VCC, PVCC, SS, FB, COMP, EN, PGOOD,
CLKOUT, PHx, LGx, etc., are available at the monitoring pins for
easy measurement. Figures 22 through 55 show the
performance data taken with this evaluation board at the default
configurations.
The board setting can be changed by configuring the connection
of the corresponding connectors (header/pin type) or replacing
the resistors and/or capacitors populated on the board. Some
examples are described as follows:
• J23 is for selection of CCM/DE/PH_DROP modes (refer to
Table 2 in the ISL78229 datasheet). The board is set in CCM
mode by default. Do Not short J23 on both sides at the same
time.
- Short J23’s Pin 2 (DE/PHDRP) to VCC with jumper for the DE
mode
- Leave all J23’s 3 pins open for DE plus Phase Dropping
mode
- Short J23’s Pin 2 (DE/PHDRP) to GND for the CCM mode
(default board setting)
UG065.1
January 6, 2016
User Guide 065
• J18 is for selection of the fault protection response modes
(Hiccup/Latch-off) as the default (can be further changed via
PMBus™). Do Not short J18 on both sides at the same time.
- Short J18’s Pin 2 (HIC/LATCH) to VCC with the jumper for
default Hiccup fault response (default board setting)
- Short J18’s Pin 2 (HIC/LATCH) to GND with the jumper for
default Latch-off fault response
• The switching frequency on the ISL78229EV1Z is fixed at
200kHz. To change the frequency, replace R15, which is
connected between FSYNC and GND. Please refer to the
“Oscillator and Synchronization” section in the ISL78229
datasheet for details. The switching clock can be synchronized
with an external clock source applied at the FSYNC pin
(through J11). The external clock frequency range can be
50kHz to 1.1MHz.
• The output voltage of ISL78229EV1Z is fixed at 36V in default
setting. This can be changed by replacing the feedback resistor
R3 or R2. When changing the feedback resistor, the maximum
output current will be changed accordingly because the
maximum input current is controlled to be fixed by input CC.
• The input average CC limit (41.5A typical) can be adjusted by
two methods.
1. Replacing the resistor R1, which is connected to IMON pin.
For the setting of the average CC control, please refer to
“Average Current Sense for 2 Phases - IMON” and “Constant
Current Control (CC)” sections in the ISL78229 datasheet.
2. Via PMBus™ command CC_LIMIT, change the CC control
loop’s reference VREF_CC to different values. Please refer to
“CC_LIMIT (D5h)” command in the ISL78229 datasheet.
• The per phase inductor’s cycle-by-cycle peak current limit
(OC1) can be changed by replacing the current sense resistor
R11 (R12) and/or current sense gain setting resistors R9, R10,
R21, R22 (R7, R8, R19, R20) for the respective phases. Please
refer to “Current Sensing” and “Cycle-by-Cycle Peak
Overcurrent Limiting/Protection” sections in ISL78229
datasheet for details. Note: if these resistors are changed, the
R1 may need to be changed accordingly to keep the desired CC
control level.
Quick Start Guide
Setup of Test Equipment
As described in “Recommended Equipment” on page 3, prepare
2 power supplies, 1 electronic load, 2 to 4 DMMs and 1
oscilloscope.
• The first power supply 60V/45A (VIN power supply) will be used
for the VIN power rail.
• The second power supply 5V/0.5A (EN power supply) will be
used to supply bias for EN. This power supply is not necessary
if EN is connected to the VIN resistor divider with J29’s Pin 2
shorted with Pin 3 by the jumper.
• The electronic load (or resistive load) will be used as the load
for VOUT and should have a capability to sink 20A (or up to
30A).
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• The DMMs will be used to monitor output voltage, input voltage
and other signals such as PVCC, VCC, IMON, FB, etc. if
interested.
External Connections and Setup Before
Start-Up
• Connect the VIN power supply between VIN (T1) and GND (T2).
Before start-up, typically set the VIN power supply voltage to
12V. The power supply output should remain off before
start-up.
• Connect the EN power supply (if used) between EN and GND
using J29’s pin 2 (EN) and GND (pin 1). Typically, set the EN
power supply voltage in the range of 3V to 5V. The power
supply output should remain off before start-up.
• Connect the electronic load between VOUT (T3) and GND (T4).
Set the electronic load to 0A for the first start-up. The load
should remain off before start-up.
• Place the DMMs appropriately where the signals are to be
measured. The input and output voltage can be measured using
J54 and J30. (Note: To measure the voltage of high current
nodes, it is recommended to use a Kelvin connection to avoid
the effect of parasitic resistances of the connections. These
connections are supplied at J54 and J30.)
• Set the oscilloscope probes to monitor PH1 (J21), PH2 (J20),
VOUT (J30), IMON (J5), or any other signals.
Start-Up and Measurement
On the ISL78229EV1Z, the user can select one of the 3 basic
operation modes of CCM/DE/PH_DROP (refer to Table 2 in the
ISL78229 datasheet) by configuring J23.
1. CCM mode - The ISL78229EV1Z board is set in CCM mode by
default with J23’s Pin 2 (DE/PHDRP) shorted to Pin 3 (GND)
with the jumper.
• Before powering up, keep EN power supply and VIN power
supply outputs off. Keep the electronic load off.
• Set VIN power supply to 12V (or desired voltage). Turn on the
output of VIN power supply.
- Confirm the VIN voltage of the evaluation board is correct.
- Confirm the supply current of VIN power supply is small.
• Enable the output of the EN power supply.
- Confirm the evaluation board output voltage is 36V (typical).
- Confirm the CCM switching pulses at PH1 and PH2. The PH1
(PH2) switching frequency is 200kHz (typical).
• Increase the load to heavy load - Slowly increase the load from
0A to 10A. Keep the input voltage around 12V. The input
current is around 31A. Check to see if PH1/PH2 waveforms
are normal and if VOUT is regulated at 36V.
• Increase the load to CC mode - Continue to slowly increase the
load. At the same time, the user can monitor the IMON pin
voltage using the DMM or Oscilloscope. When the load
increases to around 14A, VOUT starts to drop below 36V (at
around 34.5V) and the IMON pin voltage reaches 1.6V. This
shows the CC loop is working and the input current is
controlled to be fixed at 41.5A (typical). When the load current
continues to increase, the input current is fixed at 41.5A
UG065.1
January 6, 2016
User Guide 065
(controlled by the CC loop) and the VOUT continues to drop. The
heavier the load, the lower the VOUT, which is the characteristic
of constant power (VIN is kept at 12V fixed and the input
current is controlled at 41.5A fixed).
• Power off
- Turn off the load to 0A
- Turn off the EN power supply
- Power down VIN power supply
2. DE mode plus Phase Drop mode - Remove the jumper at J23
and keep J23 open. The ISL78229’s DE/PHDRP pin is floating
and the IC is set in DE+PH_DROP mode.
• Enable the system and repeat the procedures in Step 1.
• Confirm the input voltage, output voltage, load current and
operation mode.
- At no load, only Phase 1 is switching and it is pulse skipping.
Phase 2 is dropped and not switching.
- When the load increases to a level when the IMON voltage is
higher than 1.15V, Phase 2 is added and switching.
- CC control at overloading has the same scenario described
in Step 1.
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3. DE mode - Short J23’s Pin 2 (DE/PHDRP) and Pin 3 (VCC) with
a jumper to set the IC in DE Mode. Leave J23 Pin 1 (GND)
floating.
• Enable the system and repeat the procedures in Step 1.
• Confirm the input voltage, output voltage, load current and
operation mode.
- At no load, either Phase 1, or Phase 2, or both is/are
switching at Discontinuous Conduction Mode (DCM) and
pulse skipping.
- When the load increases from 0 to a certain light load, both
Phase 1 and Phase 2 are switching at DCM mode.
- When the load is higher than a certain level (inductor current
is higher than the boundary current between DCM and CCM),
Phase 1 and Phase 2 will be switching at CCM mode.
- CC control at overloading has the same scenario described
in Step 1.
UG065.1
January 6, 2016
ZONE
R40
UG2
OPTIONAL INDUCTOR FOOTPRINTS
DNP
0
4
L22
LTR
DESCRIPTION
DATE
AP
Q4
UNNAMED_1_NCHANNEL_I303_G
BUK9Y6R0-60E
0
8199-3
R44
J24
6
R20
R8
432
E
PHASE2
E
ISEN2N
ISEN2P
J30
C53
0.022UF
C34
220UF
C32
220UF
C49
0.1UF
C47
0.1UF
C37
1UF
100V
C43
1UF
100V
C41
1UF
C39
0.1UF
C31
1UF
100V
GND
E
UNNAMED_1_SMCAP_I201_A
3
UNNAMED_1_JUMPER2_I338_IN2
OUT
1
2
3
1
2
3
3
J15
GND
UNNAMED_1_SMCAP_I446_A
DNP
E
R35
LG2
DNP
200PF
C27
1
432
T2
8199-2
D1
T4
1
OPEN
E
UNNAMED_1_SMCAP_I205_B
T3
1
3
2
Q2
UNNAMED_1_NCHANNEL_I302_G
4
V12P10
R46
R30
C14
Q1
UNNAMED_1_NCHANNEL_I186_G
4
J20
51.1
R19
51.1
R7
C2
1UF
C9
1UF
1UF
C6
C4
1UF
C7
220UF
C1
BUK9Y6R0-60E
MP BUK9Y6R0-60E
C45
MP
BUK9Y6R0-60E
PH2
1
8199-2
MP
T1
1
2
3
1
4.7UH
0.001
Q3
0.1UF
UNNAMED_1_POWERIND_I199_A
VOUT
OUT
4
R12
MP
UNNAMED_1_NCHANNEL_I173_G
C29
R41
L2
OPEN
J34
OUT
1
2
3
DNP
L21
VIN
220UF
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ISL78229EV1Z Schematic
8199-3
E
OUT
E
UG1
4
Q8
UNNAMED_1_NCHANNEL_I306_G
BUK9Y6R0-60E
1
2
3
UNNAMED_1_NCHANNEL_I189_G
Q7
0
C28
C35
220UF
C33
220UF
C52
0.1UF
C48
0.1UF
C38
1UF
100V
C44
1UF
100V
C42
1UF
100V
1UF
C40
C46
OPEN
J25
432
R22
User Guide 065
432
E
DNP
PHASE1
E
UNNAMED_1_SMCAP_I449_A
UNNAMED_1_SMCAP_I198_A
3
UNNAMED_1_JUMPER2_I337_IN2
UNNAMED_1_JUMPER2_I337_IN1
D2
V12P10
R47
E
R38
LG1
J16
3
2
3
R31
1
Q6
UNNAMED_1_NCHANNEL_I305_G
R45
C16
200PF
BUK9Y6R0-60E
MP
1
2
3
4
1
2
3
51.1
R21
R9
51.1
Q5
UNNAMED_1_NCHANNEL_I191_G
4
E
R10
MP
BUK9Y6R0-60E
J21
0.001
MP
4.7UH
1
2
3
BUK9Y6R0-60E
C30
PH1
UNNAMED_1_POWERIND_I207_A
DNP
L1
R11
0.1UF
R43
MP
C36
R42
0
0.1UF
L11
DNP
4
DNP
J35
L12
OPEN
OPTIONAL INDUCTOR FOOTPRINTS
E
J1
J18
1
3
E
ISEN1P
ISEN1N
E
2
HIC/LATCH
3
R4
2
E
HEADER CONNECTOR ON TOP
C20
ISEN2P
ISEN2N
J19
20K
R23
VCC
0.1UF
J31
C17
J10
FB
1UF
C15
C21
OPEN
C5
J56
1
3
5
7
9
11
0.1UF
UNNAMED_1_SMCAP_I55_A
97.6K
R2
DNP
VOUT
ATRK/DTRK
J17
1
VCC
0.022UF
E
UNNAMED_1_CONN12_I480_IN1
1
2
3
4
5
6
7
8
9
10
11
12
2
4
6
8
10
12
FSYNC
CLKOUT
SS
COMP
BAT46W-V
1
2
2
BAT46W-V
SDA
1 2
3 4
5 6
C51
1
2
3
4
J39-1
SCL
VI2C_EXT
VI2C_EXT
EN
EN
E
SCL
GND
GND
SDA
SDA
OPTIONAL CONNECTOR FOR PMBUS SIGNALS
CONNECTOR FOR INTERSIL PMBUS DONGLE - ZLUSBEVAL3Z
3.24K
VIN
J32
200K
UNNAMED_1_SMCAP_I142_A
C50
100PF
R37
DRAWN BY:
E
E
E
DATE:
TIM KLEMANN
1
SALERT
27.4K
2
J29
6800PF
1000PF
C23
R32
J22
470K
R29
100K
R28
C54
1000PF
3
R36
UNNAMED_1_JUMPER3_I411_IN3
J40
R39
SDA
SCL
E
EN
SALERT
1
J50
SALERT
10UF
J11
SCL
J51
10K
10K
VI2C_EXT
D3
RBLANK
UNNAMED_1_JUMPER3_I384_IN2
R18
E
PLL_COMP
SDA
R17
J26
NTC
10K
2
0.47UF
CLKOUT
E
R16
3
E
E
PH2
E
VCC
C22
UNNAMED_1_SMCAP_I230_B
1.5
11
12
13
14
15
16
17
18
19
20
1
R15
J9
2
J14
1
1
J7
2
J12
2
E
EP
FB
UNNAMED_1_SMRES_I434_B
E
10K
41
SS
SOCKET CONNECTOR ON BOTTOM
1
PGOOD
E
UG2
BOOT2
R6
TRACK
1
3
5
7
5.11
PH2
J28
3
3
3
VCC
2 1
4 3
6 5
8 7
R48
PVCC
GND
LG2
R33
ADDR2
2
4
6
8
EN
PH1
LG1
40.2K
VCC
UG1
D4
ADDR1
VCC
FSYNC
VCC
J5
0.47UF
COMP
CLKOUT
C3
0.1UF
30
29
28
27
26
25
24
23
22
21
IMON
J37
TRACK
57.6K
U1
ISL78229ARZ
SGND
SDA
SCL
SALERT
NTC
DE/PHDRP
RBLANK
PLLCOMP
EN
CLKOUT
E
IMON
IMON
BOOT1
UG1
PH1
LG1
PVCC
PGND
LG2
PH2
UG2
BOOT2
10UF
SS
0.022UF
R1
1.5
UNNAMED_1_ISL78229_I433_1
SLOPE
FB
COMP
SS
IMON
TRACK
ADDR1
ADDR2
PGOOD
FSYNC
UNNAMED_1_SMCAP_I156_B
C26
E
C10
1
2
3
4
5
6
7
8
9
10
61.9K
E
36K
J57
C24
R34
E
R13
3.3K
0.1UF
E
40
39
38
37
36
35
34
33
32
31
J13
UNNAMED_1_SMCAP_I143_A
C25
R5
UNNAMED_1_ISL78229_I433_31
VCC
RDT
ATRK/DTRK
HIC/LATCH
NC
ISEN2P
ISEN2N
ISEN1P
ISEN1N
VIN
C8
UNNAMED_1_ISL78229_I433_39
10
BOOT1
COMP
J8
R3
4.53K
FB
J27
R14
PVCC
C11
0.015UF
E
E
E
ENGINEER:
UG065.1
January 6, 2016
DE/PHDRP
DRAWING TITLE
EVALUATION BOARD
JUN LIU
ISL78229
SIZE
VCC
3
E
2
1
J23
FIGURE 4. ISL78229EV1Z BOARD SCHEMATIC - PAGE 1
SCHEMATIC
08/11/2015
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DRAWING NO.
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ISL78229EV1Z
FILENAME:
~/ISL78229/ISL78229EV1ZE
SHEET
1
OF
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ISL78229EV1Z Schematic (Continued)
VOUT
VIN
IN
IN
J54
7
1
3
5
7
9
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19
1
2
3
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J52
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4
6
8
10
12
14
16
18
20
TSM-110-03-L-DV
1
3
5
7
9
11
13
15
17
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
J53
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
J55
2
4
6
8
10
12
14
16
ESQ-108-33-L-D
1
3
5
7
9
11
13
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
4
6
8
10
12
14
16
TSM-108-03-L-DV
ESQ-110-33-L-D
GND
GND
IN
IN
User Guide 065
FIGURE 5. ISL78229EV1Z BOARD SCHEMATIC - PAGE 2
UG065.1
January 6, 2016
User Guide 065
Stack Two Boards for Parallel
Operation
• Short board #1’s J56’s Pin 3 and Pin 4 with the jumper to
connect board #1’s CLKOUT signal to the board #2’s FSYNC
input.
Two ISL78229EV1Z boards can be stacked. This allows for two
ISL78229s to operate in parallel achievng a 4-phase interleaved
boost regulator.
• Short board #2’s J56’s Pin 1 and Pin 2 with the jumper to
connect board #2’s FSYNC input to the board #1’s CLKOUT
signal.
The ISL78229EV1Z has connectors to stack multiple boards for
parallel operation. Figures 6 and 7 show two ISL78229EV1Z
boards stacked. To stack two boards properly, align the two
boards with one on top of the other, and plug in the 3 groups of
connectors described in the following (first 3 bullet points).
Directions for stacking board #1 on top of board #2:
• External setup:
- Connect the input VIN power supply to T1/T2 of both boards.
- Connect the load to T3/T4 of both boards. Since both
boards’ EN pin signals are tied together, only one external
EN power supply (3V to 5V) is needed for enable/disable
through J29’s Pins 1-2 of top board.
• Plug board #2’s J54 (header/pin type, on board top) into board
#1’s J52 (socket type, on board bottom) to connect both
boards’ inputs together.
• Power Up:
- Keep EN power supply off.
- Turn on the VIN power supply.
- Then turn on the EN power supply.
• Plug board #2’s J55 (header/pin type, on board top) into board
#1’s J53 (socket type, on board bottom) to connect both
boards’ outputs together.
• Plug board #2’s J56’s Pins 5-12 (header/pin type, on board
top) into board #1’s J57 (socket type, 8 pins, on board bottom)
to connect both boards’ signals needed for the boards’ parallel
operation, e.g., TRACK, GND, EN, SS, IMON, FB and COMP
signals.
• Power Down:
- Turn off the EN power supply.
- Then turn off the VIN power supply.
Connect EN power supply (3V to 5V) to top board’s J29’s
Pin 2 (EN) and Pin 1 (GND) to enable/disable the boards.
Note: Remove both boards’ default jumpers at J29’s
Pin 2 to Pin 3.
Short one board’s (top board) J56’s Pin 3 and Pin 4
with jumper to connect its CLKOUT signal to the
other board’s FSYNC input.
Short one board (bottom board) J56’s Pin 1 and Pin 2
with jumper to connect its FSYNC input to the other
board’s CLKOUT signal.
Bottom board’s J56’s Pins 5-12 (header/pin type)
plugged into top board’s J57 (socket type)
to connect both boards’ connect control signals
Bottom board’s J54 (header/pin type) plugged
into top board’s J52 (socket type) to connect
both boards’ power inputs (VIN and GND) together.
FIGURE 6. STACK TWO ISL78229EV1Z FOR PARALLEL OPERATION TO ACHIEVE 4-PHASE INTERLEAVED BOOST REGULATOR (VIEW FROM
INPUTS SIDE)
Bottom board’s J55 (header/pin type) plugged
into top board’s J53 (socket type) to
connect both boards’ power
outputs (VOUT and GND) together.
FIGURE 7. STACK TWO ISL78229EV1Z FOR PARALLEL OPERATION TO ACHIEVE 4-PHASE INTERLEAVED BOOST REGULATOR (VIEW FROM
OUTPUTS SIDE)
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User Guide 065
Evaluate PMBus™ Functions
The ISL78229EV1Z can demonstrate all the ISL78229’s
PMBus™ functions with Intersil’s PMBus™ evaluation software,
PowerNavigator™ GUI and the included ZLUSBEVAL3Z dongle
(USB-to-PMBus™ adapter board).
Hardware Setup
Figures 8 and 9 show the setup of the ISL78229EV1Z connected
with the ZLUSBEVAL3Z dongle (user guide available as AN1900).
• Connect the included ZLUSBEVAL3Z dongle to
ISL78229EV1Z’s J50 as Figure 8 shows.
• With the included USB cable, connect the ZLUSBEVAL3Z
dongle to the host PC
Software Setup
The PowerNavigator™ evaluation software can operate in
Windows XP, 7 or 8 operating systems. Install the evaluation
software from the following Intersil website:
http://www.intersil.com/powernavigator
Refer to PowerNavigator User Guide to see instructions how to
use th GUI. Also PowerNavigator™ tutorial videos are available on
the Intersil website. www.intersil.com/powernavigator
Note the GUI is designed to support most of the Intersil parts with
PMBus™ functions. Some of the GUI features and PMBus™
functions are not supported by ISL78229. Only use the ISL78229
related features.
CONNECT THE ZLUSBEVAL3Z DONGLE CABLE TO HOST PC
CONNECT THE ZLUSBEVAL3Z DONGLE TO J50 OF THE ISL78229EV1Z
FIGURE 8. ISL78229EV1Z CONNECTED TO INTERSIL DONGLE FOR GUI (TOP VIEW)
FIGURE 9. ISL78229EV1Z CONNECTED TO INTERSIL DONGLE FOR GUI (BOTTOM VIEW)
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User Guide 065
PROCEDURE TO OPERATE THE PMBUS™ DEMO
1. Install PowerNavigator™ software to the host PC from the
following Intersil website: www.intersil.com/powernavigator
2. Connect the ZLUSBEVAL3Z dongle to the ISL78229EV1Z
board as described in “Hardware Setup” on page 9.
3. Connect supplied USB cable from the host PC’s USB port to
the ZLUSBEVAL3Z dongle as described in “Hardware Setup”
on page 9.
4. Set the VIN power supply and the EN power supply output to
off (Refer to “Setup of Test Equipment” on page 4 for the
mentioned power supplies). Keep the electronic load off.
5. Connect the VIN power supply between VIN (T1) and GND (T2).
6. Connect the EN power supply (if used, typically 3V to 5V)
between EN and GND using J29’s Pin 2 (EN) and Pin 1 (GND).
7. Connect the electronic load between VOUT (T3) and GND (T4).
8. Set the VIN power supply to 12V (or desired voltage). Turn on
the output of the VIN power supply. Keep the EN power supply
output off.
9. Enable the output of the EN power supply. Confirm the
ISL78229EV1Z board output is regulated at 36V.
10. Launch the PowerNavigator™ software.
11. Monitor and configure the ISL78229EV1Z board using the
PMBus™ commands in the evaluation software.
PCB Layout Guidelines
For a DC/DC converter design, the PCB layout is very important to
ensure the desired performance.
1. Place input ceramic capacitors as close as possible to the IC's
VIN and PGND/SGND pins.
2. Place the output ceramic capacitors as close as possible to
the power MOSFET. Keep this loop (output ceramic capacitor
and MOSFETs for each phase) as small as possible to reduce
voltage spikes induced by the trace parasitic inductances
when MOSFETs are switching ON and OFF.
3. Place the output aluminum capacitors close to power
MOSFETs also.
4. Keep the phase node copper area small but large enough to
handle the load current.
5. Place the input aluminum and some ceramic capacitors close
to the input inductors and power MOSFETs.
FIGURE 10. RECOMMENDED LAYOUT PATTERN FOR VIAS IN THE
IC BOTTOM PAD
7. Place the 10µF decoupling ceramic capacitor at the PVCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
8. Place the 1µF decoupling ceramic capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
9. Keep the bootstrap capacitor as close as possible to the IC.
10. Keep the driver traces as short as possible and with relatively
large width (25 mil to 40 mil is recommended) and avoid
using via or minimal number of vias in the driver path to
achieve the lowest impedance.
11. Place the current sense setting resistors and the filter
capacitor (shown as RSETxB, RBIASxB and CISENx in the
ISL78229 datasheet) as close as possible to the IC. Keep
each pair of the traces close to each other to avoid undesired
switching noise injections.
12. The current sensing traces must be laid out very carefully
since they carry tiny signals with only tens of mV.
13. For the current sensing traces close to the power sense
resistor (RSENx), the layout pattern shown in Figure 11 is
recommended. Assuming the RSENx is placed in the top layer
(red), route one current sense connection from the middle of
one RSENx pad in the top layer under the resistor (red trace).
For the other current sensing trace, from the middle of the
other pad on RSENx in top layer, after a short distance, via
down to the second layer and route this trace right under the
top layer current sense trace.
6. Place multiple vias under the thermal pad of the IC. The
thermal pad should be connected to the ground copper plane
with as large an area as possible in multiple layers to
effectively reduce the thermal impedance. Figure 10 shows
the layout example for vias in the IC bottom pad.
FIGURE 11. RECOMMENDED LAYOUT PATTERN FOR CURRENT
SENSE TRACES REGULATOR
14. Keep the current sensing traces far from the noisy traces like
gate driving traces (LGx, UGx and PHx), phase nodes in power
stage, BOOTx signals, output switching pulse currents, driving
bias traces and input inductor ripple current signals, etc.
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User Guide 065
TABLE 1. CONNECTOR/MONITOR-PIN DESCRIPTIONS
CONNECTOR
/TEST POINT
SIGNAL NAME
DESCRIPTION
T1
VIN
Positive power input terminal for the boost regulator input.
T2
GND
Power ground input terminal for the boost regulator input.
T3
VOUT
Positive power output terminal for the boost regulator output.
T4
GND
Power ground output terminal for the boost regulator output.
J1
VIN, VIN_PIN
Short with jumper to connect input voltage to the ISL78229 IC VIN pin.
J5
GND - IMON
Test point to monitor the IMON voltage.
A jumper can be added to short the IMON pin to ground to disable the constant current
limit (41.5A typical).
To adjust the constant current control level, replace resistor (R1) between IMON and GND.
J7
GND (Pin 1), TRACK (Pin 2), VCC (Pin 3)
Pin 2 is for monitoring TRACK voltage. It can also be used to inject a tracking reference
signal to the TRACK pin.
When the TRACK function is not used, short Pin 2 (TRACK) and Pin 2 (VCC) with the
jumper. Do Not short both sides at the same time.
J8
GND, FB
Test point to monitor FB voltage (Do Not short with jumper).
J9
GND, PGOOD
Test point to monitor PGOOD voltage.
J10
GND, VCC
Test point to monitor VCC voltage (Do Not short with jumper).
J11
GND, FSYNC
External synchronization clock input terminal or test point for the FSYNC pin voltage (Do
Not short with jumper).
J12
GND (Pin 1), ADDR1 (Pin 2), VCC (Pin 3)
PMBus™ Address setting pins to pull ADDR1 to ground or VCC (Do Not short both sides at
the same time).
J13
SLOPE, GND
Test point to monitor IMON voltage (Do Not short with jumper).
J14
GND (Pin 1), ADDR2 (Pin 2), VCC (Pin 3)
PMBus™ Address setting pins to pull ADDR2 to ground or VCC (Do Not short both sides at
the same time).
J15
Test points to monitor Phase 2 current sense input signals.
J16
Test points to monitor Phase 1 current sense input signals.
J17
VCC (Pin 1), ATRK/DTRK (Pin 2), GND (Pin 3) TRACK input mode (analog tracking or digital tracking input) selection pins. Connect to
VCC with jumper for analog tracking input or short to GND for digital tracking input (Do
Not short both sides at the same time).
J18
VCC (Pin 1), HIC/LATCH (Pin 2), GND (Pin 3) Default fault protection response mode (Hiccup/Latch-off) selection pins. Connect to VCC
with jumper for Hiccup fault response as default or short to GND for Latch-off fault
response as default (Do Not short both sides at the same time).
J19
RDT, GND
Test point to monitor the RDT voltage (Do Not short with jumper).
J20
GND, PH2
Test point to monitor the PH2 waveform (Do Not short with jumper).
J21
GND, PH1
Test point to monitor the PH1 waveform (Do Not short with jumper).
J22
GND, NTC
Test point to monitor the NTC voltage. Do Not short with jumper (shorting to ground will
trigger a NTC fault protection).
J23
VCC (Pin 1), DE/PHDRP (Pin 2), GND (Pin 3) CCM/DE/PH_DROP modes selection pins. Connect to VCC with jumper for DE mode;
Leave all the 3 pins open for DE plus Phase Dropping mode; Short to GND for CCM mode
(Do Not short both sides at the same time).
J24
GND, LG2
Test point to monitor the LG2 waveform (Do Not short with jumper).
J25
GND, LG1
Test point to monitor the LG1 waveform (Do Not short with jumper).
J26
GND, BOOT2
Test point to monitor the BOOT2 waveform (Do Not short with jumper).
J27
GND, BOOT1
Test point to monitor the BOOT1 waveform (Do Not short with jumper).
J28
GND, RBLANK
Test point to monitor RBLANK voltage (Do Not short with jumper).
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User Guide 065
TABLE 1. CONNECTOR/MONITOR-PIN DESCRIPTIONS (Continued)
CONNECTOR
/TEST POINT
SIGNAL NAME
DESCRIPTION
J29
GND (Pin 1), EN (Pin 2), Pin 3 (For VIN_UVLO) Enable/Disable options.
Pin 2 (EN) can be used to apply external signal to enable and disable the IC.
To connect Pin 2 (EN) to Pin 3 with jumper connects the resistor divider (R36, R37, dividing
input voltage) output to the EN pin, in such a way the part has an input voltage UVLO. The
board starts up when input voltage VIN > 10V and shuts down when VIN < 7.5V. This
10V/7.5V VIN UVLO setting can be changed by changing the resistor divider values. Do Not
short both sides at the same time.
J30
GND, VOUT
Test point to monitor output voltage VOUT (Do Not short with jumper).
J31
COMP, GND
Test point to monitor COMP voltage (Do Not short with jumper).
J32
GND, PLLCOMP
Test point to monitor PLLCOMP voltage (Do Not short with jumper).
J34
PH2, UG2
Test point to monitor UG2-PH2 voltage waveforms (Do Not short with jumper). Differential
voltage probe is required to monitor UG2-PH2 waveforms.
J35
PH1, UG1
Test point to monitor UG1-PH1 voltage waveforms (Do Not short with jumper). Differential
voltage probe is required to monitor UG1-PH1 waveforms.
J37
GND, PVCC
Test point to monitor PVCC voltage (Do Not short with jumper).
J39
J40
Optional connector for PMBus™ signals.
GND, CLKOUT
Test point to monitor CLKOUT voltage (Do Not short with jumper).
J50
Connector to connect to Intersil PMBus™ dongle ZLUSBEVAL3Z.
J51
VI2C_EX (Pin 1), Pin 2, VCC (Pin 3)
PMBus™/I2C bus pull-up options. Connect Pin 2 to Pin 3 (VCC) with the jumper to pull up
the I2C bus with VCC voltage. Connect Pin 2 to Pin 1 (VI2C_EX) with the jumper to pull up
the I2C bus with externally available voltage VI2C_EX. Do Not short both sides at the same
time.
J52
VIN, GND
Socket type connector for power input used to stack boards. It is plugged in by J54
(header/pin type connector) of the other board.
J53
VOUT, GND
Socket type connector for power output used to stack boards. It is plugged in by J55
(header/pin type connector) of the other board.
J54
VIN, GND
Header/pin type connector for power input used to stack boards. It is plugged to J52
(socket type connector) of the other board. Pins 1-10: VIN, Pins 11-20: GND.
J55
VOUT, GND
Header/pin type connector for power output used to stack boards. It is plugged in by J53
(socket type connector) of the other board. Pins 1-8: VOUT, Pins 9-16: GND.
J56
Pin 1: FSYNC if Pin 1 and Pin 2 shorted by Header/pin type connector on board top side for connections of signals needed for the
jumper; CLKOUT if Pin 3 and Pin 4 shorted by boards’ parallel operation. Its Pins 5-12 are used to plug into another board’s J57 (socket
type connector, 8 pins) with both boards stacked. Check the description in J57 for details.
jumper.
Pin 2: FSYNC
Pin 3: FSYNC if Pin 1 and Pin 2 shorted by
jumper; CLKOUT if Pin 3 and Pin 4 shorted by
jumper.
Pin 4: CLKOUT
Pin 5: FSYNC if Pin 1 and Pin 2 shorted by
jumper; CLKOUT if Pin 3 and Pin 4 shorted by
jumper.
Pin 6: TRACK
Pin 7: EN
Pin 8: GND
Pin 9: IMON
Pin 10: SS
Pin 11: COMP
Pin 12: FB
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User Guide 065
TABLE 1. CONNECTOR/MONITOR-PIN DESCRIPTIONS (Continued)
CONNECTOR
/TEST POINT
J57
SIGNAL NAME
DESCRIPTION
Socket type connector on the board’s bottom side for connections of the signals needed
for the boards’ parallel operation. With it being plugged by Pins 5-12 of J56 (header/pin
Pin 2: FSYNC if J56 Pin 1 and Pin 2 shorted type connector) of the other board, the two boards’ signals of TRACK, GND, EN, SS, IMON,
FB and COMP are connected respectively.
by jumper; CLKOUT if J56 Pin 3 and Pin 4
With board #1, J56 Pin 3 and Pin 4 are shorted by the jumper, and board #2 J56 Pin 1
shorted by jumper.
and Pin 2 are shorted by the jumper, board #1 CLKOUT is connected to board #2 FSYNC.
With board #1, J56 Pin 1 and Pin 2 are shorted by the jumper, and board #2 J56 Pin 3
Pin 3: GND
and Pin 4 are shorted by the jumper, board #2 CLKOUT is connected to board #1 FSYNC.
Pin 4: EN
Pin 5: SS
Pin 6: IMON
Pin 7: FB
Pin 8: COMP
Pin 1: TRACK
Bill of Materials
REFERENCE
DESIGNATOR
MANUFACTURER
PART NUMBER
MANUFACTURER
DESCRIPTION
C1, C7, C32-C35
EKZE800ELL221MK20S
UNITED CHEMI-CON
Capacitor, Alum. Electrolytic, RADIAL, 12.5x20, 220µF, 80V, 20%,
ROHS
C10
Various
Various
Capacitor, Ceramic, SMD, 0603, 0.022µF, 50V,10%, X7R, ROHS
C11
Various
Various
Capacitor, Ceramic, SMD, 0603, 0.015µF, 50V, 10%, X7R, ROHS
C14, C16
Various
Various
Capacitor, Ceramic, SMD, 0603, 200pF, 50V, 10%, NP0, ROHS
C15
Various
Various
Capacitor, Ceramic, SMD, 0603, 1.0µF, 16V, 10%, X7R, ROHS
C2, C4, C6, C9, C37-C44
Various
Various
Capacitor, Ceramic, SMD, 1206, 1µF, 100V, 10%, X7R, ROHS
C20, C31, C36, C45-C49,
C52
Various
Various
Capacitor, Ceramic, SMD, 0805, 0.1µF, 100V, 10%, X7R, ROHS
C21, C53
Various
Various
Capacitor, Ceramic, SMD, 0603, 0.022µF, 100V, 10%, X7R, ROHS
C22, C24
Various
Various
Capacitor, Ceramic, SMD, 0603, 0.47µF, 16V, 10%, X7R, ROHS
C23, C54
Various
Various
Capacitor, Ceramic, SMD, 0603, 1000pF, 50V, 10%, X7R, ROHS
C25
Various
Various
Capacitor, Ceramic, SMD, 0603, 6800pF, 50V, 10%, X7R, ROHS
C26, C51
Various
Various
Capacitor, Ceramic, SMD, 0805, 10µF, 6.3V, 10%, X5R, ROHS
C3, C8, C17
Various
Various
Capacitor, Ceramic, SMD, 0603, 0.1µF, 50V, 10%, X7R, ROHS
C5, C27-C30
Various
Various
Capacitor, Ceramic, SMD, 0603, DNP-PLACE HOLDER, ROHS
C50
Various
Various
Capacitor, Ceramic, SMD, 0603, 100pF, 50V, 5%, C0G, ROHS
D1, D2
V12P10-M3/86A
VISHAY
Diode-Schottky, SMD, TO-277A(SMPC), 100V, 12A, ROHS
D3, D4
BAT46W-E3-08
DIODES INC.
Diode-Schottky, SMD, SOD-123, 100V, 0.15A, ROHS
Four corners
PMSSS 440 0025 PH
BUILDING FASTENERS
SCREW, 4-40x1/4in, PHILLIPS, PANHEAD, STAINLESS, ROHS
Four corners
2204
KEYSTONE
STANDOFF, 4-40x3/4in, HEX, ALUMINUM, 0.25 OD, ROHS
J1, J5, J8-J11, J13, J15, J16, 69190-202HLF
J19-J22, J24-J28, J30-J32,
J34, J35, J37, J40
BERG/FCI
Connector-Header, 1x2, RETENTIVE, 2.54mm Pitch, ROHS
J39
22-11-2042
MOLEX
Connector-Header, 1x4, SOLID, 2.54mm Pitch, VERTICAL, FRICTION
LOCK, GOLD
J50
TSW-103-08-T-D-RA
SAMTEC
Connector-Header, 2x3, BRKAWY, 2.54mm Pitch, TIN, RIGHT ANGLE,
ROHS
J52
ESQ-110-33-L-D
SAMTEC
Connector-Socket, ELEVATED, Through-Hole, 2x10, DUALROW,
2.54mm Pitch, ROHS
Submit Document Feedback
13
UG065.1
January 6, 2016
User Guide 065
Bill of Materials (Continued)
REFERENCE
DESIGNATOR
MANUFACTURER
PART NUMBER
MANUFACTURER
DESCRIPTION
J53
ESQ-108-33-L-D
SAMTEC
Connector-Socket, ELEVATED, Through-Hole, 2x8, DUALROW,
2.54mm Pitch, ROHS
J54
TSM-110-03-L-DV
SAMTEC
Connector-Header, SMD, 2x10, 2.54mm Pitch, VERTICAL, ROHS
J55
TSM-108-03-L-DV
SAMTEC
Connector-Header, SMD, 2x8, 2.54mm Pitch, VERTICAL, ROHS
J56
TSM-106-03-L-DV
SAMTEC
Connector-Header, SMD, 2x6, 2.54mm Pitch, VERTICAL, ROHS
J57
ESQ-104-33-L-D
SAMTEC
Connector-Socket, ELEVATED, Through-Hole, 2x4, DUALROW, 2.54mm
Pitch, ROHS
BERG/FCI
Connector-Header, 1x3, BREAKAWAY, 1x36, 2.54mm Pitch, ROHS
J7, J12, J14, J17, J18, J23, 68000-236HLF
J29, J51
Jumpers shorting:
J1,
J12-Pins 1-2,
J14-Pins 1-2,
J17-Pins 1-2,
J18-Pins 1-2,
J23-Pins 2-3,
J29-Pins 2-3
SPC02SYAN
SULLINS
Connector-Jumper, SHORTING, 2-PIN, BLACK, GOLD, ROHS
L1, L2
SER2915H-472KLB
COILCRAFT
Power Inductor, SMD, 27x19.1, 4.7µH, 20%, 1.8mΩ, ROHS
L11, L12, L21, L22
Power Inductor, SMD, DNP-PLACE HOLDER
Q1-Q8
BUK9Y6R0-60E
NXP SEMICONDUCTOR
Transistor-MOSFET, N-CHANNEL, SMD, 56LFPAK, 60V, 100A, 6mΩ,
ROHS
R1
Various
Various
Resistor, SMD, 0603, 57.6kΩ, 1%, ROHS
R11, R12
WSLP25121L000FEA
VISHAY/DALE
Resistor, Current Sense, SMD, 2512, 0.001Ω, 3W, 1%, ROHS
R13
Various
Various
Resistor, SMD, 0603, 36kΩ, 1%, ROHS
R14
Various
Various
Resistor, SMD, 0603, 10Ω, 1%, ROHS
R15
Various
Various
Resistor, SMD, 0603, 61.9kΩ, 1%, ROHS
R2
Various
Various
Resistor, SMD, 0603, 97.6kΩ, 1%, ROHS
R23
Various
Various
Resistor, SMD, 0603, 20kΩ, 1%, ROHS
R28
Various
Various
Resistor, SMD, 0603, 100kΩ, 1%, ROHS
R29
NTCS0805E3474FXT
VISHAY/BC
COMPONENTS
Thermistor-NTC, SMD, 0805, 470k, 0.21W, 1%, B = 4025k, ROHS
R3
Various
Various
Resistor, SMD, 0603, 4.53kΩ, 1%, ROHS
R30, R31, R35, R38
Various
Various
Resistor, SMD, 0603, 3Ω, 1%, ROHS
R32
Various
Various
Resistor, SMD, 0603, 40.2kΩ, 1%, ROHS
R33, R34
Various
Various
Resistor, SMD, 0603, 1.5Ω, 1%, ROHS
R36
Various
Various
Resistor, SMD, 0603, 200kΩ, 1%, ROHS
R37
Various
Various
Resistor, SMD, 0603, 27.4kΩ, 1%, ROHS
R39
Various
Various
Resistor, SMD, 0603, 3.24kΩ, 1%, ROHS
R4
R40-R43
Resistor, SMD, 0603, DNP-PLACE HOLDER
Various
Various
R44, R45, R46, R47
Resistor, SMD, 0603, 0Ω, ROHS
Resistor, SMD, 1206, DNP-PLACE HOLDER
R48
Various
Various
Resistor, SMD, 0603, 5.11Ω, 1%, ROHS
R5
Various
Various
Resistor, SMD, 0603, 3.3kΩ, 1%, ROHS
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User Guide 065
Bill of Materials (Continued)
REFERENCE
DESIGNATOR
MANUFACTURER
PART NUMBER
MANUFACTURER
DESCRIPTION
R6, R16, R17, R18
Various
Various
Resistor, SMD, 0603, 10kΩ, 1%, ROHS
R7, R9, R19, R21
Various
Various
Resistor, SMD, 0603, 51.1Ω, 1%, ROHS
R8, R10, R20, R22
Various
Various
Resistor, SMD, 0603, 432Ω, 1%, ROHS
T1, T3
8199-2
KEYSTONE
Connector, Screw Terminal, Through-Hole, SNAP-IN, 30A, RED,
BRASS, ROHS
T2, T4
8199-3
KEYSTONE
Connector, Screw Terminal, Through-Hole, SNAP-IN, 30A, BLACK,
BRASS, ROHS
U1
ISL78229ARZ
INTERSIL
IC-2 Phase Boost Controller, 40-Pin, WFQFN, 6x6, ROHS
ISL78229EV1ZREVEPCB
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PCB, ROHS
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User Guide 065
Board Layout
FIGURE 12. TOP COMPONENT ASSEMBLY
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User Guide 065
Board Layout (Continued)
FIGURE 13. TOP SILKSCREEN AND PIN PADS
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User Guide 065
Board Layout (Continued)
FIGURE 14. TOP LAYER
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User Guide 065
Board Layout (Continued)
FIGURE 15. 2nd LAYER
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User Guide 065
Board Layout (Continued)
FIGURE 16. 3rd LAYER
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User Guide 065
Board Layout (Continued)
FIGURE 17. 4th LAYER
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User Guide 065
Board Layout (Continued)
FIGURE 18. 5th LAYER
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User Guide 065
Board Layout (Continued)
FIGURE 19. BOTTOM LAYER
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User Guide 065
Board Layout (Continued)
FIGURE 20. BOTTOM SILKSREEN AND PIN PADS
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User Guide 065
Board Layout (Continued)
FIGURE 21. BOTTOM SILKSREEN AND PIN PADS (MIRRORED)
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User Guide 065
Performance Curves
EFFICIENCY (%)
and TA = +25°C
100
95
90
85
80
75
70
65
60
55
50
0.01
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V, VOUT = 36V
VOUT 1.0V/DIV WITH 36V OFFSET
IL1 5.0A/DIV
DE WITH PHASE DROP
DE WITHOUT PHASE DROP
PH1 30.0V/DIV
CCM
0.10
1.00
10.00
100.00
SS 3.0V/DIV
LOAD CURRENT (A)
NOTE: (See Typical Application in Figure 4 in the ISL78229 datasheet.)
FIGURE 22. EFFICIENCY vs LOAD, 2-PHASE BOOST, 3 MODES
OPERATION, fSW = 200kHz, VIN = 12V, VOUT = 36V,
TA = +25°C
10ms/DIV
FIGURE 23. EN INTO PREBIASED OUTPUT, CCM MODE
(DE/PHDRP = GND), IOUT = 0A
PVCC 2.0V/DIV
VOUT 20.0V/DIV
PLLCOMP 500mV/DIV
PGOOD 5.0V/DIV
SS 700mV/DIV
PH1 30.0V/DIV
SS 3.0V/DIV
PH1 30.0V/DIV
500µs/DIV
20ms/DIV
FIGURE 24. EN ON AND INITIALIZATION TO START-UP, IOUT = 0A
FIGURE 25. SOFT-START, CCM MODE (DE/PHDRP = GND), IOUT = 8A
VOUT 20.0V/DIV
PLLCOMP 500mV/DIV
PGOOD 5.0V/DIV
CLKOUT 5.0V/DIV
PH1 30.0V/DIV
SS 2.0V/DIV
PVCC 2.0V/DIV
SS 3.0V/DIV
200µs/DIV
FIGURE 26. EN ON AND INITIALIZATION TO START-UP, IOUT = 0A
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5ms/DIV
FIGURE 27. SOFT-START, DE+PHDROP MODE (DE/PHDRP = FLOAT),
IOUT = 8A
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User Guide 065
Performance Curves
and TA = +25°C (Continued)
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V, VOUT = 36V
VOUT 20.0V/DIV
PVCC 2.0V/DIV
PGOOD 5.0V/DIV
PGOOD 3.0V/DIV
PH1 30.0V/DIV
SS 2.0V/DIV
SS 3.0V/DIV
PH1 30.0V/DIV
5ms/DIV
20ms/DIV
FIGURE 28. SOFT-START, DE MODE (DE/PHDRP = VCC), IOUT = 8A
FIGURE 29. EN SHUTDOWN, PVCC/PGOOD/SS FALL, IOUT = 0A
PGOOD 5.0V/DIV
IL1 4.0A/DIV
VOUT 20.0V/DIV
LG2 5.0V/DIV
LG1 5.0V/DIV
PH1 40.0V/DIV
PH2 40.0V/DIV
20µs/DIV
VOUT 30.0V/DIV
10µs/DIV
FIGURE 30. EN SHUTDOWN, IOUT = 8A
FIGURE 31. CCM MODE (DE/PHDRP = GND), PHASE 1 INDUCTOR
RIPPLE CURRENT, IOUT = 0A
IL1 4.0A/DIV
PGOOD 4.0V/DIV
VOUT 20.0V/DIV
LG2 5.0V/DIV
PH2 30.0V/DIV
LG1 5.0V/DIV
PH1 30.0V/DIV
VOUT 30.0V/DIV
5ms/DIV
10µs/DIV
FIGURE 32. EN SHUTDOWN, IOUT = 8A
FIGURE 33. CCM MODE (DE/PHDRP = GND), PHASE 1 INDUCTOR
RIPPLE CURRENT, IOUT = 0A
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User Guide 065
Performance Curves
and TA = +25°C (Continued)
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V, VOUT = 36V
VOUT 10.0V/DIV
PGOOD 4.0V/DIV
VOUT 1.0V/DIV WITH 36V OFFSET
PH2 20.0V/DIV
PH2 30.0V/DIV
PH1 20.0V/DIV
PH1 30.0V/DIV
2µs/DIV
5µs/DIV
FIGURE 34. DE MODE (DE/PHDRP = VCC), DIODE EMULATION
OPERATION, PULSE SKIPPING, IOUT = 0A
VOUT 10.0V/DIV
PH2 30.0V/DIV
FIGURE 35. DE MODE (DE/PHDRP = VCC), DIODE EMULATION
OPERATION, IOUT = 29mA
VOUT 10.0V/DIV
PH1 30.0V/DIV
PH2 30.0V/DIV
PH1 30.0V/DIV
10µs/DIV
FIGURE 36. DE MODE (DE/PHDRP = VCC), PH1 AND PH2 DIODE
EMULATION OPERATION, PULSE SKIPPING, IOUT = 7mA
2µs/DIV
FIGURE 37. DE+PH_DROP MODE (DE/PHDRP = FLOAT), PH1 DIODE
EMULATION WITH PH2 DROPPED, IOUT = 29mA
VOUT 10.0V/DIV
IMON 300mV/DIV
I_LOAD 5.0A/DIV
PH1 30.0V/DIV
PH1 30.0V/DIV
PH2 30.0V/DIV
PH2 30.0V/DIV
10µs/DIV
FIGURE 38. DE+PHDRP MODE (DE/PHDRP = FLOAT), PH1 DIODE
EMULATION WITH PH2 DROPPED, IOUT = 7mA
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10ms/DIV
FIGURE 39. DE+PHDRP MODE (DE/PHDRP = FLOAT), PH2 ADDED
AND DROPPED, UNDER TRANSIENT STEP LOAD OF 1A
TO 8A
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Performance Curves
and TA = +25°C (Continued)
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V, VOUT = 36V
FB 300mV/DIV
FB 300mV/DIV
VOUT 6.8V/DIV
VOUT 6.8V/DIV
TRACK 300mV/DIV
TRACK 300mV/DIV
PH1 20.0V/DIV
PH1 20.0V/DIV
2ms/DIV
2ms/DIV
FIGURE 40. ANALOG TRACKING 100Hz SINUSOIDAL SIGNAL, CCM
MODE (DE/PHDRP = GND), ATRK/DTRAK = VCC,
IOUT = 1A
FIGURE 41. ANALOG TRACKING 300Hz SINUSOIDAL SIGNAL AT THE
TRACK PIN, CCM MODE (DE/PHDRP = GND),
ATRK/DTRAK = VCC, IOUT = 1A
TRACK 4.0V/DIV
IMON 500mV/DIV
I_IN 16A/DIV
VOUT 7.0V/DIV
PH1 30.0V/DIV
PH2 40.0V/DIV
VOUT 30.0V/DIV
PH1 40.0V/DIV
50µs/DIV
1µs/DIV
FIGURE 42. STEADY-STATE OPERATION OF INPUT
CONSTANTCURRENT MODE, IIN CONTROLLED AT 43A
CONSTANT, VOUT = 19.5V
FIGURE 43. DIGITAL TRACKING (TRACKING SIGNAL,
FREQUENCY = 400kHz, D = 0.5, VOUT = 28.3V
TRACK 4.0V/DIV
IMON 500mV/DIV
I_IN 16A/DIV
VOUT 7.0V/DIV
PH1 30.0V/DIV
PH2 40.0V/DIV
VOUT 30.0V/DIV
1s/DIV
FIGURE 44. LOAD CURRENT KEEP INCREASING FROM NO LOAD TO
OVERLOAD (25A), VOUT STARTS TO DROP WHEN INPUT
CONSTANT CURRENT MODE STARTS TO WORK, INPUT
CURRENT IS FINALLY CONTROLLED TO BE CONSTANT
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PH1 40.0V/DIV
1µs/DIV
FIGURE 45. DIGITAL TRACKING (TRACKING SIGNAL,
FREQUENCY = 400kHz, D = 0.3), VOUT = 17V
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User Guide 065
Performance Curves
and TA = +25°C (Continued)
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V, VOUT = 36V
TRACK 4.0V/DIV
VOUT 2.0V/DIV WITH 36V OFFSET
VOUT 1.0V/DIV WITH 28V OFFSET
I_LOAD 5.0A/DIV
PH2 40.0V/DIV
PH1 30.0V/DIV
PH2 30.0V/DIV
PH1 40.0V/DIV
10µs/DIV
10ms/DIV
FIGURE 46. DIGITAL TRACKING, (TRACKING SIGNAL,
FREQUENCY = 200kHz, D = 0.5), VOUT = 28.3V
FIGURE 47. DE MODE (DE/PHDRP = VCC), TRANSIENT RESPONSE,
IOUT = 0.03 TO 8A STEP LOAD
VOUT 30.0V/DIV
VOUT 1.0V/DIV WITH 36V OFFSET
PH1 40.0V/DIV
I_LOAD 5.0A/DIV
PVCC 5.0V/DIV
PH1 30.0V/DIV
PH2 30.0V/DIV
SDA 3.0V/DIV
2ms/DIV
1ms/DIV
FIGURE 48. CCM MODE (DE/PHDRP = GND), TRANSIENT RESPONSE,
IOUT = 0 TO 8A STEP LOAD
FIGURE 49. SHUTDOWN VIA PMBus™ COMMAND OPERATION, OFF
VOUT 1.0V/DIV WITH 36V OFFSET
VOUT 30.0V/DIV
PH1 40.0V/DIV
I_LOAD 5.0A/DIV
PVCC 5.0V/DIV
PH1 30.0V/DIV
PH2 30.0V/DIV
5ms/DIV
FIGURE 50. DE+PH_DROP MODE (DE/PHDRP = FLOAT), TRANSIENT
RESPONSE, IOUT = 1 TO8A STEP LOAD
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SDA 3.0V/DIV
5ms/DIV
FIGURE 51. ENABLE VIA PMBus™ COMMAND OPERATION, ON
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User Guide 065
Performance Curves
and TA = +25°C (Continued)
Unless otherwise specified, operating conditions for the oscilloscope waveforms are VIN = 12V, VOUT = 36V
PH1 40.0V/DIV
PH1 30.0V/DIV
PH2 40.0V/DIV
PH2 30.0V/DIV
VOUT 5.0V/DIV WITH 36V OFFSET
VOUT 10.0V/DIV
SDA 4.0V/DIV
SDA 4.0V/DIV
2ms/DIV
20ms/DIV
FIGURE 52. PMBus™ COMMAND VOUT_COMMAND CHANGES
VREF_DAC FROM 1V TO 1.6V. VOUT_TRANSITION_RATE
SETS VREF_DAC CHANGING SLEW RATE AT 12.5mV/ms
FIGURE 53. PMBus™ COMMAND VOUT_COMMAND CHANGES
VREF_DAC FROM 1.6V TO 1V. VOUT_TRANSITION_RATE
SETS VREF_DAC CHANGING SLEW RATE AT 200mV/ms
PH1 30.0V/DIV
PH1 40.0V/DIV
PH2 30.0V/DIV
PH2 40.0V/DIV
VOUT 10.0V/DIV
VOUT 5.0V/DIV
SDA 4.0V/DIV
20ms/DIV
FIGURE 54. PMBus™ COMMAND VOUT_COMMAND CHANGES
VREF_DAC FROM 1.6V TO 1V. VOUT_TRANSITION_RATE
SETS VREF_DAC CHANGING SLEW RATE AT 12.5mV/ms
SDA 4.0V/DIV
2ms/DIV
FIGURE 55. PMBus™ COMMAND VOUT_COMMAND CHANGES
VREF_DAC FROM 1V TO 1.6V. VOUT_TRANSITION_RATE
SETS VREF_DAC CHANGING SLEW RATE AT 200mV/ms
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the document is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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