Technical Brief 500 Computing Power Reference Design Adaptation Guide Abstract The goal of this design guide is to aid in rapidly prototyping a new design on an Intersil evaluation board using an existing reference design provided from an application engineer as a starting point. This procedure will give a solid first pass of a new design with additional fine tuning and output filter modification required once the end application board is laid out and tested. Use this guide for quickly checking the feasibility and performance of key parts (e.g., inductors, FETs, bulk caps, etc.) that may differ from those called out in reference designs against both Intel and Intersil specifications. This is by no means an exhaustive reference to designing with Intersil regulators; it is a stepping stone to getting a new design up and running before additional, more thorough, testing can be done. Table of Contents Assumptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Required Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Optional Equipment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 List of Figures FIGURE 1. FIGURE 2. FIGURE 3. May 19, 2015 TB500.0 VDROOP Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Load Response Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Compensation Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Technical Brief 500 Assumptions • For single phase designs, set N = 1 • If using the Intersil default design parameters: This guide assumes the following: • An Intersil evaluation board is being used for testing • The desired inductor, FETs and/or output capacitors have been chosen • A reference design provided by Applications is being used as a starting point • DCR sensing Required Equipment • Digital multimeter • Intel Gen 4 VRTT with appropriate interposer • R-C substitution box • Typically RIMON = 100kΩ and any further adjustments to this value can be made after the rest of the design is completed. • VIN and +5V power supplies • Evaluation board documentation I LOAD V IMON = 1.2V --------------------- I CCmax • Part datasheet Optional Equipment • Electronic load - more accurate for DC loads than VRTT • Additional R-C substitution boxes - speed up the process by changing multiple components at once • List of standard 1% resistor values Design Procedure 5. Calculate Rdroop using the following formula and dial the R-C box to the closest 1% value. I CCmax R droop = ---------------------------- DC_LL I droopmax (EQ. 3) • If using the Intersil default design parameters: 1. Modify the evaluation board to configure it with the desired inductor(s), FETs and number of output bulk and ceramic capacitors. • Not all ceramic caps are created equal and capacitors from different vendors do not give the same performance. For quick design checks, leave the MLCCs used by Intersil on the board. For more thorough testing, populate the exact ones to be used in the end application. 2. Leave the compensation components used by the reference design in place. They should provide a good starting point for a reasonable range of output filters. 3. Calculate Ri using the formula below and solder connections from the R-C box to the appropriate resistor on the evaluation board. Dial the box to the 1% resistor value closest to the calculated result. 2 (EQ. 2) Solder the final resistor value in place for Ri and move the R-C box to the Rdroop resistor on the feedback resistor to dial in the DC load line. • Differential oscilloscope probe for VOUT Submit Document Feedback •For low ICCmax applications Idroopmax might need to be decreased to allow for additional current when slewing VOUT. 4. Using the VRTT, or electronic load, apply an appropriate DC load to the part that will not damage any components such as the FETs. Adjust Ri in 1% resistor value increments while monitoring the voltage at the IMON pin until it is as close as possible to the correct value. Use the formula below to find the IMON voltage for a given load current. • Oscilloscope R ntcnet DCR I CCmax R i = -----------------------------------------------------------------------------------------R sum N R ntcnet + --------------- I droopmax N - Rsum = 3.65kΩ - Rntcnet = 5.875kΩ (see datasheet for formulas if changing NTC network) - Idroopmax = 48µA (This sets the OCP point 25% higher than ICCmax as OCP trips when Idroop = 60µA.) - Idroopmax = 48µA 6. Using a VRTT, load the part with a transient from 1A to ICCmax, at a 300Hz rep rate, and monitor VOUT on the scope. Set the time base on the scope so that one full cycle is visible. Position the cursors on the scope as shown in Figure 1 on page 3 and adjust Rdroop in 1% increments until Vdroop is dialed into spec. • A duty cycle of 50% or lower is recommended for the load transient. V droop = DC_LL I CCmax – 1 (EQ. 4) (EQ. 1) TB500.0 May 19, 2015 Technical Brief 500 VOUT CURSOR 1 Vdroop CURSOR 2 FIGURE 1. VDROOP ADJUSTMENT IOUT VOUT DESIRED RESPONSE VOUT VOUT Cn TOO SMALL Cn TOO LARGE FIGURE 2. LOAD RESPONSE ADJUSTMENT 7. Solder the final resistor value in place for Rdroop and move the R-C box to the Cn capacitor in the DCR network. 8. Calculate Cn and dial the R-C box to the closest standard capacitor value possible. If necessary, assume two capacitors in parallel when setting the substitution box. L C n = ----------------------------------------------------------------------R sum R ntcnet --------------- N - -------------------------------------------- DCR R sum R -------------+ netcnet N . R3 C3 FB VOUT IDROOP gm R2 VREF COMP (EQ. 5) • For single phase designs, set N = 1 R1 C2 C1 • If using the Intersil default design parameters: - Rsum = 3.65kΩ - Rntcnet = 5.875kΩ (see datasheet for formulas if changing NTC network) 9. Using a VRTT, load the part with a transient from 1A to ICCmax, at a 300Hz rep rate, and monitor VOUT on the scope. Set the time base on the scope so that one full cycle is visible. Adjust Cn in standard capacitor increments until VOUT matches the desired response. • A duty cycle of 50% or lower is recommended for the load transient. (See Figure 2) 10. Solder down the final Cn capacitor value(s) and move the R-C box to the compensation components. 11. Using a VRTT, load the part with a transient from 1A to ICCmax, at a 300Hz rep rate, and monitor VOUT on the scope. Trigger on the falling edge of VOUT and adjust the compensation components as needed to fine tune the transient response. (See Figure 3) FIGURE 3. COMPENSATION ADJUSTMENT • Compensation scheme assumes C1 >> C2 and R2 >> R3 • Make sure overall response is square through Cn adjustment in Step 9. • R3 and C2 can be used to adjust the initial response to a load step (~2µs after insertion) • C3 can be used to adjust the response approximately 5 to 10µs after load step • R1 and C1 can adjust the transient response >10µs after load step. 12. Sweep the load transient repetition rate up to 1MHz with the persistence feature of the scope turned on while checking if over and undershoot on VOUT meet the required Intel specs. Adjust compensation and COUT as needed to pass. • A duty cycle of 50% or lower is recommended for the load transient. Submit Document Feedback 3 TB500.0 May 19, 2015 Technical Brief 500 13. Check the following parameters to ensure they are within spec and iterate through the design process as needed until all requirements are met. • CCM ripple at no load and full load • DCM ripple at 0A and light loads • DC load line • Transient response The completed design can then be used as a starting point on the end application board and further modified as more thorough testing is completed. If assistance is required during the design process, contact an Intersil FAE or Applications Engineer. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the document is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 4 TB500.0 May 19, 2015