User Guide 067
ISL68200DEMO1Z Demonstration Board User Guide
Key Features
The ISL68200 is a single-phase synchronous buck PWM
controller featuring Intersil’s proprietary R4™ Technology,
which has extremely fast transient performance, accurately
regulated frequency control and all internal compensation. The
ISL68200 supports a wide 4.5V to 24V input voltage range and
a wide 0.5V to 5.5V output range. It includes programmable
functions and telemetries for easy use and high system
flexibility using SMBus, PMBus, or I2C interface. See the
ISL68200 datasheet for more details.
• 20A synchronous buck converter with PMBus control
• On-board transient load with adjustable di/dt
• Configurable through resistor pins
• Cascadeable PMBus connectors
• Integrated LDOs for single rail solution
• Enable switch and power-good indicator
The ISL68200DEMO1Z is a 6-layer board demonstrating a
compact 17mmx17mm 20A synchronous buck converter.
Transient performance, fault protections, DC/AC regulations,
PMBus programming, power sequencing, margining and other
features can be evaluated using this board.
• All ceramics solution with SP capacitor footprint option
Target Specifications
• VIN = 4.75V to 14.5V
The PMBus dongle (ZLUSBEVAL3Z), i.e., USB-to-PMBus™
adapter, and USB cable are included in the demonstration kit.
Intersil’s evaluation software can be installed from Intersil’s
website and evaluate the full PMBus functionality of the part
using a PC running Microsoft Windows 7 or 8.
• VOUT = 1V/20A full load
• fSW = 400kHz
• Peak efficiency:
- 89% at 12A/1VOUT/12VIN
- 94% at 6A/1.8VOUT/5VIN
References
• Output regulation: 1V ±8mV
ISL68200 datasheet
• I/O capacitor rating: CIN - 16V; COUT - 4V
AN1900, “USB to PMBus™ Adapter User Guide”
• Compact size: 17mmx17mm
Intersil’s PowerNavigator™ User Guide
• With or without PMBus/SMBus/I2C Capability
Ordering Information
PART NUMBER
DESCRIPTION
ISL68200DEMO1Z
ISL68200 Demonstration Kit (Demonstration
board, dongle, USB cable)
1.0µ F
4.7µ F
VCC
7VLDO
PVCC
VIN
1.0µ F
4.75 TO 15V
0.1µF
2
SALERT
SCL
SDA
PGOOD
PGOOD
I C/SMBus/
PMBus
EN
BOOT
UGATE
1V AT 20A
PHASE
EN
IOUT
LGATE
10k
NTC
VCC
1.54k
VCC
NTC
0.1µF
4
PROG1-4
SGND
CSEN
CSRTN
VSEN
RGND
PGND
FIGURE 1. ISL68200DEMO1Z SIMPLIFIED SCHEMATIC
March 17, 2016
UG067.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved
Intersil (and design), PowerNavigator and R4 Technology are trademarks owned by Intersil corporation or
one of its subsidiaries.All other trademarks mentioned are the property of their respective owners.
User Guide 067
FIGURE 2. DEMONSTRATION BOARD TOP VIEW
Demonstration Board
Description
The ISL68200DEMO1Z provides all circuitry required to
demonstrate the key features of the ISL68200. A majority of the
features of the ISL68200, such as optimal transient response
with Intersil’s R4™ Modulator, 8-bit programmable boot voltage
levels, selectable switching frequency in continuous conduction
mode, selectable PFM operation option for improved light-load
efficiency, power-good monitor for soft-start and fault detection,
over-temperature protection, output over-current and short-circuit
protection and output overvoltage protection are available on this
demonstration board.
Figure 1 shows a simplified schematic diagram of the
ISL68200DEMO1Z board. Figure 6 shows the detailed 20A buck
solution schematics, while Figure 7 shows the I/O connectors,
auxiliary circuits and on-board transient circuits. Figures 8
through 30 show typical performance data and Figures 31
through 36 show the PCB board layout. The default programming
pins setting is given on the upper right corner of Figure 7, and the
Bill of Materials (BOM) is included for reference beginning on
page 9.
FIGURE 3. DEMONSTRATION BOARD BOTTOM VIEW
Furthermore, an on-board transient load, as shown in Figure 7,
with both di/dt and load step amplitude is controlled by a
function generator. Since this auxiliary circuit draws more than
10A of bias current, the jumper on JP5 should be removed for
accurate efficiency measurement.
Intersil’s evaluation software is compatible with Windows 7 or 8
operating systems and can be used to evaluate the series bus
functionality of the ISL68200. The software and user guide can
be found in following Intersil website:
http://www.intersil.com/powernavigator
Quick Start Guide
Stand-Alone Operation
1. Set ENABLE switch to “OFF” position.
2. Connect a power supply (off) to input connectors (J4-VIN and
J2-GND).
3. Set input power supply voltage level (no more than 15V) and
current limiting (no more than 1A for 0A load).
4. Turn the power supply on.
5. Set ENABLE switch to “ON” position.
The ISL68200DEMO1Z board can run by itself without a series
bus communication. The operational configuration is fully
programmable via programming pins (PROG1-4).
6. Increase power supply current limit enough to support more
than the full load.
The ISL68200 however, utilizes the PMBus/SMBus/I2C protocol
8. Monitor operation using an oscilloscope.
and provides the flexibility for digital power management and
performance optimization prior to finalizing the hardware
configuration on the programming pins.
The buck regulator in the ISL68200DEMO1Z board is a single
input rail design, i.e., everything is biased by the input supply
(typically 12V). The resistor divider on the EN pin (R4 and R12)
can set the input supply undervoltage protection level and its
hysteresis. The “ENABLE” switch is a hardware operational
control, alternately, the series bus ON_OFF_CONFIG and
OPERATION commands can be used for software operational
control.
Submit Document Feedback
2
7. Apply load to output connectors (J1-VOUT and J2-SGND).
PMBus Operation
1. Connect supplied Intersil’s dongle J9.
2. Connect supplied USB cable from computer to the dongle.
3. After the input power supply turns on, open the
PowerNavigator evaluation software.
4. Select detected ISL68200 device (Address - 60h) and follow
Intersil’s PowerNavigator™ operation guide.
5. Monitor and configure the board using PMBus commands in
the evaluation software.
UG067.1
March 17, 2016
User Guide 067
Configuration
Load Transient
The default programming pins setting of the ISL68200DEMO1Z
board can be found at the resistor reader table on the upper right
corner of “ISL68200DEMO1Z Schematics” on page 7 or read
back via Intersil’s PowerNavigator™ software. Each PMBus
command can be loaded or programmed via the
PowerNavigator™ software. Note that ISL68200 does not have
NVM to store the operational configuration, which can however
be set by the resistor programming pins (PROG1-4) or
programmed by the series bus master before powering up. If a
series bus master is available in the system, the ISL68200-based
rail can be fully controlled via software for the power-up/down
sequencing and operational configuration without a soldering
iron.
The on-board transient load can be controlled by a function
generator, whose inputs are connected to FG_DRIVE2 and
FG_GND2. The function generator’s output is terminated by R42
at the input terminal, while its amplitude and dV/dt set the load
amplitude and di/dt on the 50mΩ load (RLT1//RLT2). The
transient load can be monitored with a scope probe on TP15.
Note that the duty cycle of applied load should be less than 10%
duty cycle with <10ms pulse width to keep the average power of
RLT1/RLT2 less than its power rating.
.
2SHQ-XPSHUIRU(IILFLHQF\0HDXUHPHQW
-3
9&&B/'*(1
&
2Q%RDUG/RDG7UDQVLHQW
9287
&
X
5
5
X
287%
39&&
OPEN JP4 FOR
EFFICIENCY MEASUREMENT
287$
8
48
287%
287$
%6&1/6
73
75$1B/2$'
287$
96
,1$
287%
,1$
,1%
96
,1%
& 3 5
'13
& S
5
)*B'5,9(
.
(/,6=
5
N
5/7
5/7
5
5
5
)*B*1'
5
FIGURE 4. LOAD TRANSIENT
FIGURE 5. ISL68200 DEMONSTRATION KIT SET-UP
Submit Document Feedback
3
UG067.1
March 17, 2016
User Guide 067
Design Modifications
fine-tune might be needed depending upon the rework and final
layout design.
When modifying the design, it will require a new set of L/DCR
matching for different inductor, divider on the PROG pins for
different operational configuration, RSEN1 for OCP, and IOUT
network for accurate digital IOUT; higher input capacitor rating to
support higher than 16V input, higher output capacitor rating to
support higher than 4V output. Refer to ISL68200 datasheet and
PowerNavigator™ software for proper design modifications
including L/DCR matching, thermal compensation, OCP and
digital IOUT fine tuning.
Two examples are provided in Table 1, showing the
recommended design modifications to accommodate the
application cases with 5V and 3.3V output voltages. Some
For the 5V input voltage applications with 4.5V < VIN < 5.5V
requirement, the “VIN”, “VCC”, “PVCC” and “7VLDO” pins should
be shorted together, to connect with the input supply for optimal
performance; R12 should be removed as well.
Note that all devices in the same bus should set different
addresses for unique identification and proper communication.
JP2, JP3, JP9 and JP10 connectors are designed to cascade
many Intesil’s solutions for easy communication and system
evaluation prior to the system integration and design.
TABLE 1. DESIGN EXAMPLES
REFERENCE
DESIGNATOR
5.0V AT 16A
L1
3.3V AT 16A
680nH, 1.72mΩ
Vendor: Wurth Electronic;
Part Number: 744334006
CO5, CO6, CO8,
CO9
3.3V AT 30A
COMMENTS
Reduce Output ripple current; typically higher
470nH, 0.165mΩ
Vendor: Wurth Electronic; voltage output needs higher inductance.
Part Number: 744309047
Increase COUT rating to support higher VOUT.
Also capacitance of ceramic capacitors
decreases with increased output voltage.
100µF/X5R/6.3V/1206
Vendor: Murata;
Part Number: GRM21BR60J107ME11
PROG1 (DC)
DFh
BFh
BFh
Set correct VBOOT = VOUT
R3
147k, 1%
105k, 1%
105k, 1%
PROG2 (DD)
A0h
BFh
BFh
R5
105k, 1%
DNP
DNP
R6
DNP
105k, 1%
105k, 1%
PROG3 (DE)
0Dh
0Dh
0Dh
R8
24.3k, 1%
24.3k, 1%
24.3k, 1%
R9
16.9k, 1%
16.9k, 1%
16.9k, 1%
PROG4 (DF)
08h
08h
08h
R10
15k, 1%
15k, 1%
15k, 1%
R11
29.4k, 1%
29.4k, 1%
29.4k, 1%
RP1
4.99k, 1%
4.99k, 1%
3.57k, 1%
RSEN1
536, 1%
536, 1%
62, 1%
Set OCP
R13
11k, 1%
11k, 1%
15k, 1%
Set IOUT to 1A/1A Slope
R14
TBD
TBD
TBD
Set Different PMBus Addresses as needed
TCOMP = 15
PFM DISABLED
Set AV = 13
fSW = 500kHz
OCP = Retry
25kHz Clamp Disabled
Set RR = 400k
SS = 1.25mV/µs
AVMLTI = 1 x
L/DCR Matching
Pull-up value depends upon final layout
design
NOTE:
1. Some fine-tune might be needed depending upon the rework and final layout design.
Submit Document Feedback
4
UG067.1
March 17, 2016
User Guide 067
Design and Layout
Considerations
TABLE 2. DESIGN AND LAYOUT CHECKLIST (Continued)
To ensure a first pass design, the schematics design must be
done correctly and the board must be carefully laid out.
PIN
NAME
NOISE
SENSITIVITY
SCL, SDA
Yes
50kHz to 1.25MHz signal when the SMBus,
PMBus, or I2C is sending commands. Pairing
up with SALERT and routing carefully back to
SMBus, PMBus or I2C master. 20 mils spacing
within SDA, SALERT and SCL; and more than
30 mils to all other signals. Refer to the
SMBus, PMBus or I2C design guidelines and
place proper terminated (pull-up) resistance
for impedance matching. Tie them to GND
when not used.
SALERT
No
Open-drain and high dv/dt pin during
transitions. Route it in the middle of SDA and
SCL. Tie it to GND when not used.
PGOOD
No
Open-drain pin. Tie it to ground when not used.
RGND,
VSEN
Yes
Differential pair routed to the remote sensing
points with sufficient decoupling ceramics
capacitors and not across or go above/under
any switching nodes (BOOT, PHASE, UGATE,
LGATE) or planes (VIN, PHASE, VOUT) even
though they are not in the same layer. At least
20 mils spacing from other traces. DO NOT
share the same trace with CSRTN.
CSRTN
Yes
Connect to the output rail side of the output
inductor or current sensing resistor pin with a
series resistor in close proximity to the pin. The
series resistor sets the current gain and should
be within 40Ωand 3.5kΩ. Decoupling
(~0.1µF/X7R) on the output end (not the pin)
is optional and might be required for long
sense trace and a poor layout.
CSEN
Yes
Connect to the phase node side of the output
inductor or current sensing resistor pin with
L/DCR or ESL/RSEN matching network in close
proximity to CSEN and CSRTN pins.
Differentially routing back to the controller
with at least 20 mils spacing from other
traces. Should NOT cross or go above/under
the switching nodes [BOOT, PHASE, UGATE,
LGATE] and power planes (VIN, PHASE, VOUT)
even though they are not in the same layer.
NTC
Yes
Place NTC 10k (Murata, NCP15XH103J03RC,
= 3380) in close proximity to the output
inductor’s output rail, not close to MOSFET
side; the return trace should be 20 mils away
from other traces. Place 1.54kΩ pull-up and
decoupling capacitor (typically 0.1µF) in close
proximity to the controller. The pull-up resistor
should be exactly tied to the same point as VCC
pin, not through an RC filter. If not used,
connect this pin to VCC.
IOUT
Yes
Scale R such that IOUT pin voltage is 2.5V at
63.875A load. Place R and C in general
proximity to the controller. The time constant
of RC should be sufficient as an averaging
function for the digital IOUT. An external
pull-up resistor to VCC is recommended to
cancel IOUT offset at 0A load.
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board or internal layers.
The ground-plane layer should be in between the power layers
and the signal layers to provide shielding, often the layer below
the top and the layer above the bottom should be the ground
layers.
There are two sets of components in a DC/DC converter, the
power components and the small signal components. The power
components are the most critical because they switch large
amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors and the inductor. Keeping
the distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, GND, PHASE and BOOT.
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible. Input high frequency capacitors should be
placed close to the drain of the upper MOSFETs and the source of
the lower MOSFETs. Place the output inductor and output
capacitors between the MOSFETs and the load. High frequency
output decoupling capacitors (ceramic) should be placed as
close as possible to the decoupling target, making use of the
shortest connection paths to any internal planes. Place the
components in such a way that the area under the IC has less
noise traces with high dV/dt and di/dt, such as gate signals,
phase node signals and VIN plane.
Tables 2 and 3 provide design and layout checklist that the
designer must pay attention to.
TABLE 2. DESIGN AND LAYOUT CHECKLIST
PIN
NAME
NOISE
SENSITIVITY
EN
Yes
There is an internal 1µs filter. Decoupling the
capacitor is NOT needed, but if needed, use a
low time constant one to avoid too large a
shutdown delay.
VIN
Yes
Place 16V+ X7R 1µF in close proximity to VIN
pin and the system ground plane.
7VLDO
Yes
Place 10V+ X7R 1µF in close proximity to
7VLDO pin and the system ground plane.
VCC
Yes
Place X7R 1µF in close proximity to VCC pin
and the system ground plane.
DESCRIPTION
Submit Document Feedback
5
DESCRIPTION
UG067.1
March 17, 2016
User Guide 067
TABLE 2. DESIGN AND LAYOUT CHECKLIST (Continued)
PIN
NAME
NOISE
SENSITIVITY
PROG1-4
No
Resistor divider must be referenced to VCC pin
and the system ground; they can be placed
anywhere. DO NOT use decoupling capacitors
on these pins.
GND
Yes
Directly connect to low noise area of the
system ground. The GND PAD should use at
least 4 vias. Separate analog ground and
power ground with a 0Ω resistor is highly NOT
recommended.
DESCRIPTION
LGATE
No
Low-side driver output and short and wide
trace in between this pin and MOSFET gate pin
as possible. High dV/dt signals should not be
close to any sensitive signals.
UGATE
No
High-side driver output and short and wide
trace in between this pin and MOSFET gate pin
as possible. High dV/dt signals should not be
close to any sensitive signals.
BOOT,
PHASE
Yes
Place X7R 0.1µF or 0.22µF in proximity to
BOOT and PHASE pins. High dV/dt signals
should not be close to any sensitive signals.
PVCC
Yes
Place X7R 4.7µF in proximity to PVCC pin and
the system ground plane.
Submit Document Feedback
6
TABLE 3. TOP LAYOUT TIPS
NUMBER
DESCRIPTION
1
The layer next to controller (top or bottom) should be a ground
layer. Separate analog ground and power ground with a 0Ω
resistor is highly NOT recommended. Directly connect GND
PAD to low noise area of the system ground with at least 4
vias.
2
Never place controller and its external components above or
under VIN plane or any switching nodes.
3
Never share CSRTN and VSEN on the same trace.
4
Place the input rail decoupling ceramic capacitors closely to
the high-side FET. Never use only one via and a trace to
connect the input rail decoupling ceramics capacitors; must
connect to VIN and GND planes.
5
Place all decoupling capacitors in close proximity to the
controller and the system ground plane.
6
Connect remote sense (VSEN and RGND) to the load and
ceramic decoupling capacitors nodes; never run this pair
below or above switching noise plane.
7
Always double check critical component pinout and their
respective footprints.
UG067.1
March 17, 2016
Submit Document Feedback
ISL68200DEMO1Z Schematics
RESISTOR READER
9&&
&
X)
X)
PROG2
A0h
PFM DISABLED, TCOMP=15degC, ADDR = C0/C1h
08h
25k Clamp Disabled, OCP/OTP Retry, 400kHz, AV=42
00h
SS = 1.25mV/us; RR = 200k Ohm;AVMULTI=1X
PROG4
7
*
'
'
'
4'8$/
80h
PROG3
8*$7(
&
BOOT VOTLAGE = 1V
PROG1
)'066
*50&5*0( X);59
&%
&
N
%227
39&&
NCP15XH103J03RC
0402 size
*
6
6
6
/*$7(
X
9287
/ Q+
'6
3+$6(
.
5
'13
517&
5
39&&
&2
X)
&2
X)
&2
'13
&2
X)
5
5
&
9/'2
X
39&&
&
X
&
X
(1
352*%7
9,1
352*3)0B7&203B$''5
9/'2
352*86B)/7B)6:B$9
352*66B55
9&&
,6/
6&/.
'13
5
39&&
*1'
/*$7(
8*$7(
3+$6(
9&&
%227
39&&
(1$%/(
N
5
User Guide 067
X
8
,287
6$/(57
17&
5
5
N
N
N
'13 5
5
39&&
39&&
&
5
,287
Q)
N
5
'13
39&&
&6(1
&6571
96(1
5*1'
6'$
*1'
570
N
39&&
&17&
X
6$/57
3*22'
17&
6&/
&6(1
6'$
3*22'
&6571
&&
56(1 X
N
53
3+$6(
9287
96(1
5*1'
FIGURE 6. ISL68200DEMO1Z 1V AT 20A BUCK SOLUTION SCHEMATICS
&2
X)
UG067.1
March 17, 2016
9,1B*1'
-
73
-
39&&
9&&
,287
17&
73
R12 = 9.09K for typical POR = 10.08V/9.12V;
R12 = 24.9K for typical POR = 4.21V/3.81V
5
N
9&&
17&
5
,287
VOUT PGOOD
N
&
&
X)
X)
'6
5('/('
9&&
LED LIGHT
ON
OFF
VOUT STATUS
DOWN
UP
&,1
X)
5
Submit Document Feedback
ISL68200DEMO1Z Schematics (Continued)
73
3*22'
95B5'<
N
8
73)0/326&$39X)(65P2KP/[:[+PPPD[
9287
&2
'13
5%/'
-
9287
-
*1'
&2
'13
(1$%/(
DNP these and leave the holes for probes
8*$7(
/*$7(
3+$6(
73
-3
73
73
8*$7(
&
&
&2
'13
9287
&2
'13
(1$%/(
73
5
73
&2
'13
6:
&2
'13
Place Connection of
VOUT and GND to the
Remote Sensing
Points (Say center
of the Ceramic Caps
or Last Ceramic Cap)
73
*1'
/*$7(
3+$6(
X
X
2SHQ-XPSHUIRU(IILFLHQF\0HDXUHPHQW
-3
FROMPREQUEL
TOSEQUEL
-
-
0675B6<1&
569'
*1'
''&
569'
569'
+'5B;B5$
&
2Q%RDUG/RDG7UDQVLHQW
ONRIGHTOFBOARD(FEMALE)
9287
5
8
39&&
48
&
287%
5
N
5
N
5
73
N
75$1B/2$'
287$
,1$
96
287%
,1$
,1%
96
,1%
& 3 5
'13
& S
5
)*B'5,9(
.
(/,6=
6.7B;B5$
-
+'5B;B5$
%6&1/6
6'$
DONGLE
287$
X
5
N
6$/57
6'$
6$/57
6&/
*1'
9LF
0675B(1
X
287$
6&/
&
X
5
287%
ONLEFTOFBOARD(MALE)
9&&B/'*(1
39&&
%2$5'72%2$5',17(5)$&(
ThisboardonlyusesSDA,SCL,SALRT,
GNDsignals;PullͲUpImpedancetoBe
AjustedforHowManyBoardsare
connectedtotheBus
5/7
5/7
5
5
6.7B;B5$
-
FIGURE 7. I/O CONNECTORS, AUXILIARY CIRCUITS AND ON-BOARD TRANSIENT LOAD SCHEMATICS
5
5
)*B*1'
User Guide 067
5
UG067.1
March 17, 2016
User Guide 067
Bill of Materials
REFERENCE
DESIGNATOR
QTY
DESCRIPTION
PCB FOOTPRINT
MANUFACTURER
PART NUMBER
1
U1
R4 Wrapper with Driver
QFN24_157X157_197_EPC
INTERSIL
ISL68200IRZ-REVD
1
CIN1
270µF/16V/8x9/10mΩ
CAPR_315X275_150_P
SANYO
16SEPC270MX
1
C1
4.7µF/6.3V/X5R
SM0603
VENKEL
C0603X5R6R3-475KNE
2
C2, C3
1.0µF/16V/X7R
SM0603
TDK
C1608X7R1C105K
1
C4
1µF/6.3V/X5R
SM0603
PANASONIC
ECJ1VB0J105K
1
C5
22nF/50V/X7R
SM0603
VENKEL
C0603X7R500-223KNE
4
C6, CB1, CC1, CNTC1 0.1µF/16V/X7R
SM0603
MURATA
GRM39X7R104K016AD
4
C10, C11, C19, C20
22µF/16V/X5R
SM0805
VENKEL
C0805X5R160-226KNE
4
CO5, CO6, CO8, CO9
220µF/4V/X5R
SM1206
MURATA
GRM31CR60G227ME11
1
L1
220nH, 0.29mΩ
ind_we_744302010
Wurth Electronics
744307022
1
QDUAL
Dual FET
pqfn_5x6_dual
INFINEON
BSC0910NDI
1
R2
75kΩ, 1%
SM0603
VENKEL
CR0603-10W-7502FT
1
R4
100kΩ, 1%
SM0603
VENKEL
CR0603-10W-1003FT
1
R5
105kΩ, 1%
SM0603
PANASONIC
ERJ-3EKF1053V
1
R8
15kΩ, 1%
SM0603
PANASONIC
ERJ-3EKF1502V
1
R9
29.4kΩ, 1%
SM0603
YAGEO
RC0603FR-0729K4L
4
R10, R15, R16, R17
10kΩ, 1%
SM0603
VENKEL
CR0603-10W-1002FT
1
R12
24.9kΩ, 1%
SM0603
PANASONIC
ERJ-3EKF2492V
1
R13
9.53kΩ, 1%
SM0603
YAGEO
9C06031A9531FKHFT
2
R30, R31
0Ω
SM0603
VENKEL
CR0603-10W-000T
1
RBLD1
121Ω, 1%
SM0603
VISHAY/DALE
CRCW0603121RFKTA
1
RNTC1
10kΩ NTC, 5%, = 3380
SM0402
MURATA
NCP15XH103J03RC
1
RP1
9.09kΩ, 1%
SM0603
YAGEO
RC0603FR-079K09L
1
RSEN1
75Ω, 1%
SM0603
PANASONIC
ERJ-3EKF75R0V
1
RTM1
1.54kΩ, 1%
SM0603
YAGEO
RC0603FR-071K54L
DEMONSTRATION BOARD SPECIFIC AUXILIARY PARTS BILL OF MATERIALS
1
U2
Dual Amp/500MHz/5V
SOIC8
INTERSIL
EL8203ISZ
1
QU2
8mΩ N-MOSFET
LFPAK
INFINEON
BSC080N03LS G
1
DS1
LED/RED/0805/CLEAR
SM0805
WURTH ELEKTRONIK
150080RS75000
1
SW1
Enable Switch
GT11SC
C&K DIVISION
GT11MSCBE
1
C12
4.7µF/6.3V/X5R
SM0603
VENKEL
C0603X5R6R3-475KNE
2
C13, C55
0.1µF/16V/X7R
SM0603
MURATA
GRM39X7R104K016AD
1
C16
1µF/6.3V/X5R
SM0603
PANASONIC
ECJ1VB0J105K
1
C17
22pF/50V/C0G
SM0603
VENKEL
C0603C0G500-220JNE
1
C18
100pF/50V/C0G
SM0603
PANASONIC
ECJ-1VC1H101J
2
J1, J2
Screw Terminal
B2C-PCB
INTERNATIONAL
HYDRAULICS INC
B2C-PCB
1
J3
Female Banana Jack, Black
111-07xx-001
JOHNSON
COMPONENTS
111-0703-001
Submit Document Feedback
9
UG067.1
March 17, 2016
User Guide 067
Bill of Materials (Continued)
REFERENCE
DESIGNATOR
QTY
DESCRIPTION
PCB FOOTPRINT
MANUFACTURER
PART NUMBER
1
J4
Female Banana Jack, Red
111-07xx-001
JOHNSON
COMPONENTS
111-0702-001
2
J8, J9
CONN-HEADER, 2X3, BRKAWY,
2.54mm,TIN
CONN6
SAMTEC
TSW-103-08-T-D-RA
2
J10, J11
CONN-SOCKET STRIP,TH,2X3,
2.54mm,TIN
CONN6
SAMTEC
SSQ-103-02-T-D-RA
2
JP1, JP4
2-pin 0.1'' spacing Jumper
CONN2
BERG/FCI
69190-202HLF
1
TP1
Probe Ground
TP-150C100P-RTP
KEYSTONE
1514-2
2
TP2, TP14
Probe Jack
TEK131-4353-00
TEKTRONIX
131-4353-00
4
TP3, TP4, TP5, TP6
Test Point
MTP500x
KEYSTONE
5002
2
VCC12, FG_DRIVE
Test Point RED
MTP500x
KEYSTONE
5000
2
VIN_GND, FG_GND
Test Point BLACK
MTP500x
KEYSTONE
5001
4
R32, R33, R36, R37
3Ω, 1%
SM0603
VENKEL
CR0603-10W-03R0FT
1
R34
2kΩ, 1%
SM0603
KOA
RK73H1JTTD2001F
1
R39
2.49kΩ, 1%
SM0603
KOA
RK73H1JTTD2491F
1
R42
52.3Ω, 1%
SM0603
PANASONIC
ERJ-3EKF52R3V
1
R41
274Ω, 1%
SM0603
VENKEL
CR0603-10W-2740FT
1
R43
124kΩ, 1%
SM0603
YAGEO
9C06031A1243FKHFT
2
R45, R46
499Ω, 1%
SM0603
VENKEL
CR0603-10W-4990FT
2
RLT1, RLT2
0.1Ω, 1%
SM2512
CTS RESISTOR
73L7R10J
Submit Document Feedback
10
UG067.1
March 17, 2016
User Guide 067
24
0.25
20
0.2
16
0.15
12
0.1
8
0.05
4
0
SLOPE=1
0
-0.05
0
2
4
6
8
10
12
14
16
18
20
ERROR (DIGITAL IOUT-LOAD) (A)
The following data was acquired using a ISL68200DEMO1Z board.
EFFICIENCY (%)
Measured Data
22
LOAD CURRENT (A)
92
91
90
89
88
87
86
85
84
83
82
81
80
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 8. TYPICAL DIGITAL OUTPUT CURRENT MEASUREMENT
VOUT=0.8V
VOUT=1V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
0
2
4
6
8
10
12
14
16
18
20
22
95
94
93
92
91
90
89
88
87
86
85
84
83
24
VOUT=0.8V
VOUT=1V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
0
2
4
6
LOAD CURRENT (A)
EFFICIENCY (%)
EFFICIENCY (%)
VOUT=0.8V
VOUT=1V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
0
2
4
6
8
10
12
14
16
18
20
22
LOAD CURRENT (A)
FIGURE 11. EFFICIENCY, VIN = 12V, fSW = 500kHz
Submit Document Feedback
11
12
14
16
18
20
22
24
FIGURE 10. EFFICIENCY, VIN = 5V, fSW = 400kHz
92
91
90
89
80
10
LOAD CURRENT (A)
FIGURE 9. EFFICIENCY, VIN = 12V, fSW = 400kHz
88
87
86
85
84
83
82
81
8
24
95
94
93
92
91
90
89
88
87
86
85
84
83
VOUT=0.8V
VOUT=1V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
0
2
4
6
8
10
12
14
16
18
20
22
24
LOAD CURRENT (A)
FIGURE 12. EFFICIENCY, VIN = 5V, fSW = 500kHz
UG067.1
March 17, 2016
User Guide 067
The following data was acquired using a ISL68200DEMO1Z board. (Continued)
92
91
90
89
88
87
86
85
EFFICIENCY (%)
84
83
82
81
VOUT=0.8V
VOUT=1V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
80
95
94
93
92
91
90
89
88
87
86
85
84
VOUT=0.8V
VOUT=1.2V
VOUT=1.8V
83
0
2
4
6
8
10
12
14
16
18
20
22
24
0
2
4
6
8
LOAD CURRENT (A)
25
PWM at Fsw=400kHz
20
PFM EN at Fsw=400kHz
15
PWM at Fsw=500kHz
10
PFM EN at Fsw=500kHz
80
PWM at Fsw=600kHz
5
PFM EN at Fsw=600kHz
77.5
0
-5
75
0
2
4
6
8
10
12
14
16
18
20
22
24
EFFICIENCY (%)
87.5
EFFICIENCY BOOST BY PFM EN (%)
30
82.5
12
14
16
18
20
22
24
FIGURE 14. EFFICIENCY, VIN = 5V, fSW = 600kHz
90
85
10
LOAD CURRENT (A)
FIGURE 13. EFFICIENCY, VIN = 12V, fSW = 600kHz
EFFICIENCY (%)
VOUT=1V
VOUT=1.5V
94
25
92
20
90
15
PWM at Fsw=400kHz
88
PFM EN at Fsw=400kHz
10
PWM at Fsw=500kHz
86
PFM EN at Fsw=500kHz
5
PWM at Fsw=600kHz
84
PFM EN at Fsw=600kHz
82
0
80
-5
0
LOAD CURRENT (A)
2
4
6
8
10
12
14
16
18
20
22
EFFICIENCY BOOST BY PFM EN (%)
EFFICIENCY (%)
Measured Data
24
LOAD CURRENT (A)
FIGURE 15. EFFICIENCY COMPARISON OF PWM MODE AND PFM
ENABLED MODE, VIN = 12V, VOUT =1V
93
FIGURE 16. EFFICIENCY COMPARISON OF PWM MODE AND PFM
ENABLED MODE, VIN = 5V, VOUT =1V
EN
92
PGOOD
PRECHARGED VOUT < 1V
EFFICIENCY (%)
91
90
89
1.14V PRECHARGED VOUT
88
PGOOD AT 1.14V, PRECHARGED VOUT
0.8V PRECHARGED VOUT
87
0.3V PRECHARGED VOUT
ALL RAILS TIED TOGETHER
86
85
LDO ENABLED
84
VOUT WITHOUT PRECHARGE
83
0
2
4
6
8
10
12
14
16
18
20
22
24
LOAD CURRENT (A)
FIGURE 17. EFFICIENCY COMPARISON OF LDO ENABLED AND
BYPASSED, VIN = 5V, VOUT = 1V, fSW = 500kHz
Submit Document Feedback
12
200µs/DIV
FIGURE 18. POWER-UP WITH/WITHOUT PRECHARGE AT 1A LOAD
UG067.1
March 17, 2016
User Guide 067
Measured Data
The following data was acquired using a ISL68200DEMO1Z board. (Continued)
100mV/DIV
10V/DIV
100mV/DIV
10V/DIV
100µs/DIV
100µs/DIV
FIGURE 19. VOUT RAMP-UP FROM 0.5V TO 1V IN PWM MODE
(CH1-VOUT, CH2-PHASE)
100mV/DIV
FIGURE 20. VOUT RAMP-DOWN FROM 1V TO 0.5V IN PWM MODE
(CH1-VOUT, CH2-PHASE)
100mV/DIV
10V/DIV
10V/DIV
100µs/DIV
100µs/DIV
FIGURE 21. VOUT RAMP-UP FROM 0.5V TO 1V IN PFM MODE
(CH1-VOUT, CH2-PHASE)
FIGURE 22. VOUT RAMP-DOWN FROM 1V TO 0.5V IN PFM MODE
(CH1-VOUT, CH2-PHASE)
20mV/DIV
20mV/DIV
10A/DIV
10A/DIV
20µs/DIV
FIGURE 23. STEP RESPONSE AT PWM MODE, VOUT = 1V,
fSW = 400kHz, LOAD PROFILE: 0.25A TO 12.75A AT
25A/µs (CH1-VOUT, CH2-LOAD)
Submit Document Feedback
13
20µs/DIV
FIGURE 24. STEP RESPONSE AT PFM ENABLED MODE, VOUT = 1V,
fSW = 400kHz, LOAD PROFILE: 0.25A TO 12.75A AT
25A/µs (CH1-VOUT, CH2-LOAD)
UG067.1
March 17, 2016
User Guide 067
Measured Data
The following data was acquired using a ISL68200DEMO1Z board. (Continued)
20mV/DIV
20mV/DIV
10A/DIV
10A/DIV
10V/DIV
10V/DIV
5µs/DIV
5µs/DIV
FIGURE 25. STEP RESPONSE TO LOAD STEP AT PWM MODE,
VOUT = 1V, fSW = 400kHz, LOAD PROFILE: 0.25A TO
12.75A AT 25A/µs (CH1-VOUT, CH2-LOAD, CH3-PHASE)
OC RETRY
FIGURE 26. STEP RESPONSE TO LOAD RELEASE AT PWM MODE,
VOUT = 1V, fSW = 400kHz, LOAD PROFILE: 0.25A TO
12.75A AT 25A/µs (CH1-VOUT, CH2-LOAD, CH3-PHASE)
5V/DIV
500mV/DIV
10V/DIV
5V/DIV
100mV/DIV
10ms/DIV
5V/DIV
OC LATCH
5V/DIV
500mV/DIV
100µs/DIV
10V/DIV
50ms/DIV
FIGURE 27. OVERCURRENT PROTECTION
(CH1-VOUT, CH2-PGOOD, CH3-PHASE)
2V/DIV
FIGURE 28. OVERVOLTAGE PROTECTION
(CH1-VOUT, CH2-PGOOD, CH3-LGATE)
5V/DIV
5V/DIV
5V/DIV
5mV/DIV
500mV/DIV
10V/DIV
10V/DIV
20ms/DIV
FIGURE 29. OVER-TEMPERATURE PROTECTION AT 1A LOAD
(CH1-VOUT, CH2-LOAD, CH3-PHASE, CH4-NTC)
Submit Document Feedback
14
200µs/DIV
FIGURE 30. POWER-DOWN AT VOUT = 1V, 1A LOAD
(CH1-VOUT, CH2-PGOOD, CH3-PHASE, CH4-EN)
UG067.1
March 17, 2016
User Guide 067
ISL68200DEMO1Z Board Layout
FIGURE 31. PCB - TOP ASSEMBLY
Submit Document Feedback
15
UG067.1
March 17, 2016
User Guide 067
ISL68200DEMO1Z Board Layout
(Continued)
FIGURE 32. PCB - TOP LAYER
Submit Document Feedback
16
UG067.1
March 17, 2016
User Guide 067
ISL68200DEMO1Z Board Layout
(Continued)
FIGURE 33. PCB - INNER LAYER 2 (TOP VIEW)
Submit Document Feedback
17
UG067.1
March 17, 2016
User Guide 067
ISL68200DEMO1Z Board Layout
(Continued)
FIGURE 34. PCB - INNER LAYER 3 (TOP VIEW)
Submit Document Feedback
18
UG067.1
March 17, 2016
User Guide 067
ISL68200DEMO1Z Board Layout
(Continued)
FIGURE 35. PCB - INNER LAYER 4 (TOP VIEW)
Submit Document Feedback
19
UG067.1
March 17, 2016
User Guide 067
ISL68200DEMO1Z Board Layout
(Continued)
FIGURE 36. PCB - INNER LAYER 5 (TOP VIEW)
Submit Document Feedback
20
UG067.1
March 17, 2016
User Guide 067
ISL68200DEMO1Z Board Layout
(Continued)
FIGURE 37. PCB - BOTTOM LAYER (TOP VIEW)
Submit Document Feedback
21
UG067.1
March 17, 2016
User Guide 067
ISL68200DEMO1Z Board Layout
(Continued)
FIGURE 38. PCB - BOTTOM ASSEMBLY (TOP VIEW)
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the document is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
22
UG067.1
March 17, 2016