User Guide 068
ISL68201-99140DEMO1Z Board User Guide
Key Features
The ISL68201 is a single-phase synchronous buck PWM
controller featuring Intersil’s proprietary R4™ Technology,
which has extremely fast transient performance, accurately
regulated frequency control and all internal compensation. The
ISL68201 supports a wide 4.5V to 24V input voltage range and
a wide 0.5V to 5.5V output range. It includes programmable
functions and telemetries for easy use and high system
flexibility using SMBus, PMBus, or I2C interface. See the
ISL68201 datasheet for more details.
• 35A synchronous buck converter with PMBus control
• On-board transient load with adjustable di/dt
• Configurable through resistor pins
• Cascadable PMBus connectors
• Integrated LDOs for single rail solution
• Enable switch and power-good indicator
The ISL99140 is a high performance DrMOS power stage
designed for high frequency power conversion. By combining a
high performance FET driver and MOSFETs in an advanced
package, high density DC/DC converters may be created.
• All ceramics solution with SP capacitor footprint option
Target Specifications
• VIN = 4.75V to 14.5V
The ISL68201-99140DEMO1Z is a 6-layer board
demonstrating a compact 17mmx17mm 35A synchronous
buck converter. Transient performance, fault protections,
DC/AC regulations, PMBus programming, power sequencing,
margining and other features can be evaluated using this
board.
• VOUT = 1V/35A full load
• fSW = 400kHz
• Peak efficiency:
- 88.3% at 15A/1VOUT/12VIN
- 94.5% at 10A/2.5VOUT/5VIN
The PMBus dongle (ZLUSBEVAL3Z), i.e., USB-to-PMBus™
adapter, and USB cable are included in the demonstration kit.
Intersil’s PowerNavigator™ evaluation software can be
installed from Intersil’s website and evaluate the full PMBus
functionality of the part using a PC running Microsoft
Windows 7 or 8.
• Output regulation: 1V ±8mV
• I/O capacitor rating: CIN - 16V; COUT - 4V
• Compact size: 17mmx17mm
• With or without PMBus/SMBus/I2C capability
References
Ordering Information
• ISL68201 datasheet
PART NUMBER
• AN1900, “USB to PMBus™ Adapter”
ISL6820199140DEMO1Z
• Intersil’s PowerNavigator™ User Guide
1.0µF
DESCRIPTION
ISL68201-99140 demonstration kit
(demonstration board, dongle, USB cable)
4.7µ F
VCC
PVCC
VIN
7VLDO
4.75 TO 15V
1.0µF
2
I C/
SMBus/
PMBus
SALERT
SCL
SDA
PGOOD
FCCM
PGOOD
EN
ISL99140
PWM
PWM
PHASE
LG
LGIN
IOUT
‐
V OUT < 7VLDO 1.7V
0.5V TO 2.5V
UG
EN
VCC
BOOT
100
10k
NTC
VCC
1.54k
VCC
NTC
0.1µF
4
PROG1-4
NCP18XH103J03RB
BETA = 3380
CSEN
CSRTN
VSEN
RGND
GND
FIGURE 1. ISL68201-99140DEMO1Z SIMPLIFIED SCHEMATIC
March 10, 2016
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved
Intersil (and design), PowerNavigator and R4 Technology are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
User Guide 068
FIGURE 2. DEMONSTRATION BOARD TOP VIEW
Demonstration Board Description
The ISL68201-99140DEMO1Z provides all circuitry required to
demonstrate the key features of the ISL68201. A majority of the
features of the ISL68201, such as optimal transient response
with Intersil’s R4™ Modulator, 8-bit programmable boot voltage
levels, selectable switching frequency in continuous conduction
mode, selectable PFM operation option for improved light-load
efficiency, power-good monitor for soft-start and fault detection,
over-temperature protection, output overcurrent and short-circuit
protection, and output overvoltage protection are available on
this demonstration board.
Figure 1 shows a simplified schematic diagram of the
ISL68201-99140DEMO1Z board. Figure 6 shows the detailed
35A buck solution schematics, while Figure 7 shows the I/O
connectors, auxiliary circuits and on-board transient circuits.
Figures 8 through 30 show typical performance data and
Figures 31 through 38 show the PCB board layout. The default
programming pins setting is given on the upper right corner of
Figure 6 and the Bill of Materials (BOM) is included for reference
beginning on page 9.
FIGURE 3. DEMONSTRATION BOARD BOTTOM VIEW
Furthermore, an on-board transient load, as shown on Figure 4,
with di/dt and load step amplitude is controlled by a function
generator. Since this auxiliary circuit draws more than 10mA
current, the jumper on JP5 should be removed for accurate
efficiency measurement.
Intersil’s PowerNavigator™ evaluation software is compatible
with Windows XP, 7 or 8 operating systems and can be used to
evaluate the series bus functionality of the ISL68201. The
software and user guide can be found on following Intersil
website: http://www.intersil.com/powernavigator.
Quick Start Guide
Stand-Alone Operation
1. Set ENABLE switch to “OFF” position.
2. Connect a power supply (off) to input connectors (J4-VIN and
J2-GND).
3. Set input power supply voltage level (no more than 15V) and
current limiting (no more than 1A for 0A load).
4. Turn the power supply on.
The ISL68201-99140DEMO1Z board can run by itself without a
series bus communication. The operational configuration is fully
programmable via the programming pins (PROG1-4).
5. Set ENABLE switch to “ON” position.
The ISL68201 however, utilizes the PMBus/SMBus/I2C protocol
and provides the flexibility for digital power management and
performance optimization prior to finalizing the hardware
configuration on the programming pins.
7. Apply load to output connectors (J1-VOUT and J2-SGND).
The buck regulator in the ISL68201-99140DEMO1Z board is a
single input rail design, i.e., everything is biased by the input
supply (typically 12V). The resistor divider on the EN pin (R4 and
R12) can set the input supply undervoltage protection level and
its hysteresis. The “ENABLE” switch is a hardware operational
control, alternately, the series bus ON_OFF_CONFIG and
OPERATION commands can be used for software operational
control.
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6. Increase power supply current limit enough to support more
than the full load.
8. Monitor operation using an oscilloscope.
PMBus Operation
1. Connect supplied Intersil’s dongle to J9.
2. Connect supplied USB cable from computer to the dongle.
3. After the input supply powers up, open the PowerNavigator
evaluation software.
4. Select detected ISL68201 device (Address - 60h) and follow
Intersil’s PowerNavigator™ user guide.
5. Monitor and configure the board using PMBus commands in
the evaluation software.
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User Guide 068
Configuration
Load Transient
The default programming pin settings of the
ISL68201-99140DEMO1Z board can be found at the resistor
reader table on the upper right corner of “ISL6820199140DEMO1Z Schematics” on page 7 or read back via Intersil’s
PowerNavigator™ software. Each PMBus command can be
loaded or programmed via the PowerNavigator™ software. Note
that ISL68201 does not have NVM to store the operational
configuration however, it can be set by the resistor programming
pins (PROG1-4) or programmed by the series bus master before
powering up. If a series bus master is available in the system, the
ISL68201-based rail can be fully controlled via software for the
power-up/power-down sequencing and operational configuration
without a soldering iron.
The on-board transient load can be controlled by a function
generator, whose inputs are connected to FG_DRIVE2 and
FG_GND2. The function generator’s output is terminated by R42
at the input terminal, while its amplitude and dV/dt set the load
amplitude and di/dt on the 50mΩ load (RLT1//RLT2). The
transient load can be monitored with a scope probe on TP15.
Note that the duty cycle of applied load should be less than 10%
duty cycle with <10ms pulse width to keep the average power of
RLT1/RLT2 less than its power rating.
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FIGURE 4. ON-BOARD LOAD TRANSIENT
FIGURE 5. ISL68201-99140DEMO1Z DEMONSTRATION KIT SET-UP
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User Guide 068
Design Modifications
When modifying the design, it will require a new set of L/DCR
matching for different inductor, divider on the PROG pins for
different operational configuration, RSEN1 for OCP, and IOUT
network for accurate digital IOUT; higher input capacitor rating to
support higher than 16V input, higher output capacitor rating to
support higher than 4V output. Refer to ISL68201 datasheet and
PowerNavigator™ software for proper design modifications
including L/DCR matching, thermal compensation, OCP and
digital IOUT fine tuning.
Two examples are provided in Table 1, showing the
recommended design modifications to accommodate the
application cases with 5V and 3.3V output voltages. Some fine
tuning might be needed depending upon the rework and final
layout design.
For the 5V input voltage applications with 4.5V < VIN < 5.5V
requirement, the “VIN”, “VCC”, “PVCC” and “7VLDO” pins should
be shorted together, to connect with the input supply for optimal
performance; R12 should be removed as well.
Note that all devices in the same bus should set different
addresses for unique identification and proper communication.
JP2, 3, 9 and 10 connectors are designed to cascade many
Intersil's solutions for easy communication and system
evaluation prior to the system integration and design.
TABLE 1. DESIGN EXAMPLES
REFERENCE
DESIGNATOR
5.0V AT 16A
L1
3.3V AT 16A
680nH, 1.72mΩ
Vendor: Wurth Electronic;
Part Number: 744334006
CO5, CO6, CO8,
CO9
3.3V AT 30A
COMMENTS
470nH, 0.165mΩ
Vendor: Wurth Electronic;
Part Number: 744309047
Reduce Output ripple current; typically higher
voltage output needs higher inductance.
Increase COUT rating to support higher VOUT.
Also capacitance of ceramic capacitors
decreases with increased output voltage.
100µF/X5R/6.3V/1206
Vendor: Murata;
Part Number: GRM21BR60J107ME11
PROG1 (DC)
DFh
BFh
BFh
Set correct VBOOT = VOUT
R3
147k, 1%
105k, 1%
105k, 1%
PROG2 (DD)
A0h
BFh
BFh
R5
105k, 1%
DNP
DNP
R6
DNP
105k, 1%
105k, 1%
PROG3 (DE)
0Dh
0Dh
0Dh
R8
24.3k, 1%
24.3k, 1%
24.3k, 1%
R9
16.9k, 1%
16.9k, 1%
16.9k, 1%
PROG4 (DF)
08h
08h
08h
R10
15k, 1%
15k, 1%
15k, 1%
R11
29.4k, 1%
29.4k, 1%
29.4k, 1%
RP1
4.99k, 1%
4.99k, 1%
3.57k, 1%
RSEN1
536, 1%
536, 1%
62, 1%
Set OCP
R13
11k, 1%
11k, 1%
15k, 1%
Set IOUT to 1A/1A Slope
R14
TBD
TBD
TBD
Set Different PMBus Addresses as needed
TCOMP = 15
PFM DISABLED
Set AV = 13
fSW = 500kHz
OCP = Retry
25kHz Clamp Disabled
Set RR = 400k
SS = 1.25mV/µs
AVMLTI = 1x
L/DCR Matching
Pull-up value depends upon final layout
design
NOTE: Some fine tuning might be needed depending upon the rework and final layout design.
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User Guide 068
Design and Layout
Considerations
TABLE 2. DESIGN AND LAYOUT CHECKLIST (Continued)
To ensure a first pass design, the schematics design must be
done correctly and the board must be carefully laid out.
PIN
NAME
NOISE
SENSITIVITY
SCL, SDA
Yes
50kHz to 1.25MHz signal when the SMBus,
PMBus, or I2C is sending commands. Pairing
up with SALERT and routing carefully back to
SMBus, PMBus or I2C master. 20 mils spacing
within SDA, SALERT, and SCL; and more than
30 mils to all other signals. Refer to the
SMBus, PMBus or I2C design guidelines and
place proper terminated (pull-up) resistance
for impedance matching. Tie them to GND
when not used.
SALERT
No
Open-drain and high dv/dt pin during
transitions. Route it in the middle of SDA and
SCL. Tie it to GND when not used.
PGOOD
No
Open-drain pin. Tie it to ground when not used.
RGND,
VSEN
Yes
Differential pair routed to the remote sensing
points with sufficient decoupling ceramics
capacitors and not across or go above/under
any switching nodes (BOOT, PHASE, UGATE,
LGATE) or planes (VIN, PHASE, VOUT) even
though they are not in the same layer. At least
20 mils spacing from other traces. DO NOT
share the same trace with CSRTN.
CSRTN
Yes
Connect to the output rail side of the output
inductor or current sensing resistor pin with a
series resistor in close proximity to the pin. The
series resistor sets the current gain and should
be within 40Ω and 3.5kΩ. Decoupling
(~0.1µF/X7R) on the output end (not the pin) is
optional and might be required for long sense
trace and a poor layout.
CSEN
Yes
Connect to the phase node side of the output
inductor or current sensing resistor pin with
L/DCR or ESL/RSEN matching network in close
proximity to CSEN and CSRTN pins.
Differentially routing back to the controller
with at least 20 mils spacing from other traces.
Should NOT cross or go above/under the
switching nodes [BOOT, PHASE, UGATE, LGATE]
and power planes (VIN, PHASE, VOUT) even
though they are not in the same layer.
NTC
Yes
Place NTC 10k (Murata, NCP15XH103J03RC,
= 3380) in close proximity to the output
inductor’s output rail, not close to MOSFET
side; the return trace should be 20 mils away
from other traces. Place 1.54kΩ pull-up and
decoupling capacitor (typically 0.1µF) in close
proximity to the controller. The pull-up resistor
should be exactly tied to the same point as VCC
pin, not through an RC filter. If not used,
connect this pin to VCC.
IOUT
Yes
Scale R such that IOUT pin voltage is 2.5V at
63.875A load. Place R and C in general
proximity to the controller. The time constant
of RC should be sufficient as an averaging
function for the digital IOUT. An external pull-up
resistor to VCC is recommended to cancel IOUT
offset at 0A load.
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board or internal layers.
The ground-plane layer should be in between the power layers
and the signal layers to provide shielding. Often, the layer below
the top and the layer above the bottom should be the ground
layers.
There are two sets of components in a DC/DC converter, the
power components and the small signal components. The power
components are the most critical because they switch large
amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors and the inductor. Keeping
the distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, GND, PHASE and BOOT.
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible. Input high frequency capacitors should be
placed close to the drain of the upper MOSFETs and the source of
the lower MOSFETs. Place the output inductor and output
capacitors between the MOSFETs and the load. High frequency
output decoupling capacitors (ceramic) should be placed as
close as possible to the decoupling target, making use of the
shortest connection paths to any internal planes. Place the
components in such a way that the area under the IC has less
noise traces with high dV/dt and di/dt, such as gate signals,
phase node signals and VIN plane.
Tables 2 and 3 provide a design and layout checklist that a
designer must pay attention to.
TABLE 2. DESIGN AND LAYOUT CHECKLIST
PIN
NAME
NOISE
SENSITIVITY
EN
Yes
There is an internal 1µs filter. Decoupling the
capacitor is NOT needed. However, if needed,
use a low time constant one to avoid too large
a shutdown delay.
VIN
Yes
Place 16V+ X7R 1µF in close proximity to the
VIN pin and the system ground plane.
7VLDO
Yes
Place 10V+ X7R 1µF in close proximity to the
7VLDO pin and the system ground plane.
VCC
Yes
Place X7R 1µF in close proximity to the VCC pin
and the system ground plane.
DESCRIPTION
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DESCRIPTION
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User Guide 068
TABLE 2. DESIGN AND LAYOUT CHECKLIST (Continued)
PIN
NAME
NOISE
SENSITIVITY
PROG1-4
No
Resistor divider must be referenced to VCC pin
and the system ground; they can be placed
anywhere. DO NOT use decoupling capacitors
on these pins.
GND
Yes
Directly connect to low noise area of the
system ground. The GND PAD should use at
least 4 vias. Separate analog ground and
power ground with a 0Ω resistor is highly NOT
recommended.
DESCRIPTION
FCCM
No
DO NOT make it across or under external
components of the controller. Keep it at least
20 mils away from sensitive nodes.
PWM
No
DO NOT make it across or under external
components of the controller. Keep it at least
20 mils away from any other traces.
LGIN
No
Keep it at least 20 mils away from sensitive
nodes. A series 100Ω resistor to low-side gate
signal is required for noise attenuation.
PVCC
Yes
Place X7R 4.7µF in proximity to the PVCC pin
and the system ground plane.
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s
TABLE 3. TOP LAYOUT TIPS
NUMBER
DESCRIPTION
1
The layer next to controller (top or bottom) should be a ground
layer. Separate analog ground and power ground with a 0Ω
resistor is highly NOT recommended. Directly connect GND
PAD to low noise area of the system ground with at least 4
vias.
2
Never place a controller and its external components above
or under VIN plane or any switching nodes.
3
Never share CSRTN and VSEN on the same trace.
4
Place the input rail decoupling ceramic capacitors closely to
the high-side FET. Never use only one via and a trace to
connect the input rail decoupling ceramics capacitors; must
connect to VIN and GND planes.
5
Place all decoupling capacitors in close proximity to the
controller and the system ground plane.
6
Connect remote sense (VSEN and RGND) to the load and
ceramic decoupling capacitors nodes; never run this pair
below or above switching noise plane.
7
Always double check critical component pinout and their
respective footprints.
UG068.0
March 10, 2016
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ISL68201-99140DEMO1Z Schematics
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ISL68201-99140DEMO1Z Schematics (Continued)
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User Guide 068
Bill of Materials
QTY
REFERENCE
DESIGNATOR
1
U1
1
DESCRIPTION
PCB FOOTPRINT
MANUFACTURER
PART NUMBER
R4 Wrapper
QFN24_157X157_197_EPC
INTERSIL
ISL68201IRZ-REVC
UD1
40A DrMOS PWR MODULE
EPQFN40_6X6
INTERSIL
ISL99140IRZ
1
CIN1
270µF/16V/8x9/10mΩ
CAPR_315X275_150_P
SANYO
16SEPC270MX
1
C1
4.7µF/6.3V/X5R
SM0603
VENKEL
C0603X5R6R3-475KNE
2
C2, C3
1.0µF/16V/X7R
SM0402
TDK
C1005X5R1C105K050BC
1
C4
1µF/6.3V/X5R
SM0402
PANASONIC
ECJ-0EB0J105K
1
C5
22nF/50V/X7R
SM0402
JOHANSON
DIELECTRICS INC
500R07W223KV4T
1
C6
0.1µF/16V/X7R
SM0603
MURATA
GRM39X7R104K016AD
3
CB2, CC1, CNTC1
0.1µF/16V/X7R
SM0402
VENKEL
C0402X7R160-104KNE
4
C10, C11, C19, C20 22µF/16V/X5R
SM0805
VENKEL
C0805X5R160-226KNE
4
CO5, CO6, CO8, CO9 220µF/4V/X5R
SM1206
MURATA
GRM31CR60G227ME11
1
L1
175nH, 0.29mΩ
SMD, 10.4X7.9
PULSE
PA2607.181NLT
1
R2
75kΩ, 1%
SM0402
VENKEL
CR0402-16W-7502FT
1
R4
100kΩ, 1%
SM0603
VENKEL
CR0603-10W-1003FT
1
R5
105kΩ, 1%
SM0402
VENKEL
CR0402-16W-1053FT
1
R8
15kΩ, 1%
SM0402
PANASONIC
ERJ-3EKF1502V
1
R9
29.4kΩ, 1%
SM0402
VENKEL
CR0402-16W-2942FT
1
R10
10kΩ, 1%
SM0402
PANASONIC
ERJ-2RKF1002X
3
R15, R16, R17
10kΩ, 1%
SM0603
VENKEL
CR0603-10W-1002FT
1
R12
24.9kΩ, 1%
SM0603
PANASONIC
ERJ-3EKF2492V
1
R13
15.8kΩ, 1%
SM0402
YAGEO
RC0402FR-0715K8L
1
R21
100Ω, 1%
SM0402
VENKEL
CR0402-16W-101JT
2
R30, R31
0Ω
SM0402
PANASONIC
ERJ-2RKF00R0X
1
RBLD1
121Ω, 1%
SM0603
VISHAY/DALE
CRCW0603121RFKTA
1
RNTC1
10kΩ NTC, 5%, = 3380
SM0402
MURATA
NCP15XH103J03RC
1
RP1
7.68kΩ, 1%
SM0402
PANASONIC
ERJ-2RKF7681X
1
RSEN1
137Ω, 1%
SM0402
PANASONIC
ERJ-2RKF1370X
1
RTM1
1.54kΩ, 1%
SM0402
PANASONIC
ERJ-2RKF1541X
DEMONSTRATION BOARD SPECIFIC AUXILIARY PARTS BILL OF MATERIALS
1
U2
Dual Amp/500MHz/5V
SOIC8
INTERSIL
EL8203ISZ
1
QU2
8mΩ N-MOSFET
LFPAK
INFINEON
BSC080N03LS G
1
DS1
LED/RED/0805/CLEAR
SM0805
WURTH ELEKTRONIK
150080RS75000
1
SW1
Enable Switch
GT11SC
C&K DIVISION
GT11MSCBE
1
C12
4.7µF/6.3V/X5R
SM0603
VENKEL
C0603X5R6R3-475KNE
2
C13, C55
0.1µF/16V/X7R
SM0402
VENKEL
C0402X7R160-104KNE
1
C16
1µF/6.3V/X5R
SM0402
PANASONIC
ECJ-0EB0J105K
1
C17
22pF/50V/C0G
SM0603
VENKEL
C0603C0G500-220JNE
1
C18
100pF/50V/C0G
SM0603
PANASONIC
ECJ-1VC1H101J
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User Guide 068
Bill of Materials (Continued)
QTY
REFERENCE
DESIGNATOR
2
J1, J2
1
DESCRIPTION
PCB FOOTPRINT
MANUFACTURER
PART NUMBER
Screw Terminal
B2C-PCB
INTERNATIONAL
HYDRAULICS INC
B2C-PCB
J3
Female Banana Jack, Black
111-07xx-001
JOHNSON
COMPONENTS
111-0703-001
1
J4
Female Banana Jack, Red
111-07xx-001
JOHNSON
COMPONENTS
111-0702-001
2
J8, J9
CONN-HEADER, 2x3, BRKAWY,
2.54mm, TIN
CONN6
SAMTEC
TSW-103-08-T-D-RA
2
J10, J11
CONN-SOCKET STRIP, TH, 2x3,
2.54mm, TIN
CONN6
SAMTEC
SSQ-103-02-T-D-RA
2
JP1, JP4
2-pin 0.1'' spacing Jumper
CONN2
BERG/FCI
69190-202HLF
1
TP1
Probe Ground
TP-150C100P-RTP
KEYSTONE
1514-2
2
TP2, TP14
Probe Jack
TEK131-4353-00
TEKTRONIX
131-4353-00
4
TP3, TP4, TP5, TP6
Test Point
MTP500x
KEYSTONE
5002
2
VCC12, FG_DRIVE
Test Point RED
MTP500x
KEYSTONE
5000
2
VIN_GND, FG_GND
Test Point BLACK
MTP500x
KEYSTONE
5001
SM0603
VENKEL
CR0603-10W-03R0FT
4
R32, R33, R36, R37 3Ω, 1%
1
R34
2kΩ, 1%
SM0603
KOA
RK73H1JTTD2001F
1
R39
2.49kΩ, 1%
SM0603
KOA
RK73H1JTTD2491F
1
R42
52.3Ω, 1%
SM0603
PANASONIC
ERJ-3EKF52R3V
1
R41
274Ω, 1%
SM0603
VENKEL
CR0603-10W-2740FT
1
R43
124kΩ, 1%
SM0603
YAGEO
9C06031A1243FKHFT
2
R45, R46
499Ω, 1%
SM0603
VENKEL
CR0603-10W-4990FT
2
RLT1, RLT2
0.1Ω, 1%
SM2512
CTS RESISTOR
73L7R10J
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40
0.1
35
0
30
SLOPE = 1
-0.1
25
-0.2
20
-0.3
15
-0.4
10
-0.5
5
0
0
5
10
15
20
25
30
35
-0.6
ERROR (DIGITAL IOUT-LOAD) (A)
DIGITAL IOUT (A)
Performance Data
LOAD CURRENT (A)
92
91
90
89
88
87
86
85
84
83
82
81
80
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 8. TYPICAL DIGITAL OUTPUT CURRENT
0
2.5
5
VOUT=0.8V
VOUT=1V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
VOUT=2.5V
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VOUT=0.8V
VOUT=1.2V
VOUT=1.8V
0
2.5
5
LOAD CURRENT (A)
FIGURE 10. EFFICIENCY, VIN = 5V, fSW = 400kHz
93
92
91
EFFICIENCY (%)
EFFICIENCY (%)
89
88
87
86
85
84
VOUT=0.8V
VOUT=1.2V
VOUT=1.8V
83
82
81
0
VOUT=1V
VOUT=1.5V
VOUT=2.5V
2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35
LOAD CURRENT (A)
FIGURE 11. EFFICIENCY, VIN = 12V, fSW = 500kHz
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11
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35
LOAD CURRENT (A)
FIGURE 9. EFFICIENCY, VIN = 12V, fSW = 400kHz
90
VOUT=1V
VOUT=1.5V
VOUT=2.5V
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
VOUT=0.8V
VOUT=1.2V
VOUT=1.8V
0
2.5 5
VOUT=1V
VOUT=1.5V
VOUT=2.5V
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35
LOAD CURRENT (A)
FIGURE 12. EFFICIENCY, VIN = 5V, fSW = 500kHz
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User Guide 068
Performance Data (Continued)
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
EFFICIENCY (%)
VOUT=0.8V
VOUT=1.2V
VOUT=1.8V
VOUT=1V
VOUT=1.5V
VOUT=2.5V
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35
VOUT=0.8V
VOUT=1.2V
VOUT=1.8V
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35
LOAD CURRENT (A)
LOAD CURRENT (A)
FIGURE 14. EFFICIENCY, VIN = 5V, fSW = 600kHz
25
87.5
20
15
PWM at Fsw=400kHz
PFM EN at Fsw=400kHz
PWM at Fsw=500kHz
PFM EN at Fsw=500kHz
PWM at Fsw=600kHz
PFM EN at Fsw=600kHz
82.5
80
77.5
75
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35
10
5
0
-5
95
18
92.5
16
14
90
EFFICIENCY (%)
90
EFFICIENCY BOOST BY PFM EN (%)
EFFICIENCY (%)
FIGURE 13. EFFICIENCY, VIN = 12V, fSW = 600kHz
85
12
87.5
10
PWM at Fsw=400kHz
PFM EN at Fsw=400kHz
PWM at Fsw=500kHz
PFM EN at Fsw=500kHz
PWM at Fsw=600kHz
PFM EN at Fsw=600kHz
85
82.5
80
77.5
75
FIGURE 15. EFFICIENCY COMPARISON OF PWM MODE AND PFM
ENABLED MODE, VIN = 12V, VOUT = 1V
92
8
6
4
2
0
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35
-2
LOAD CURRENT (A)
LOAD CURRENT (A)
FIGURE 16. EFFICIENCY COMPARISON OF PWM MODE AND PFM
ENABLED MODE, VIN = 5V, VOUT = 1V
EN 5V/DIV
91
90
EFFICIENCY (%)
VOUT=1V
VOUT=1.5V
VOUT=2.5V
EFFICIENCY BOOST BY PFM EN (%)
EFFICIENCY (%)
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
PGOOD
PRECHARGED VOUT <1V 5V/DIV
89
88
87
1.14V PRECHARGED VOUT 500mV/DIV
86
0.8V PRECHARGED VOUT 500mV/DIV
ALL RAILS TIED TOGETHER
85
84
LDO ENABLED
83
PGOOD AT 1.14V
PRECHARGED VOUT 5V/DIV
0.3V PRECHARGED
VOUT 500mV/DIV
VOUT W/O PRE-CHARGE 500mV/DIV
82
0 2.5 5
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35
LOAD CURRENT (A)
FIGURE 17. EFFICIENCY COMPARISON OF LDO ENABLED AND
BYPASSED, VIN = 5V, VOUT = 1V, fSW = 500kHz
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200µs/DIV
FIGURE 18. POWER-UP WITH/WITHOUT PRE-CHARGED LOAD
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User Guide 068
Performance Data (Continued)
100mV/DIV
10V/DIV
100mV/DIV
10V/DIV
100µs/DIV
100µs/DIV
FIGURE 19. VOUT RAMP-UP FROM 0.5V TO 1V IN PWM MODE
(CH1-VOUT, CH2-PHASE)
100mV/DIV
10V/DIV
FIGURE 20. VOUT RAMP-DOWN FROM 1V TO 0.5V IN PWM MODE
(CH1-VOUT, CH2-PHASE)
100mV/DIV
10V/DIV
100µs/DIV
FIGURE 21. VOUT RAMP-UP FROM 0.5V TO 1V IN PFM MODE
(CH1-VOUT, CH2-PHASE)
100µs/DIV
FIGURE 22. VOUT RAMP-DOWN FROM 1V TO 0.5V IN PFM MODE
(CH1-VOUT, CH2-PHASE)
20mV/DIV
20mV/DIV
10A/DIV
10A/DIV
20µs/DIV
FIGURE 23. STEP RESPONSE AT PWM MODE, VOUT = 1V,
fSW = 400kHz, LOAD PROFILE: 0.25A TO 12.75A AT
25A/µs (CH1-VOUT, CH2-LOAD)
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20µs/DIV
FIGURE 24. STEP RESPONSE AT PFM ENABLED MODE, VOUT = 1V,
fSW = 400kHz, LOAD PROFILE: 0.25A TO 12.75A AT
25A/µs (CH1-VOUT, CH2-LOAD)
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User Guide 068
Performance Data (Continued)
20V/DIV
20V/DIV
10A/DIV
10A/DIV
10V/DIV
10V/DIV
5µs/DIV
5µs/DIV
FIGURE 25. STEP RESPONSE TO LOAD STEP AT PWM MODE,
VOUT = 1V, fSW = 400kHz, LOAD PROFILE: 0.25A TO
12.75A AT 25A/µs (CH1-VOUT, CH2-LOAD, CH3-PHASE)
FIGURE 26. STEP RESPONSE TO LOAD RELEASE AT PWM MODE,
VOUT = 1V, fSW = 400kHz, LOAD PROFILE: 0.25A TO
12.75A AT 25A/µs (CH1-VOUT, CH2-LOAD, CH3-PHASE)
OC RETRY
5V/DIV
500mV/DIV
10V/DIV
5V/DIV
10ms/DIV
100mV/DIV
OC LATCH
5V/DIV
5V/DIV
500mV/DIV
10V/DIV
100µs/DIV
10ms/DIV
FIGURE 27. OVERCURRENT AND SHORT-CIRCUIT PROTECTION
(CH1-VOUT, CH2-PGOOD, CH3-PHASE)
FIGURE 28. OVERVOLTAGE PROTECTION
(CH1-VOUT, CH2-PGOOD, CH3-LGATE)
5V/DIV
2V/DIV
5V/DIV
5V/DIV
500mV/DIV
500mV/DIV
10V/DIV
10V/DIV
20ms/DIV
FIGURE 29. OVER-TEMPERATURE PROTECTION AT 1A LOAD
(CH1-VOUT, CH2-LOAD, CH3-PHASE, CH4-NTC)
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14
200µs/DIV
FIGURE 30. POWER-DOWN AT VOUT = 1V, 1A LOAD
(CH1-VOUT, CH2-PGOOD, CH3-PHASE, CH4-EN)
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ISL68201-99140DEMO1Z Board Layout
FIGURE 31. PCB - TOP ASSEMBLY
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ISL68201-99140DEMO1Z Board Layout
(Continued)
FIGURE 32. PCB - TOP LAYER
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ISL68201-99140DEMO1Z Board Layout
(Continued)
FIGURE 33. PCB - INNER LAYER 2 (TOP VIEW)
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ISL68201-99140DEMO1Z Board Layout
(Continued)
FIGURE 34. PCB - INNER LAYER 3 (TOP VIEW)
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ISL68201-99140DEMO1Z Board Layout
(Continued)
FIGURE 35. PCB - INNER LAYER 4 (TOP VIEW)
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ISL68201-99140DEMO1Z Board Layout
(Continued)
FIGURE 36. PCB - INNER LAYER 5 (TOP VIEW)
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ISL68201-99140DEMO1Z Board Layout
(Continued)
FIGURE 37. PCB - BOTTOM LAYER (TOP VIEW)
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ISL68201-99140DEMO1Z Board Layout
(Continued)
FIGURE 38. PCB - BOTTOM ASSEMBLY (TOP VIEW)
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the document is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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