SmartLEWIS TM RX+
TDA5240/35/25 Explorer
Configuration and Evaluation Software B12.6.33-51
High Sensitivity Receiver with
Digital Baseband Processing (TDA5240/35) /
Digital Slicer (5225)
Regis ter Valu e Cal c ulatio ns
Addendum to Data Sheet
Released, 2011-03-11
Wirel ess Con trol
Rev0.1 2011-03-11
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
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warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual
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TDA5240/35/25 Explorer
Register Value Calculations
Explorer Calculation
Revision History: 2011-03-11, Released
Previous Revision:
Page
Subjects (major changes since last revision)
Update of formulas
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Last Trademarks Update 2011-02-24
TDA5240/35/25 Explorer
Register Value Calculations
Table of Contents
Table of Contents
Introduction ............................................................................................................................................................ 5
1
1.1
Wizard Page 2 – RF PLL .................................................................................................................... 5
Spur warning ........................................................................................................................................ 6
2
2.1
2.2
2.3
Wizard Page 5 – Digital Receiving Unit ............................................................................................ 7
Datarate Calculation for TDA5240/35 ................................................................................................ 10
Datarate Calculation for TDA5225 ..................................................................................................... 12
Modifications for Jitter optimized Datarate Calculation ...................................................................... 14
3
Wizard Page 6 – Clock Data Recovery ........................................................................................... 15
4
Wizard Page 7 – Frame Synchronization Unit ............................................................................... 15
5
Wizard Page 9 – Polling Timer Unit ................................................................................................ 15
6
Wizard Page 10 – AFC AGC ............................................................................................................ 17
Application Note
4
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TDA5240/35/25 Explorer
Register Value Calculations
Wizard Page 2 – RF PLL
Introduction
This document describes all calculations for registers implemented by the TDA5240/35/23 Explorer software.
Calculations that recover input values from register values are not covered by this document. Some calculations
are valid for multiple configuration pages (Config A,B,C,D) of the chip. Affected register names contain the
placeholder %Page%.
The crystal oscillator frequency is changeable in the Explorer software. However, for this document a constant
input of 21.948717 MHz is used for the system frequency.
Arguments of a function are separated by a comma. Digits of a floating point number are separated by a dot.
Definitions for rounding functions are:
Math rounding:
the number was at the half way point
Example:
;
Bankers rounding:
half way point
Example:
Rounds to the next higher integer away from zero number if
Rounds to the even number if the number was at the
;
is the largest integer not greater than x
is the smallest integer not less than x
is the numerical value of x without regard to its sign
Definitions for logical functions are:
is true if at least one of the conditions evaluates to true
is true if both conditions evaluates to true
Definitions for notations in the set theory are:
is the collection of points which are in X or in Y (or in both)
:= The empty set is the set having no elements
Wizard Page 2 – RF PLL
1
Input variables and constants:
System frequency;
RF channel frequency for channel ch: rf(ch) [MHz]; ch
Single/Double conversion selection: ifconv = (SFR_%Page%_IF1.SDCSEL)
RXRF Receive Side Band Select: sbsel = (SFR_%Page%_IF1.SSBSEL)
Channels; Channels = {1, 2, 3}
Intermediate variables:
Single/Double conversion frequency: conv [MHz]
Output variables and registers allocation:
ISM band: ismb(ch) = (SFR_%Page%_PLLINTC1.BANDSEL)
PLL Fractional Division Ratio: fracdiv(ch) =
(SFR_%Page%_PLLFRAC2C(ch),SFR_%Page%_PLLFRAC1C(ch),SFR_%Page%_PLLFRAC0C(ch))
Fractional Spurii Compensation: fraccomp(ch) = (SFR_%Page%_PLLFRAC2C(ch).PLLFCOMPC(ch))
:= 0
PLL Multi Modulus Divider Integer Offset: mmdiv(ch) = (SFR_%Page%_PLLINTC1.PLLINTC(ch))
Application Note
5
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Register Value Calculations
Wizard Page 2 – RF PLL
Explorer version > B12.6.37 uses
1.1
instead of
Spur warning
Input variables and constants:
EMI Source: fEmi [MHz] (fEmi can be an external EMI source or the crystal itself)
Maximal spur frequency: fMax [MHz] := 3000
Wanted bandwith: fWantedBW [MHz] := 0.3
Intermediate variables and sets:
Local oscillator harmonics for low side injection: fLOharmoniclow [MHz]
Local oscillator harmonics for high side injection: fLOharmonichigh [MHz]
Mixer sideband: nSideband
The set of spurs when using low side injection: FDeltaLow
The set of spurs when using high side injection: FDeltaHigh
Output variables:
The value the crystal oscillator frequency must be shifted to avoid spurs in the actual channel:
fDeltaMax [MHz]
Spur warning: spurWarning SpurWarnings; SpurWarnings = {“No spur detected”, “Crystal frequency
shift”, “Low side injection recommended”, “High side injection recommended”}
Application Note
6
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Register Value Calculations
Wizard Page 5 – Digital Receiving Unit
Note: If the variable “spurWarning” evaluates to “Crystal frequency shift”, then a crystal oscillator frequency shift
by fDeltaMax MHz is needed to avoid a spur.
Wizard Page 5 – Digital Receiving Unit
2
Input variables and constants:
System frequency;
Datarate: datarate [bit/s]
Chip per bit selection: cpb := 1 if one chip per bit is selected, 2 if two chip per bit is selected
Attack (Up) Time: attTime [bit]
Decay (Down) Time: decTime [bit]
Expected max. FSK deviation: fdev [+/-kHz]
Expected min. FSK deviation: fdevmin [+/-kHz]
Modulation type: modtype = (SFR_%Page%_CHCFG.MT) (taken from Wizard page 1 – Master Control
Unit)
modtype=0 Pure ASK
modtype=1 Pure FSK
modtype>1 Mixed Mode
Band Pass Filter Bandwidth (analog BW): bpf = (SFR_%Page%_IF1.BPFBWSEL)
Application Note
7
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Register Value Calculations
Wizard Page 5 – Digital Receiving Unit
Predemodulation Bandwidth (digital BW): dbpf = (SFR_%Page%_ISUPFCSEL.FCSEL)
Settling Time: stime [bit]
Intermediate variables:
Band Pass Filter Bandwidth (analog BW): bpfBW [kHz]
Predemodulation Bandwidth (digital BW): dbpf BW [kHz]
Maximum frequency offset: foffsetmax [kHz]
Minimum frequency offset: foffsetmin [kHz]
Maximum amplitude of FSK offset after predecimation before scaling: predec_max_bs_offset
Maximum amplitude of FSK deviation after predecimation before scaling: predec_max_bs_fdev
Maximum amplitude of ASK output after predecimation before scaling: predec_max_bs
Minimal scaling for given coefficient: scalmin
Selector for minimal scaling: selmin
Output variables and registers allocation:
Attack factor: attFactor = (SFR_%Page%_PMFUDSF.PMFUP)
Decay factor: decFactor = (SFR_%Page%_PMFUDSF.PMFDN)
Downsampling of signal after arctan demodulation:
(SFR_%Page%_PDECF.PREDECF)
Matched filter: mf = (SFR_%Page%_MFC.MFL)
Sample rate converter: src = (SFR_%Page%_SRC) | min=0 < max=255
Predecimation Block Scaling Factor for ASK: pdscaleASK = (SFR_%Page%_PDECSCASK.PDSCALEA)
Predecimation Block Scaling Factor for FSK: pdscaleFSK = (SFR_%Page%_PDECSCFSK.PDSCALEF)
FSK data interpolation enable: interpolFSK = (SFR_%Page%_PDECSCFSK.INTPOLENF)
ASK data interpolation enable: interpolASK = (SFR_%Page%_PDECSCASK.INTPOLENA)
Saturation threshold of the Sigdet peak detector used for zero-tube threshold calculation: pd =
(SFR_%Page%_SIGDETSAT) | 0 < pd < 254 (255=disabled)
Raw data slicer BW selection: bwsel = (SFR_%Page%_EXTSLC.ESLCBW)
Raw data slicer BW selection scaling: bwscal = (SFR_%Page%_EXTSLC.ESLCSCA)
=
Explorer version <= B12.6.33 used
Application Note
8
instead of
Released, 3/11/2011
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Register Value Calculations
Wizard Page 5 – Digital Receiving Unit
Application Note
9
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Register Value Calculations
Wizard Page 5 – Digital Receiving Unit
2.1
Datarate Calculation for TDA5240/35
Note: Use the calculation declared in section 2.2 if (SFR_%Page%_CHCFG.EXTPROC) = 2 (taken from Wizard
page 1 – Master Control Unit)
Input variables and constants:
Samples per chip: samplesPerChip := 8
Pure FSK (modtype=1):
Application Note
10
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Register Value Calculations
Wizard Page 5 – Digital Receiving Unit
Pure ASK (modtype=0):
Mixed Mode (modtype>1):
Application Note
11
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Register Value Calculations
Wizard Page 5 – Digital Receiving Unit
2.2
Datarate Calculation for TDA5225
Note: Use the calculation declared here if (SFR_%Page%_CHCFG.EXTPROC) = 2 (taken from Wizard page 1
– Master Control Unit)
Input variables and constants:
Samples per chip: samplesPerChip = 16
Pure FSK (modtype=1) and datarate*cpb < 1000:
0
Pure FSK (modtype=1) and datarate*cpb >= 1000:
1
Application Note
12
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Register Value Calculations
Wizard Page 5 – Digital Receiving Unit
Pure FSK (modtype=1, use intermediate variable from datarate-depended formulas above):
Pure ASK (modtype=0):
Application Note
13
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Register Value Calculations
Wizard Page 5 – Digital Receiving Unit
Mixed Mode (modtype>1):
2.3
Modifications for Jitter optimized Datarate Calculation
This feature is available for Explorer version equal or greater than B12.6.45.
These values are affected by activation (option at Wizard Page 1) of the jitter optimized datarate calculation:
Input variables and constants:
Datarate oversampling factor: drOversampling
Datarate: datarate [bit/s] := datarate * drOversampling (the datarate input is multiplied by the
oversampling factor
Samples per chip: samplesPerChip := 8 (also for TDA5225)
Application Note
14
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Register Value Calculations
Wizard Page 6 – Clock Data Recovery
Wizard Page 6 – Clock Data Recovery
3
Input variables and constants:
Equal bits of pattern A: eqbitsA := number of equal chips within the TSI pattern A, beginning from the
least significant bit of the register (SFR_%Page%_TSIPTA0), divided by two
Maximum length of code violation within datapacket: cv [bit] | min=1 < max=11
TSI mode: tsimode = (SFR_%Page%_TSIMODE.TSIDETMOD)
Output variables and registers allocation:
Timing Violation Window Length: tv = SFR_%Page%_TVWIN.TVWIN
Wizard Page 7 – Frame Synchronization Unit
4
Input variables and constants:
Equal bits of pattern A: eqbitsA := number of equal chips within the TSI pattern A, beginning from the
least significant bit of the register (SFR_%Page%_TSIPTA0), divided by two
Gap time between TSIA+TSIB: gaptime [bit] | min=0 < max=15.5
TSI Gap resync mode: tsiresync = (SFR_%Page%_TSIMODE.TSIGRSYN)
Output variables and registers allocation:
Gap time T2: tsigapt2 = (SFR_%Page%_TSIGAP.TSIGAP)
Gap time T16: tsigap16 = (SFR_%Page%_TSIGAP.GAPVAL)
Wizard Page 9 – Polling Timer Unit
5
Input variables and constants:
System frequency;
Time base: trt [ms]
Wake-Up level observation time: wulot_time [ms]
Timeout SYNC: timeout_sync [ms]
Timeout TSI: timeout_tsi [ms]
Timeout EOM: timeout _eom [ms]
On time (Config. %Page%): ontimex [ms]
Off time: offtime [ms]
Runin length: runlen = (SFR_%Page%_CDRRI.RUNLEN)
Application Note
15
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Register Value Calculations
Wizard Page 9 – Polling Timer Unit
Datarate: datarate [bit/s] (taken from Wizard page 5 – Digital Receiving Unit)
Output variables and registers allocation:
Startup time;
Channel hop time:
Self polling mode reference timer: spmrt = (SFR_SPMRT) | min=1 < 255 < max=0
Wake-Up Level Observation Time: wulot = (SFR_%Page%_WULOT.WULOT) | min=1 < 31 <
max=32(=regval=0)
Wake-Up Level Observation Time PreScaler: wulotps = (SFR_%Page%_WULOT.WULOTPS)
Timeout SYNC: totim_sync = (SFR_%Page%_TOTIM_SYNC) | min=1 < max=255
Timeout TSI: totim_sync = (SFR_%Page%_TOTIM_TSI) | min=1 < max=255
Timeout EOM: totim_sync = (SFR_%Page%_TOTIM_EOM) | min=1 < max=255
On time (Config. %Page%): spmontx = (SFR_SPMONT%Page%1,SFR_SPMONT%Page%0) | min=1 <
16383 < max=16384(=regval=0)
Off time: spmofft = (SFR_SPMOFFT1,SFR_SPMOFFT0) | min=1 < 16383 < max=16384(=regval=0)
Sync Search Timeout: sysrcto = (SFR_%Page%_SYSRCTO) | min=0 < max=255
Explorer version <= B12.6.33 used
Application Note
instead of
16
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Register Value Calculations
Wizard Page 10 – AFC AGC
Wizard Page 10 – AFC AGC
6
Input variables and constants:
System frequency;
Datarate: datarate [bit/s] (taken from Wizard page 5 – Digital Receiving Unit)
Chip per bit selection: cpb := 1 if one chip per bit is selected, 2 if two chip per bit is selected (taken from
Wizard page 5 – Digital Receiving Unit)
Settling time; st
RF channel frequency for channel ch: rf(ch) [MHz]; ch
RXRF Receive Side Band Select: sbsel = (SFR_%Page%_IF1.SSBSEL)
AFC Limit: afclim = (SFR_%Page%_AFCLIMIT.AFCLIMIT)
{ultra_fast, fast, normal, slow, very_slow}
Channels; Channels = {1, 2, 3}
Intermediate variables:
Single/Double conversion frequency: conv [MHz] (taken from section 1 - Wizard Page 2 – RF PLL)
Output variables and registers allocation:
Integrator 1 Gain Coefficient; coeff1 = (SFR_%Page%_AFCK1CFG1,SFR_%Page%_AFCK1CFG0)
Integrator 2 Gain Coefficient: coeff2 = (SFR_%Page%_AFCK2CFG1,SFR_%Page%_AFCK2CFG0)
Warning message “For a proper function of AFC it is recommended to change the LO injection side or
to use a smaller AFC limit value.”: warning :=
Explorer version <= B12.6.33 used
Application Note
instead of
17
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Register Value Calculations
Wizard Page 10 – AFC AGC
Application Note
18
Released, 3/11/2011
w w w . i n f i n e o n . c o m
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