TDA5225

Dat a Sh ee t, V1.0 , F eb rua ry 2 01 0
S m a r t L E W I S TM R X +
TDA5225
En hanced Sensitivity M ulti-Cha nnel
Qua d-C onfi gu rati on R ec ei ve r
w ith Di gita l Sl icer
Wi re less Co ntro l
N e v e r
s t o p
t h i n k i n g .
Edition February 19, 2010
Published by Infineon Technologies AG,
Am Campeon 1 - 12
85579 Neubiberg, Germany
© Infineon Technologies AG February 19, 2010.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or the Infineon Technologies Companies and our Infineon Technologies
Representatives worldwide (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Dat a Sh ee t, V1.0 , F eb rua ry 2 01 0
S m a r t L E W I S TM R X +
TDA5225
En hanced Sensitivity M ulti-Cha nnel
Qua d-C onfi gu rati on R ec ei ve r
w ith Di gita l Sl icer
Wi re less Co ntro l
N e v e r
s t o p
t h i n k i n g .
TDA5225
Revision Number:
Revision History:
010
2010-02-19
Previous Version:
TDA5225_v0.2
V1.0
Page
Subjects (major changes since last revision)
Page 26
Update of Figure 9
Page 28
Update of Figure 10
Page 30
AFC limitation added
Page 32
AGC setting proposal added
Page 33
New Section 2.4.6.5 ADC added
Page 34
Additional information on RSSIPRX register inserted
Page 40
Update of Figure 19
Page 41
Update of Figure 20
Page 45
Additional hint on clock and data recovery algorithm of the user
software inserted
Page 49
Limitation for ISx readout and Burst-read function added
Page 51
Limitation for Burst-read function added
Page 77
Additional hints added
Page 79
Adaption of Section 4.1
Page 82
Page 90 f
New item C7 added
Comments added for items I6, I7, I8, I9, J11, J12
Page 90
Item J1 updated
Page 95
BOM components C7, C8, L1, R2 and R3 updated
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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TDA5225
Table of Contents
Page
1
1.1
1.2
1.3
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.6
2.4.6.1
2.4.6.2
2.4.6.3
2.4.6.4
2.4.6.5
2.4.7
2.4.8
2.4.8.1
2.4.8.2
2.4.9
2.4.9.1
2.4.9.2
2.5
2.5.1
2.5.1.1
2.5.1.2
2.5.2
2.5.3
2.5.4
2.5.4.1
2.5.5
2.6
2.6.1
2.6.1.1
2.6.1.2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Definition and Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RF/IF Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Crystal Oscillator and Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sigma-Delta Fractional-N PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PLL Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Digital Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ASK and FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ASK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Automatic Frequency Control Unit (AFC) . . . . . . . . . . . . . . . . . . . . . 27
Digital Automatic Gain Control Unit (AGC) . . . . . . . . . . . . . . . . . . . . 29
Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RSSI Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Digital Baseband (DBB) Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Wake-Up Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power Supply Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Chip Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interfacing to the TDA5225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Digital Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interrupt Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Digital Control (4-wire SPI Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chip Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
System Management Unit (SMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Master Control Unit (MCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Run Mode Slave (RMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Data Sheet
5
7
7
8
8
V1.0, 2010-02-19
TDA5225
Table of Contents
Page
2.6.1.3
2.6.1.4
2.6.1.5
2.6.1.6
2.6.1.7
2.6.1.8
2.6.2
2.6.2.1
2.6.2.2
2.6.2.3
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.8.1
2.8.2
HOLD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Polling Mode (SPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Modulation Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Channel in Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Mode Self Polling (RMSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polling Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Constant On-Off Time (COO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Idle Period Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Bit Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Manchester Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Power Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Symbols of SFR Registers and Control Bits . . . . . . . . . . . . . . . . . . . . .
Digital Control (SFR Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFR Address Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFR Register List and Detailed SFR Description . . . . . . . . . . . . . . . . .
59
60
60
64
64
64
67
68
68
71
72
72
72
75
75
76
76
76
3
3.1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4
4.1
4.1.1
4.1.2
4.1.3
4.2
4.3
4.4
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Test Circuit - Evaluation Board v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Test Board Layout - Evaluation Board v1.0 . . . . . . . . . . . . . . . . . . . . . . . . 99
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Appendix - Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Data Sheet
6
V1.0, 2010-02-19
TDA5225
Product Description
1
Product Description
1.1
Overview
The IC is a low power ASK/FSK Receiver for the frequency bands 300-320, 425-450,
863-870 and 902-928 MHz.
The chip offers a very high level of integration and needs only a few external
components.
The device is qualified to automotive quality standards and operates between -40 and
+105°C at supply voltage ranges of 3.0-3.6 Volts or 4.5-5.5 Volts.
The receiver is realized as a double down conversion super-heterodyne/low-IF
architecture each with image rejection. A fully integrated Sigma-Delta Fractional-N PLL
Synthesizer allows for high-resolution frequency generation and uses a crystal oscillator
as the reference. The on-chip temperature sensor may be utilized for temperature drift
compensation via the crystal oscillator.
The high performance down converter is the key element for the exceptional sensitivity
performance of the device which take it close to the theoretical top-performance limits.
It demodulates the received ASK or FSK data stream independently which can then be
accessed via separate pins. The RSSI output signal is converted to the digital domain
with an ADC. All these signals are accessible via the 4-wire SPI interface bus. Up to 4
pre-configured telegram parameters can be stored into the device offering independent
pre-processing of the received data to an extent not available till now. The down
converter can be also configured in single-conversion mode at moderately reduced
selectivity performance but at the advantage of omitting the IF ceramic filter.
Data Sheet
7
V1.0, 2010-02-19
TDA5225
Product Description
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Enhanced sensitivity receiver
Multi-band/Multi-Channel (300-320, 425-450, 863-870 and 902-928 MHz)
One crystal frequency for all supported frequency bands
21-bit Sigma-Delta Fractional-N PLL synthesizer with high resolution of 10.5 Hz
Up to 4 parallel parameter sets for autonomous scanning and receiving from different
sources
Up to 12 different frequency channels are supported with 10.5 Hz resolution each
Ultrafast Wake-up on RSSI
Selectable IF filter bandwidth and optional external filters possible
Double down conversion image reject mixer
ASK and FSK capability
Automatic Frequency Control (AFC) for carrier frequency offset compensation
NRZ data processing capability
Sliced data output
RSSI peak detectors
Wake-up generator and polling timer unit
Unique 32-bit serial number
On-chip temperature sensor
Integrated timer usable for external watch unit
Integrated 4-wire SPI interface bus
Supply voltage range 3.0 Volts to 3.6 Volts or 4.5 Volts to 5.5 Volts
Operating temperature range -40 to +105°C
ESD protection +/- 2 kV on all pins
Package PG-TSSOP-28
1.3
•
•
•
•
•
•
•
Features
Applications
Remote keyless entry systems
Remote start applications
Tire pressure monitoring
Short range radio data transmission
Remote control units
Cordless alarm systems
Remote metering
Data Sheet
8
V1.0, 2010-02-19
TDA5225
Functional Description
2
Functional Description
2.1
Pin Configuration
IFBUF_IN
1
28
IF _OUT
IFBUF_OUT
2
27
VDDA
GNDA
3
26
RSSI
IFMIX _INP
4
25
PP3
IFMIX _INN
5
24
GNDRF
VDD5V
6
23
LNA_INP
VDDD
7
22
LNA_INN
VDDD1V5
8
21
T2
GNDD
9
20
T1
PP0
10
19
SDO
PP1
11
18
SDI
PP2
12
17
SCK
P_ON
13
16
NCS
XTAL1
14
15
XTAL2
Figure 1
Data Sheet
TDA5225
Pin-out
9
V1.0, 2010-02-19
TDA5225
Functional Description
2.2
Pin Definition and Pin Functionality
Table 1
Pin Definition and Function
Pin Pad name
No.
1
Equivalent I/O Schematic
Function
IFBUF_IN
VDDA
Analog input
IF Buffer input
VDDA
330Ω
IFBUF
IFBUF_IN
Note: Input is
biased at VDDA/2
VDDA
330Ω
MIX2BUF
IFMIX_INN
2
IFBUF_OUT
Analog output
IF Buffer output
VDDA
VDDA
330Ω
IFBUF_OUT
IFBUF
GNDA
GNDA
3
GNDA
Analog ground
4
IFMIX_INP
Analog input
+ IF mixer input
VDDA
VDDA
330Ω
IFMIX_INP
MIX2BUF
Note: Input is
biased at VDDA/2
IFMIX_INN
5
IFMIX_INN
6
VDD5V
Data Sheet
see schematic of Pin 1 and 4
Analog input.
- IF mixer input
Analog input
5 Volt supply input
10
V1.0, 2010-02-19
TDA5225
Functional Description
Pin Pad name
No.
7
Equivalent I/O Schematic
Function
VDDD
VDD5V
Analog input
digital supply input
+
VReg
=
-
VDDD
GNDD
8
VDDD1V5
VDDD
Analog output
1.5 Volt voltage
regulator
+
VReg
=
-
VDD1V5
GNDD
9
GNDD
Digital ground
10 PP0
VDD5V
VDD5V
PPx
SDO
GNDD
Data Sheet
11
GNDD
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA and
DATA_MATCHFIL
are programmable
via a SFR (Special
Function Register),
default = CLK_OUT
V1.0, 2010-02-19
TDA5225
Functional Description
Pin Pad name
No.
Equivalent I/O Schematic
Function
11 PP1
see schematic of Pin 10
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA and
DATA_MATCHFIL
are programmable
via a SFR,
default = DATA
12 PP2
see schematic of Pin 10
Digital output
CLK_OUT,
RX_RUN,
NINT, LOW, HIGH,
DATA and
DATA_MATCHFIL
are programmable
via a SFR,
default = NINT
13 P_ON
VDD5V
Digital input
power-on reset
VDDD
P_ON
NCS
SCK
SDI
GNDD
GNDD
14 XTAL1
VDDD
VDDD
Analog input
crystal oscillator
input
XTAL1
GNDD
....
GNDD
GNDD
Data Sheet
12
V1.0, 2010-02-19
TDA5225
Functional Description
Pin Pad name
No.
Equivalent I/O Schematic
Function
15 XTAL2
VDDD
Analog output
crystal oscillator
output
VDDD
XTAL2
....
GNDD
GNDD
GNDD
16 NCS
see schematic of Pin 13
Digital input
SPI enable
17 SCK
see schematic of Pin 13
Digital input
SPI clock
18 SDI
see schematic of Pin 13
Digital input
SPI data in
19 SDO
see schematic of Pin 10
Digital output
SPI data out
20 T1
Digital input,
connect to Digital
Ground
21 T2
Digital input,
connect to Digital
Ground
22 LNA_INN
Analog input
LNA - RF input
LNA_INN
GNDRF
23 LNA_INP
Analog input
LNA + RF input
LNA_INP
GNDRF
24 GNDRF
Data Sheet
RF analog ground
13
V1.0, 2010-02-19
TDA5225
Functional Description
Pin Pad name
No.
25 PP3
Equivalent I/O Schematic
Function
see schematic of Pin 10
Digital output
RX_RUN,
NINT, LOW, HIGH,
DATA and
DATA_MATCHFIL
are programmable
via a SFR,
default = RX_RUN
26 RSSI
VDDA
VDDA
Analog output
analog RSSI output/
analog test pin
ANA_TST
500Ω
RSSI
GNDA
GNDA
27 VDDA
VDD5V
Analog input
Analog supply
+
VReg
=
-
VDDA
GNDA
28 IF_OUT
VDDA
Analog output
IF output
VDDA
330Ω
IF_OUT
PPFBUF
GNDA
Data Sheet
GNDA
14
V1.0, 2010-02-19
Figure 2
Data Sheet
XTAL
21.948717
MHz
15
GNDD
(9)
XTAL2
(15)
XTAL1
(14)
PP3 (25)
[RX_RUN]
VDDA
(27)
Vreg
3V3
3.3V-Analog
VDD5V
(6)
XOSC
Vreg
3V3
1st LO-Q
ΣΔ PLL
1st LO-I
wide
narrow
VDDD
(7)
nd
3.3V Dig-I/O
5V Dig-O
Clock for
Digital Core
2nd LO-Q
2nd LO-I
T2
(21)
Reset
Generator
to
RX
PPF
2
Reset for
Digital Core
nd
IR-Mix2, 2 IF:
274.35897 kHz
1.5V Dig-Core
2 LO
Div 2
MIX2
BUF
VDDD1V5 P_ON T1
(8)
(13) (20)
Vreg
1V5
1s t IF = 10.7 MHz
2nd IF = 1st IF / 39
fcrystal = 2nd IF * 80
double/single
conversion (SDCSEL)
IFBUF
IFBUF_IN (1)
PPF
BUF
IFBUF_OUT (2)
GNDRF
(24)
LNA
GNDA (3)
PPF
IFMIX_INN (5)
LNA_INN
(22)
LNA_INP
(23)
IF_OUT (28)
IR-Mix, 1st IF:
10.7 MHz
IFMIX_INP (4)
matching
+
SAW
Antenna
10.7 MHz
narrow ( opt )
VDDD
AAF
LP
D
AFC
Digital
Demod
PP0
(10)
[CLK_OUT]
ADC
I/F
MUX
PP2
(12)
[NINT]
Interrupt
Generator
Peripheral Bus
PLL
Control I/F
Clock
Generator
to
PLL
A
ADC-MUX
RSSI
System
Management
RX
Control I/F
Temp.Sensor
BPF
select
BW
Limiter
RSSI
(26)
Slicer
NCS SCK SDI SDO
(16) (17) (18) (19)
SPI Interface
Serial
Number
Peak Detector
Data
Filter
PP1
(11)
[DATA]
TDA5225
2.3
(CERFSEL)
10.7 MHz
wide
TDA5225
Functional Description
Functional Block Diagram
TDA5225 Block Diagram1)
1) The function on each PPx port pin can be programmed via SFR (see also Table 1). Default values are given
in squared brackets in Figure 2.
V1.0, 2010-02-19
TDA5225
Functional Description
2.4
Functional Block Description
2.4.1
Architecture Overview
A fully integrated Sigma-Delta Fractional-N PLL Synthesizer covers the frequency bands
300-320 MHz, 425-450 MHz, 863-870 MHz, 902-928 MHz with a high frequency
resolution, using only one VCO running at around 3.6 GHz. This makes the IC most
suitable for Multi-Band/Multi-Channel applications.
For Multi-Channel applications a very good channel separation is essential. To achieve
the necessary high sensitivity and selectivity a double down conversion superheterodyne architecture is used. The first IF frequency is located around 10.7 MHz and
the second IF frequency around 274 kHz. For both IF frequencies an adjustment-free
image frequency rejection feature is realized. In the second IF domain the filtering is
done with an on-chip third order bandpass polyphase filter. A multi-stage bandpass
limiter completes the RF/IF path of the receiver. For Single-Channel applications with
relaxed requirements to selectivity, a single down conversion low-IF scheme can be
selected.
For Multi-Channel systems where even higher channel separation is required, up to two
(switchable) external ceramic (CER) filters can be used to improve the selectivity.
An RSSI generator delivers a DC signal proportional to the applied input power and is
also used as an ASK demodulator. Via an anti-aliasing filter this signal feeds an ADC
with 10 bits resolution.
The harmonic suppressed limiter output signal feeds a digital FSK demodulator. This
block demodulates the FSK data and delivers an AFC signal which controls the divider
factor of the PLL synthesizer.
A digital receiver, which comprises RSSI peak detectors, a matched data filter and a data
slicer, decodes the received ASK or FSK data stream. The received data signal is
accessible via one of the port pins.
The crystal oscillator serves as the reference frequency for the PLL phase detector, the
clock signal of the Sigma-Delta modulator and divided by two as the 2nd local oscillator
signal. To accelerate the start up time of the crystal oscillator two modes are selectable:
a Low Power Mode (with lower precision) and a High Precision Mode.
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
2.4.2
Block Overview
The TDA5225 is separated into the following main blocks:
•
•
•
•
•
•
•
•
•
RF / IF Receiver
Crystal Oscillator and Clock Divider
Sigma-Delta Fractional-N PLL Synthesizer
ASK / FSK Demodulator incl. AFC, AGC and ADC
RSSI Peak Detector
Digital Baseband Receiver
Power Supply Circuitry
System Interface
System Management Unit
2.4.3
RF/IF Receiver
The receiver path uses a double down conversion super-heterodyne/low-IF architecture,
where the first IF frequency is located around 10.7 MHz and the second IF frequency
around 274 kHz. For the first IF frequency an adjustment-free image frequency rejection
is realized by means of two low-side injected I/Q-mixers followed by a second order
passive polyphase filter centered at 10.7 MHz (PPF). The I/Q-oscillator signals for the
first down conversion are delivered from the PLL synthesizer. The frequency selection
in the first IF domain is done by an external CER filter (optionally by two, decoupled by
a buffer amplifier). For moderate or low cost applications, this ceramic filter can be
substituted by a simple LC Pi-filter or completely by-passed using the receiver as a
single down conversion low-IF scheme with 274 kHz IF frequency. The down conversion
to the second IF frequency is done by means of two high-side injected I/Q-mixers
together with an on-chip third order bandpass polyphase filter (PPF2 + BPF). The I/Qoscillator signals for the second down conversion are directly derived by division of two
from the crystal oscillator frequency. The bandwidth of the bandpass filter (BPF) can be
selected from 50 kHz to 300 kHz in 5 steps. For a frequency offset of -150 kHz to -120
kHz, the AFC (Automatic Frequency Control) function is mandatory. Activated AFC
option might require a longer preamble sequence in the receive data stream.
The receiver enable signal (RX_RUN) can be offered at each of the port pins to control
external components. Whenever the receiver is active, the RX_RUN output signal is
active. Active high or active low is configurable via PPCFG2 register.
Data Sheet
17
V1.0, 2010-02-19
TDA5225
Functional Description
The frequency relations are calculated with the following formulas:
f IF1 = 10.7MHz
f IF1
f IF2 = --------39
f crystal = f IF2 × 80
f crystal
f LO2 = ---------------2
f LO1 = f crystal × NF divider
Lim ite r
QMix2
3rd order BP /PP F2
IF2 = 274 kH z
IF
Attenuation
adjust
IMix2
SDCSEL-MUX
MIX2BUF
(var. gain)
CERFilter IF1
10.7 MHz
optional
CERFSEL-MUX
Q-Mix
CERFilter
IF1
10 .7 MHz
IFBUF
LNA
PPFBUF
MUX
RX
Input
2nd order PPF
10.7 MHz
I-Mix
RSSI Generator
LP
harm sup
digital
FSK Demod
LP
alias sup
ASK /
RSSI
ADC
RX
FSK Data
RX
ASK Data
Divider
:N
IQ :2
Channel Filter
Bandwidth select
N
AFC
Filter
ΣΔ Modulator
Channel select
VCO
:1/:2/:3
IQ Divider : 4
Multi Modulos
Divider : N_FN
PD
Crystal
oscil lator
Band select
Channel select
LF select
Channel Filter select
Band select
Loop
Filter
Front end
control unit
IF Attenuation adjust
RSSI Gain/ Offset adjust
LF select
Figure 3
Block Diagram RF Section
The front end of the receiver comprises an LNA, an image reject mixer and a digitally
gain controlled buffer amplifier. This buffer amplifier allows the production spread of the
on-chip signal strip, of external matching circuitry and RF SAW and ceramic IF filters to
be trimmed. The second image reject mixer down converts the first IF to the second IF.
Data Sheet
18
V1.0, 2010-02-19
TDA5225
Functional Description
The bandpass filter follows the subsequent formula:
f center =
f corner, low × f corner, high
Therefore asymmetric corner frequencies can be observed. The use of AFC results in
more symmetry.
A multi-stage bandpass limiter at a center frequency of 274 kHz completes the receiver
chain. The -3dB corner frequencies of the bandpass limiter are typically at 75 kHz and
at 520 kHz.
An RSSI generator delivers a DC signal proportional to the applied input power and is
also used as an ASK demodulator. Via a programmable anti-aliasing filter this signal is
converted to the digital domain by means of a 10-bit ADC.
The limiter output signal is connected to a digital FSK demodulator.
The immunity against strong interference frequencies (so called blockers) is determined
by the available filter bandwidth, the filter order and the 3rd order intercept point of the
front end stages. For Single-Channel applications with moderate requirements to the
selectivity the performance of the on-chip 3rd order bandpass polyphase filter might be
sufficient. In this case no external filters are necessary and a single down conversion
architecture can be used, which converts the input signal frequency directly to the 2nd IF
frequency of 274 kHz.
IF
Attenuation
adjust
RSSI Generator
LP
harm sup
LP
alias sup
RX
FSK Data
digital
FSK Demod
ASK /
RSSI
ADC
RX
ASK Data
Divider
:N
Channel Filter
Bandwidth select
1st LO
Figure 4
L im ite r
QMix2
3 rd o rd e r B P /P P F 2
I F2 = 2 7 4 k H z
IMix2
S D C S E L -M U X
Q-Mix
M IX 2 B U F
( va r. g a i n )
C E RF S E L - M UX
IFB U F
LNA
PPF BU F
MUX
RX
Input
2nd order PPF
1 0 .7 M H z
I-Mix
2nd LO
Single Down Conversion (SDC, no external filters required)
For Multi-Channel applications or systems which demand higher selectivity the double
down conversion scheme together with one or two external CER filters can be selected.
The order of such ceramic filters is in a range of 3, so the selectivity is further improved
and a better channel separation is guaranteed.
Data Sheet
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TDA5225
Functional Description
IF
Attenuation
adjust
RSSI Generator
LP
harm sup
LP
alias sup
RX
FSK Data
digital
FSK Demod
ASK /
RSSI
ADC
RX
ASK Data
Divider
:N
Channel Filter
Bandwidth select
1st LO
Figure 5
L im ite r
QMix2
3 r d o r d e r B P /P P F 2
IF2 = 2 7 4 k H z
IMix2
S D C S E L -M U X
Q-Mix
M IX 2 B U F
( va r. g a in )
C E RF S E L-M UX
CERFilter
IF1
10.7 MHz
IFB U F
LNA
PPFBUF
MUX
RX
Input
2 nd ord er P P F
1 0 .7 M H z
I-Mix
2nd LO
Double Down Conversion (DDC) with one external filter
For applications which demand very high selectivity and/or channel separation even two
CER filters may be used. Also in applications where one channel requires a wider
bandwidth than the other (e.g. TPMS and RKE) the second filter can be by-passed.
IF
Attenuation
adjust
Data Sheet
RSSI Generator
LP
harm sup
LP
alias sup
RX
FSK Data
digital
FSK Demod
ASK /
RSSI
ADC
RX
ASK Data
Divider
:N
Channel Filter
Bandwidth select
1st LO
Figure 6
L im ite r
QMix2
3 rd o rde r B P /P P F2
I F2 = 2 7 4 k H z
IMix2
S D C S E L -M U X
M IX 2 B U F
( va r. g a in )
CERFilter IF1
10.7 MHz
optional
C E RF S E L -M UX
Q-Mix
CERFilter
IF1
10.7 MHz
IFB U F
LNA
PPF BU F
MUX
RX
Input
2nd order PPF
1 0 .7 M H z
I-Mix
2nd LO
Double Down Conversion (DDC) with two external filters
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TDA5225
Functional Description
2.4.4
Crystal Oscillator and Clock Divider
The crystal oscillator is a Pierce type oscillator which operates together with the crystal
in parallel resonance mode. An automatic amplitude regulation circuitry allows the
oscillator to operate with minimum current consumption. In SLEEP Mode, where the
current consumption should be as low as possible, the load capacitor must be small and
the frequency is slightly detuned, therefore all internal trim capacitors are disconnected.
The internal capacitors are controlled by the crystal oscillator calibration registers
XTALCALx. With a binary weighted capacitor array the necessary load capacitor can be
selected.
Whenever a XTALCALx register value is updated, the selected trim capacitors are
automatically connected to the crystal so that the frequency is precise at the desired
value. The SFR control bit XTALHPMS can be used to activate the High Precision Mode
also during SLEEP Mode.
fsys
9
Setting
automatically
controlled
( ≤ 1pF steps )
XTALCAL0
XTALCAL1
Oscillator -Core
XTAL1
Figure 7
Data Sheet
Binary weighted
Capacitor-Array
Binary weighted
Capacitor-Array
(DGND)
XTALHPMS
XTAL2
Crystal Oscillator
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TDA5225
Functional Description
Recommended Trimming Procedure
• Set the registers XTALCAL0 and XTALCAL1 to the expected nominal values
• Set the TDA5225 to Run Mode Slave
• Wait for 0.5ms minimum
• Trim the oscillator by increasing and decreasing the values of XTALCAL0/1
• Register changes larger than 1 pF are automatically handled by the TDA5225 in 1 pF
steps
• After the Oscillator is trimmed, the TDA5225 can be set to SLEEP mode and keeps
these values during SLEEP mode
• Add the settings of XTALCAL0/1 to the configuration. It must be set after every power
up or brownout!
Using the High Precision Mode
As discussed earlier, the TDA5225 allows the crystal oscillator to be trimmed by the use
of internal trim capacitors. It is also possible to use the trim functionality to compensate
temperature drift of crystals.
During Run Mode (always when the receiver is active) the capacitors are automatically
connected and the oscillator is working in the High Precision Mode.
On entering SLEEP Mode, the capacitors are automatically disconnected to save
power.
If the High Precision Mode is also required for SLEEP Mode, the automatic disconnection of trim capacitors can be avoided by setting XTALHPMS to 1 (enable XTAL High
Precision Mode during SLEEP Mode).
External Clock Generation Unit
A built in programmable frequency divider can be used to generate an external clock
source out of the crystal reference. The 20 bit wide division factor is stored in the
registers CLKOUT0, CLKOUT1 and CLKOUT2. The minimum value of the
programmable frequency divider is 2. This programmable divider is followed by an
additional divider by 2, which generates a 50% duty cycle of the CLK_OUT signal. So
the maximum frequency at the CLK_OUT signal is the crystal frequency divided by 4.
The minimum CLK_OUT frequency is the crystal frequency divided by 221.
To save power, this programmable clock signal can be disabled by the SFR control bit
CLKOUTEN. In this case the external clock signal is set to low.
Data Sheet
22
V1.0, 2010-02-19
TDA5225
Functional Description
The resulting CLK_OUT frequency can be calculated by:
CLKOUTEN
CLKOUT2
CLKOUT1
CLKOUT0
f sys
f CLKOUT = --------------------------------------------2 ⋅ divisionfactor
Enable
fsys
Enable
2 x f C LK_OU T
20 Bit Counter
Figure 8
Divide
by 2
fC LK _OU T
External Clock Generation Unit
The maximum CLK_OUT frequency is limited by the driver capability of the PPx pin and
depends on the external load connected to this pin. Please be aware that large loads
and/or high clock frequencies at this pin may interfere with the receiver and reduce
performance.
After Reset the PPx pin is activated and the division factor is initialized to 11 (equals
fCLK_OUT = 998 kHz).
A clock output frequency higher than 1 MHz is not supported.
For high sensitivity applications, the use of the external clock generation unit is not
recommended.
Data Sheet
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TDA5225
Functional Description
2.4.5
Sigma-Delta Fractional-N PLL Block
The Sigma-Delta Fractional-N PLL is fully integrated on chip. The Voltage Controlled
Oscillator (VCO) with on-chip LC-tank runs at approximately 3.6 GHz and is first divided
with a band select divider by 1, 2 or 3 and then with an I/Q-divider by 4 which provides
an orthogonal local oscillator signal for the first image reject mixer with the necessary
high accuracy.
The multi-modulus divider determines the channel selection and is controlled by a
3rd order Sigma-Delta Modulator (SDM). A type IV phase detector, a charge pump with
programmable current and an on-chip loop filter closes the phase locked loop.
To 1 st mixer
3.6 GHz VCO Loop Filter
IQ Divider
÷4
Band Select
÷1/÷2/÷3
Multimodulus
Divider
Channel FN
CP
PFD
ΣΔ Modulator
QOSC
22MHz
AFC filter
AFC-data
Figure 9
Data Sheet
Synthesizer Block Diagram
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TDA5225
Functional Description
When defining a Multi-Channel system, the correct selection of channel spacing
is extremely important. A general rule is not possible, but following must be considered:
• If an additional SAW filter is used, all channels including their tolerances have to be
inside the SAW filter bandwidth.
• The distance between channels must be high enough, that no overlapping can occur.
Strong input signals may still appear as recognizable input signal in the neighboring
channel because of the limited suppression of IF Filters. Example: a typical 330kHz IF
filter has at 10.3 MHz ( 10.7 MHz - 0.4 MHz ) only 30 dB suppression. A -70 dBm input
signal appears like a -100 dBm signal, which is inside the receiver sensitivity. In critical
cases the use of two IF filters must be considered. See also Chapter 2.4.3 RF/IF
Receiver.
2.4.5.1
PLL Dividers
The divider chain consists of a band select divider 1/2/3, an I/Q-divider by 4 which
provides an orthogonal 1st local oscillator signal for the first image reject mixer with the
necessary high accuracy and a multi-modulus divider controlled by the Sigma-Delta
Modulator. With the band select divider, the wanted frequency band is selected. Divide
by 1 selects the 915 MHz and 868 MHz band, divide by 2 selects the 434 MHz band and
divide by 3 selects the 315 MHz band. The ISM band selection is done via bit group
BANDSEL in x_PLLINTC1 register.
2.4.5.2
Digital Modulator
The 3rd order Sigma-Delta Modulator (SDM) has a 22 bit wide input word, however the
LSB is always high, and is clocked by the XTAL oscillator. This determines the
achievable frequency resolution.
The Automatic Frequency Control Unit filters the actual frequency offset from the FSK
demodulator data and calculates the necessary correction of the divider factor to achieve
the nominal IF center frequency.
Data Sheet
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TDA5225
Functional Description
2.4.6
ASK and FSK Demodulator
B = 50..300kHz
channel filter FM limiter
image suppression /
band limitation (noise)
FSK
PPF2
BP
2nd
conversion
33 / 46 / 65 / 93 / 132 /
190 / 239 / 282 kHz
(2sided PDF BW)
RSSI
FSK
demodulator
FSK
demodulator
AFC track/freeze
AFC
loop filter
RF PLL ctrl
FSK/ASK
Rate adapter
Demodulated
Data
Bypass
Rate doubler
Decimation
8 … 16 samples /chip
(data rate dependent )
Temp
VDDD/2
Mux
ADC
RSSI Slope
RSSI Offset
Dig. Gain
Control
Peak Memory
Filter
delog
ASK
buffer
Div
fSystem
RSSI
AGC
RSSI Peak
Detector
register
RSSIPMF
register
RSSIPWU
(internal
signal)
Begin of config /
channel ,
x*WULOT
Figure 10
Analog Gain Control
RSSIPWU
register
End of config/
channel
>
WU event
TH, BL, BH
Functional Block Diagram ASK/FSK Demodulator
The IC comprises two separate demodulators for ASK and FSK.
After combining FSK and ASK data path, a sampling rate adaptation follows to meet an
output oversampling between 8 and 16 samples per chip. Finally, an oversampling of 8
samples per chip can be achieved using a fractional sample rate converter (SRC) with
linear interpolation (for further details see Figure 15).
2.4.6.1
ASK Demodulator
The RSSI generator delivers a DC signal proportional to the applied input power at a
logarithmic scale (dBm) and is also used as an ASK demodulator. Via a programmable
anti-aliasing filter this signal is converted to the digital domain by means of a 10-bit ADC.
For the AM demodulation a signal proportional to the linear power is required. Therefore
a conversion from logarithmic scale to linear scale is necessary. This is done in the digital
domain by a nonlinear filter together with an exponential function. The analog RSSI
signal after the anti-aliasing filter is available at the RSSI pin via a buffer amplifier. To
enable this buffer the SFR control bit RSSIMONEN must be set. The anti-aliasing filter
can be by-passed for visualization on the RSSI pin (see AAFBYP control bit).
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
2.4.6.2
FSK Demodulator
The limiter output signal, which has a constant amplitude over a wide range of the input
signal, feeds the FSK demodulator. There is a configurable lowpass filter in front of the
FSK demodulation to suppress the down conversion image and noise/limiter harmonics
(FSK Pre-Demodulation Filter, PDF). This is realized as a 3rd order digital filter. The
sampling rate after FSK demodulation is fixed and independent from the target data rate.
2.4.6.3
Automatic Frequency Control Unit (AFC)
In front of the image suppression filter a second FSK demodulator is used to derive the
control signal for the Automatic Frequency Control Unit, which is actually the DC
value of the FSK demodulated signal. This makes the AFC loop independent from signal
path filtering and allow so a wider frequency capture range of the AFC. The derivation of
the AFC control signal is preferably done during the DC free preamble and is then frozen
for the rest of the datagram.
Since the digital FSK demodulator determines the exact frequency offset between the
received input frequency and the programmed input center frequency of the receiver,
this offset can be corrected through the sigma delta control of the PLL. As shown in
Figure 10, for AFC purposes a parallel demodulation path is implemented. This path
does not contain the digital low pass filter (PDF, Pre-Demodulation Filter). The entire IF
bandwidth, filtered by the analog bandpass filter only, is processed by the AFC
demodulator.
There are two options for the active time of the AFC loop:
•
•
1. always on
2. active for a programmable time relative to a signal identification event
In the latter case the AFC can either be started or frozen relative to the signal
identification. After the active time the offset for the sigma-delta PLL (SD PLL) is frozen.
The programming of the active time is especially necessary in case the expected frame
structure contains a gap (noise) between wake-up and payload in order to avoid the AFC
from drifting.
AFC works both for FSK and ASK. In the latter case the AFC loop only regulates during
ASK data = high.
The maximum frequency offset generated by the AFC can be limited by means of the
x_AFCLIMIT register. This limit can be used to avoid the AFC from drifting in the
presence of interferers or when no RF input signal is available (AFC wander). A
maximum AFC limit of 42 kHz is recommended. AFC wandering needs to be kept in mind
especially when using Run Mode Slave.
Data Sheet
27
V1.0, 2010-02-19
TDA5225
Functional Description
K1 = integrator1 gain
x_AFCLIMIT
x_AFCK1CFG0/1
integrator 1
K1
x16
limit
+
AFC Demod out
integrator 2
hold
K2
x4
limit
SDPLL
scaling &
limiting
FreqOffset
HOLD
hold
Freeze* / Track
Delay
x_AFCK2CFG0/1
x_AFCAGCD
K2 = integrator 2 gain
Figure 11
AFC Loop Filter (I-PI Filtering and Mapping)
The bandwidth (and thus settling time) of the loop is programmed by means of the
integrator gain coefficients K1 and K2 (x_AFCK1CFG and x_AFCK2CFG register).
K1 mainly determines the bandwidth. K2 influences the dynamics/damping (overshoot)
- smaller K2 means smaller overshoot, but slower dynamics. The bandwidth of the AFC
loop is approximately 1.3*K1.
To avoid residual FM, limiting the AFC BW to 1/20 ~ 1/40 of the bit rate is suggested,
therefore K1 must be set to approximately 1/50 ~ 1/100 of the bit rate. For most
applications K2 can be set equal to K1 (overshoot is then <25%).
When very fast settling is necessary K1 and K2 can be increased up to bit rate/10,
however, in this case approximately 1dB sensitivity loss is to be expected due to the AFC
counteracting the input FSK signal.
AFC limitation at Local Oscillator (LO) frequencies at multiples of reference frequency
(f_xtal). When AFC is activated and AFC drives the wanted LO frequency over the
integer limit of Sigma Delta (SD) modulator, the SD modulator stucks at frac=1.0 or
frac=0.0 due to saturation. So when AFC can change the integer value for the LO
(register x_PLLINTCy) within the frequency range LO-frequency +/- AFC-limit, a change
of the LO injection side or a smaller AFC-limit is recommended.
The frequency offset found by AFC (AFC loop filter output) can be readout via register
AFCOFFSET, when AFC is activated. The value is in signed representation and has a
frequency resolution of 2.68 kHz/digit. The output can be limited by the x_AFCLIMIT
register.
Data Sheet
28
V1.0, 2010-02-19
TDA5225
Functional Description
2.4.6.4
Digital Automatic Gain Control Unit (AGC)
Automatic Gain Control (AGC) is necessary mainly because of the limited dynamic range
of the on-chip bandpass filter (BPF). The dynamic range reduces to less than 60dB in
case of minimum BPF bandwidth.
AGC is used to cover the following cases:
1. ASK demodulation at large input signals
2. RSSI reading at large input signals
3. Improve IIP3 performance in either FSK or ASK mode
The 1st IF buffer (PPFBUF, see Figure 3) can be fine tuned "manually" by means of 4
bits thus optimizing the overall gain to the application (attenuation of 0dB to -12dB by
means of IFATT0 to IFATT15 in DDC mode; SDC mode has lower IFATT range). This
buffer allows the production spread of external components to be trimmed.
The gain of the 2nd IF path is set to three different values by means of an AGC algorithm.
Depending on whether the receiver is used in single down conversion or in double down
conversion mode the gain control in the 2nd IF path is either after the 2nd poly-phase
network or in front of the 2nd mixer.
The AGC action is illustrated in the RSSI curve below:
Analog (blue) &
digital (black )
RSSI output
Mixer2
saturation
BPF bypassed
AGC OFF
Max. B W
BPF
saturation
AGC ON
Min. B W
margin
Analog AGC
attack point
hysteresis
Analog AGC
decay point
Max. B W
Front- end
noise x gain
Max . FE gain
(IFA TT 0)
Min. B W
Min. FE gain
(IFA TT 15)
AGCTUP
Data Sheet
AGCTLO
AGCTHOFFS
Figure 12
AGCHYS
AGCHYS
Limiter
noise floor
Input power
Analog RSSI output curve with AGC action ON (blue) vs. OFF (black)
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TDA5225
Functional Description
Digital RSSI, AGC and Delog:
In order to match the analog RSSI signal to the digital RSSI output a correction is
necessary. It adds an offset (RSSIOFFS) and modifies the slope (RSSISLOPE) such
that standardized AGC levels and an appropriate DELOG table can be applied.
Upon entering the AGC unit the digital RSSI signal is passed through a Peak Memory
Filter (PMF). This filter has programmable up and down integration time constants
(PMFUP, PMFDN) to set attack respectively decay time. The integration time for decay
time must be significantly longer than the attack time in order to avoid the AGC interfering
with the ASK modulation.
The integrator is followed by two digital Schmitt triggers with programmable thresholds
(AGCTLO; AGCTUP) - one Schmitt trigger for each of the two attack thresholds (two
digital AGC switching points). The hysteresis of the Schmitt triggers is programmable
(AGCHYS) and sets the decay threshold. The Schmitt triggers control both the analog
gain as well as the corresponding (programmable) digital gain correction (DGC).
The difference ("error") signal in the PMF is actually a normalized version of the
modulation. This signal is then used as input for the DELOG table.
AGC threshold programming
The SFR description for the AGC thresholds are in dBs. The first value to set is the AGC
threshold offset in AGCTHOFFS.
This value is the offset relative to 0 input (no noise, no signal), which for the default
setting of gain, and assuming typical insertion loss of matching network and ceramic
filter, can be extrapolated to be approximately -143dBm.
In this case the default setting of the AGCTHOFFS of 63.9dB corresponds to an input
power of approximately -79dBm (= -143dBm + 63.9dB).
The low (digital) AGC threshold is then -79 + 12.8dB (default AGCTLO) = -66dBm and
the upper (digital) AGC threshold is -79 + 25.6 (default AGCTUP) = -53dBm.
Therefore a margin of about 6dB is indicated before a degradation of the linearity of the
2nd IF can be observed when using the 50kHz BPF or even about 16dB when using the
300kHz BPF.
The input power level at which the AGC switches back to maximum gain is -66dBm 21.3dB (default AGCHYS) = -87dBm. This provides enough margin against the minimum
sensitivity.
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
When AGC is activated, RSSI is untrimmed, IFATT <= 5.6dB and the same RSSI offset
should be applied for all bandpass filter settings, then the settings in Table 2 can be
applied, where a small reduction of the RSSI input range can be observed.
Table 2
AGC Settings 1
AGC Threshold Hysteresis = 21.3 dB
AGC Digital RSSI Gain Correction = 15.5 dB
AGC
AGC
AGC
Threshold Threshold Threshold
Offset
Low
Up
BPF
RSSI Offset
Compensation
(untrimmed) 1)
300 kHz
32
63.9 dB
8
4
5 dB
200 kHz
32
63.9 dB
6
2
5 dB
125 kHz
32
63.9 dB
5
0
5 dB
80 kHz
32
51.1 dB
11
6
2.8 dB
50 kHz
32
51.1 dB
9
5
0 dB
RSSI Input
Range
Reduction
1) Note: This value needs to be used for calculating the register value
For the full RSSI input range, the values in Table 3 can be applied.
Table 3
AGC Settings 2
AGC Threshold Hysteresis = 21.3 dB
AGC Digital RSSI Gain Correction = 15.5 dB
AGC
AGC
AGC
Threshold Threshold Threshold
Offset
Low
Up
BPF
RSSI Offset
Compensation
(untrimmed) 1)
300 kHz
-18
63.9 dB
5
1
200 kHz
-18
51.1 dB
11
7
125 kHz
-18
51.1 dB
10
5
80 kHz
4
51.1 dB
9
5
50 kHz
32
51.1 dB
9
5
1) Note: This value needs to be used for calculating the register value
Data Sheet
31
V1.0, 2010-02-19
TDA5225
Functional Description
Attack and Decay coefficients PMF-UP & PMF-DOWN:
The settling time of the loop is determined by means of the integrator gain coefficients
PMFUP and PMFDN, which need to be calculated from the wanted attack and decay
times.
The ADC is running at a fixed sampling frequency of 274kHz. Therefore the integrator is
integrating with PMFUP*274k per second, i.e. time constant is 1/(PMFUP*274k). The
attack times are typically 16 times faster than the decay times.
Typical calculation of the coefficients by means of an example:
•
•
PMFUP = 2^-round( ln(AttTime / BitRate * 274kHz) / ln(2) )
PMFDN = 2^-round( ln(DecTime / BitRate * 274kHz) / ln(2) ) / PMFUP
where AttTime, DecTime = attack, decay time in number of bits
Note: PMFDN = overall_PMFDN / PMFUP
Example:
BitRate = 2kbps
AttTime = 0.1 bits
=> PMFUP = 2^-round(ln(0.1bit/2kbps*274kHz)/ln(2)) = 2^-round(3.8) = 2^-4
DecTime = 2 bits
=> PMFDN = 2^-round(ln(2bit/2kbps*274kHz)/ln(2))/PMFUP = 2^-round(8.1)/2^-4 = 2^-4
Note: In case of ASK with large modulation index the attack time (PMFUP) can be up to
a factor 2 slower due to the fact that the ASK signal has a duty cycle of 50% - during the
ASK low duration the integrator is actually slightly discharged due to the decay set by
PMFDN.
The AGC start and freeze times are programmable. The same conditions can be used
as in the corresponding AFC section above. They will however, be programmed in
separate SFR registers.
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
2.4.6.5
Analog to Digital Converter (ADC)
In front of the AD converter there is a multiplexer so that also temperature and VDDD
can be measured (see Figure 10).
The default value of the ADC-MUX is RSSI (register ADCINSEL: 000 for RSSI; 001 for
Temperature; 010 for VDDD/2).
After switching ADC-MUX to a value other than RSSI in SLEEP Mode, the internal
references are activated and this ADC start-up lasts 100µs. So after this ADC start-up
time the readout measurements may begin. The chip stays in this mode until
reconfiguration of register ADCINSEL to setting RSSI. However, it is recommended to
measure temperature during SLEEP mode (This is also valid for VDDD).
Readout of the 10-bit ADC has to be done via ADCRESH register (the lower 2 bits in
ADCRESL register can be inconsistent and should not be used).
Typical the ADC refresh rate is 3.7 µs. Time duration between two ADC readouts has to
be at least 3.7 µs, so this is already achieved due to the maximum SPI rate (16 bit for
SPI command and address last 8µs at an SPI rate of 2MBit/s). The EOC bit (end of
conversion) indicates a successful conversion additionally. Repetition of the readout
measurement for several times is for averaging purpose.
The input voltage of the ADC is in the range of 1 .. 2 V. Therefore VDDD/2 (= 1.65 V
typical) is used to monitor VDDD.
Further details on the measurement and calibration procedure for temperature and
VDDD can be taken from the corresponding application note.
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
2.4.7
RSSI Peak Detector
The IC possesses digital RSSI peak level detectors. The RSSI level is averaged over 4
samples before it is fed to the peak detectors. This prevents the evaluated peak values
to be dominated by single noise peaks.
f sys
ADC Sampling
Clock Generation
Divide
by 4
fAD C
Integrate
A
from
RSSI
Generator
RSSI Slope
D
fAD C/4
Dump
RSSI
I&D Averaging Filter
RSSI Offset
Compare
Peak Detector
Update
Peak
Value
RSSIPRX
Load
RX_RUN
&
to
ASK path
Read Access to
Register RSSIPRX
from
FSM
from
SPI Controller
RSSIRX
Figure 13
Peak Detector Unit
Peak Detector is used to measure RSSI independent of a data transfer and to digitally
trim RSSI. It is read via SFR RSSIPRX.
Observation of the RSSI signal is active whenever the RX_RUN signal is high. The
RSSIPRX register is refreshed and the Peak Detector is reset after every read access to
RSSIPRX.
It may be required to read RSSIPRX twice to obtain the required result. This is because,
for example, during a trim procedure in which the input signal power is reduced, after
reading RSSIPRX, the peak detector will still hold the higher RSSI level. After reading
RSSIPRX the lower RSSI level is loaded into the Peak Detector and can be read by
reading RSSIPRX again.
Register RSSIPRX should not be read-out faster than 41µs in case AGC is ON (as
register value would not represent the actual, but a lower value).
When the RX_RUN signal is inactive, a read access has no influence to the peak
detector value. The register RSSIPRX is reset to 0 at power up reset.
Peak Detector Wake-Up RSSIPWU (see Figure 10) is used to measure the input signal
power during Wake-Up search. The internal signal RSSIPWU gets initialized to 0 at start
of the first observation time window at the beginning of each configuration/channel. The
peak value of this signal is tracked during Wake-Up search.
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
In case of a Wake-Up, the actual peak value is written in the RSSIPWU register. Even
in case no Wake-Up occurred, actual peak value is written in the RSSIPWU register at
the end of the actual configuration/channel of the Self Polling period. So if no Wake-Up
occurred, then the RSSIPWU register contains the peak value of the last
configuration/channel of the Self Polling period, even in a Multi-Configuration/MultiChannel setup. This functionality can be used to track RSSI during unsuccessful WakeUp search due to no input signal or due to blocking RSSI detection.
For further details please refer to Chapter 2.4.8.2 Wake-Up Generator and
Chapter 2.6.2 Polling Timer Unit.
Input
Data Pattern
Noise
Run-In
Data
Noise
Run-In
Data
SPI read out
RSSIPRX
internal RSSIPRX =
RSSIPRX Register
internal RSSI
SPI
Reset
Figure 14
Peak Detector Behavior
Recommended Digital Trimming Procedure
•
•
•
•
•
•
•
•
•
•
Download configuration file (Run Mode Slave; RSSISLOPE, RSSIOFFS set to
default, i.e. RSSISLOPE=1, RSSIOFFS=0)
Turn off AGC (AGCSTART=0) and set gain to AGCGAIN=0
Apply PIN1 = -85 dBm RF input signal
Read RSSIRX eleven times (minimum 10 ms in-between readings), use average of
last ten readings (always), store as RSSIM1
Apply PIN2 = -65 dBm RF input signal
Read RSSIRX eleven times (minimum 10 ms in-between readings), use average of
last ten readings (always), store as RSSIM2
Calculate measured RSSI slope SLOPEM=(RSSIM2-RSSIM1)/(PIN2-PIN1)
Adjust RSSISLOPE for required RSSI slope SLOPER as follows:
RSSISLOPE=SLOPER/SLOPEM
Adjust RSSIOFFS for required value RSSIR2 at PIN2 as follows:
RSSIOFFS=(RSSIR2-RSSIM2)+(SLOPEM-SLOPER)*PIN2
The new values for RSSISLOPE and RSSIOFFS have to be added to the
configuration!
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
Notes:
1. The upper RF input level must stay well below the saturation level of the receiver (see
Chapter 2.4.6.4 Digital Automatic Gain Control Unit (AGC))
2. The lower RF input level must stay well above the noise level of the receiver
3. If IF Attenuation is trimmed, this has to be done before trimming of RSSI
4. If RSSI needs to be trimmed in a higher input power range the AGCGAIN must be set
accordingly
2.4.8
Digital Baseband (DBB) Receiver
adjust_length
SRC
bypass
8 to 16
samples
per chip
Matched Filter
fractional SRC
From ASK/
FSK
Demodulator
fs out / fs in = 0.5 … 1.0
MUX
RAW Data Slicer
for external
processing
SIGN
Data
Invert
DINVEXT
DATA
(Sliced RAW Data for
external processing )
Figure 15
Data
Invert
DATA_MATCHFIL
(Matched Filtered Data
for external processing )
Functional Block Diagram Digital Baseband Receiver
The digital baseband receiver comprises a matched data filter and a data slicer. The
received data signal is accessible via one of the port pins.
2.4.8.1
Data Filter
The data filter is a matched filter (MF). The frequency response of a matched filter has
ideally the same shape as the power spectral density (PSD) of the originally transmitted
signal, therefore the signal-to-noise ratio (SNR) at the output of the matched filter
becomes maximum. The input sampling rate of the baseband receiver has to be
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
between 8 and 16 samples per chip. The oversampling factor within this range is
depending on the data rate (see Figure 10). The MF has to be adjusted accordingly to
this oversampling. After the MF a fractional sample rate converter (SRC) is applied using
linear interpolation. Depending on the data rate decimation is adjusted within the range
1...2. Finally, at the output of the fractional SRC the sampling rate is adjusted to 8
samples per chip for further processing.
2.4.8.2
Wake-Up Generator
A wake-up generation unit is used only in the Self Polling Mode for the detection of
exceeding a predefined level for RSSI, which then leads to a wake-up and to a change
to Run Mode Self Polling.
A configurable observation time for Wake-up on RSSI can be set in the x_WULOT
register. The Wake-up on RSSI criterion can be handled very quickly for FSK
modulation, while in case of ASK the nature of this modulation type has to be kept in
mind.
RSSI Level
WU
x_WURSSIBHy
Exceeding Threshold
Compare
x_WURSSIBLy
Wake-up
Generation
FSM
No WU
x_WURSSITHy
Figure 16
Wake-Up Generation Unit
The threshold x_WURSSITHy is used to decide whether the actual signal is a wanted
signal or just noise. Any kind of interfering RSSI level can be blocked by using an RSSI
blocking window. This window is determined by the thresholds x_WURSSIBLy and
x_WURSSIBHy, where y represents the actual RF channel. These two thresholds can
be evaluated during normal operation of the application to handle the actual interferer
environment.
The blocking window can be disabled by setting x_WURSSIBHy to the minimum value
and x_WURSSIBLy to the maximum value.
Data Sheet
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V1.0, 2010-02-19
TDA5225
RSSI magnitude
Functional Description
wanted signal
x_WURSSIBHy
interferer
x_WURSSIBLy
wanted signal
x_WURSSITHy
noise floor
Figure 17
RSSI Blocking Thresholds
Threshold evaluation procedure
A statistical noise floor evaluation using read register RSSIPMF (RMS operation) leads
to the threshold x_WURSSITHy. The interferer thresholds x_WURSSIBLy and
x_WURSSIBHy are disabled when they are set to their default values.
For evaluation of the interferer thresholds, either use register RSSIPMF for RMS
operation or during SPM and WU (Wake-Up) on RSSI use register RSSIPWU to
statistically evaluate the interferer band. Finally the thresholds x_WURSSIBLy and
x_WURSSIBHy can be set. Further details can be seen in Figure 10, Chapter 2.4.7
RSSI Peak Detector and Chapter 2.6.2.2 Constant On-Off Time (COO).
NOTE: If e.g. an interferer ends/starts too close after/to the beginning/end of the
observation time, then a decision level error can arise. This is due to the filter dynamics
(settling time). Further, for interferer thresholds evaluation in SPM this changes interferer
statistics. Several interferer measurements are recommended to suppress this, what
makes sense anyway for a better distribution.
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
2.4.9
Power Supply Circuitry
The chip may be operated within a 5 Volts or a 3.3 Volts environment.
VDD5V
En able
IN
En able
IN
Voltage Regulator
5 → 3.3 V
RX_RUN
OUT
Voltage Regulator
5 → 3.3 V
OUT
VDDA
VDDD
E nable
IN
Analog
Section
RF
Section
Voltage Regulator
3.3 → 1.5 V
Digital-I/O
OUT
GNDA
VDDD1V5
E na ble
GNDRF
P_ON
Power-Up
ResetCircuit
Internal
Reset
Digital-Core
Brownout
Detector
GNDD
Figure 18
Power Supply
For operation within a 5 Volts environment (supply voltage range 1), the chip is supplied
via the VDD5V pin. In this configuration the digital I/O pads are supplied via VDD5V and
a 5 V to 3.3 V voltage regulator supplies the analog/RF section (only active in Run
Modes).
When operating within a 3.3 Volts environment (supply voltage range 2), the VDD5V,
VDDA and VDDD pins must be supplied. The 5 V to 3.3 V voltage regulators are inactive
in this configuration.
The internal digital core is supplied by an additional 3.3 V to 1.5 V regulator.
The regulators for the digital section are controlled by the signal at P_ON (Power On)
pin. A low signal at P_ON disables all regulators and set the IC in Power Down Mode. A
low to high transition at P_ON enables the regulators for the digital section and initiates
a power on reset. The regulator for the analog section is controlled by the Master Control
Unit and is active only when the RF section is active.
To provide data integrity within the digital units, a brownout detector monitors the digital
supply. In case a voltage drop of VDDD below approximately 2.45 V is detected a
RESET will be initiated.
Data Sheet
39
V1.0, 2010-02-19
TDA5225
Functional Description
A typical power supply application for a 3.3 Volts and a 5 Volts environment is shown in
the figure below.
*) 22Ω
4.7Ω
TDA5225
4.7Ω
TDA5225
10Ω
VDD5V
VDDA
VDD5V
VDDD
VDDA
100n
100n
100n
GNDRF
Supply -Application in 3.3V environment
*) 1μ
100n
GNDA
GNDD
5V
100n
VDDD1V5
100n
GNDA
VDDD
100n
100n
VDDD1V5
GNDRF
3.3V
GNDD
Supply-Application in 5V environment
*) When operating in a 5V environment, the voltage-drop across the voltage
regulators 5 Æ 3.3V has to be limited , to keep the regulators in a safe
operating range. Resistive or capacitive loads (in excess to the scheme
shown above) on pins VDDA and VDDD are not recommended.
Figure 19
Data Sheet
3.3 Volts and 5 Volts Applications
40
V1.0, 2010-02-19
TDA5225
Functional Description
2.4.9.1
Supply Current
In SLEEP Mode, the Master Control Unit switches the crystal oscillator into Low Power
Mode (all internal load capacitors are disconnected) to minimize power consumption.
This is also valid for Self Polling Mode during Off time (SPM_OFF).
Whenever the chip leaves the SLEEP Mode/SPM_OFF (t1), the crystal oscillator
resumes operation in High Precision Mode and requires tCOSCsettle to settle at the trimmed
frequency. At t2 the analog signal path (RF and IF section) and the RF PLL are activated.
At t3 the chip is ready to receive data. The chip requires tRXstartup when leaving SLEEP
Mode/SPM_OFF until the receiver is ready to receive data.
A transient supply current peak may occur at t1, depending on the selected trimming
capacitance. The average supply current drawn during tRFstartdelay is IRF-FE-startup,BPFcal.
Run Mode*)
SLEEP Mode**)
SPM OFF Time
RX_RUN Signal
Supply
Current
I Run
IRF-FE-startup ,BPFcal
Isleep_low
t1
t2
t3
t
tRFstartdelay
tCOSCsettle
tRXstartup
(To ff )
Ton
(Toff )
*) Run Mode covers the global chip states
: Run Mode Slave/ Receiver active in Self Polling Mode/ Run Mode Self Polling
**) Isleep_low is valid in the chip states: SLEEP / Off time during Self Polling Mode
Figure 20
Supply Current Ramp Up/Down
If the IF buffer amplifier or the clock generation feature (PPx pin active) are enabled, the
respective currents must be added.
Data Sheet
41
V1.0, 2010-02-19
TDA5225
Functional Description
2.4.9.2
Chip Reset
Power down and power on are controlled by the P_ON pin. A LOW at this pin keeps the
IC in Power Down Mode. All voltage regulators and the internal biasing are switched off.
A high transition at P_ON pin activates the appropriate voltage regulators and the
internal biasing of the chip. A power up reset is generated at the same time.
Supply Voltage
at VDDD Pin
3V
Reset- / BrownoutThreshold (typ . 2.45V)
Functional Threshold (typ . 2V)
t
tR eset
Internal Reset
Voltage at PP2 Pin
(NINT Signal)
3V
Reset- / BrownoutThreshold (typ . 2.45V)
Functional Threshold (typ . 2V)
Level on
NINT signal
is undefined
Supply voltage falls below
Reset- / Brownout-Threshold
Supply voltage
falls below
Functional- Threshold
A ‚LOW’ is generated
at NINT signal
Figure 21
A ‚LOW’ is
generated at
PP2 pin
(NINT signal)
Supply voltage
rises above
Functional-Threshold
t
A ‚HIGH’ is
generated at
PP2 pin
(NINT signal)
µC reads
InterruptStatus-Register
A ‚LOW’ is
generated at
PP2 pin
(NINT signal)
Reset Behavior
A second source that can trigger a reset is a brownout event. Whenever the integrated
brownout detector measures a voltage drop below the brownout threshold on the digital
Data Sheet
42
V1.0, 2010-02-19
TDA5225
Functional Description
supply, the integrity of the stored data and configuration can no longer be guaranteed;
thus a reset is generated. While the supply voltage stays between the brownout and the
functional threshold of the chip, the NINT signal is forced to low. When the supply voltage
drops below the functional threshold, the levels of all digital output pins are undefined.
When the supply voltage raises above the brownout threshold, the IC generates a high
pulse at NINT and remains in the reset state for the duration of the reset time. When the
IC leaves the reset state, the Interrupt Status registers (IS0 and IS1) are set to 0xFF and
the NINT signal is forced to low. Now, the IC starts operation in the SLEEP Mode, ready
to receive commands via the SPI interface. The NINT signal will go high, when one of
the Interrupt Status registers is read for the first time.
Data Sheet
43
V1.0, 2010-02-19
TDA5225
Functional Description
2.5
System Interface
In all applications, the TDA5225 receiver IC is attached to an external microcontroller.
This so-called Application Controller executes a firmware which governs the TDA5225
by reading data from the receiver when data has been received on the RF channel and
by configuring the receiver device. The TDA5225 features an easy to use System
Interface, which is described in this chapter.
The TDA5225 supports the so-called Transparent Mode, which provides a rather
rudimentary interface by which the incoming RF signal is demodulated and the
corresponding data is made available to the Application Controller. The usage of the
Transparent Mode will be described in Chapter 2.5.1.2.
2.5.1
Interfacing to the TDA5225
The TDA5225 is interfacing with an application by three logical interfaces, see
Figure 22. The RF/IF interface handles the reception of RF signals and is responsible
for the demodulation. Its physical implementation has been described in Chapter 2.4.3
and Chapter 2.4.8, respectively. The other two logical interfaces establish the
connection to the Application Controller.
For the sake of clarity, the communication between the TDA5225 and the Application
Controller is split into control flow and data flow. This separation leads to an
independent definition of the data interface and the control interface, respectively.
dig. Out
data interface
RX data
RF interface
SPI &
dig. Out
TDA5225
configuration
status & alerts
Application
Controller
(µC)
control interface
Figure 22
Data Sheet
Logical and electrical System Interfaces of the TDA5225
44
V1.0, 2010-02-19
TDA5225
Functional Description
2.5.1.1
Control Interface
The control interface is used in order to configure the TDA5225 after start-up or to reconfigure it during run-time, as well as to properly react on changes in the status of the
receiver in the Application Controller’s firmware. The control interface offers a bidirectional communication link by which
•
•
•
configuration data is sent from the Application Controller to the TDA5225,
the receiver provides status information (e.g. information about the source of a
received data stream, by reading out the interrupt status registers) as response to a
request it has received from the Application Controller, and
the TDA5225 autonomously alerts the Application Controller that a certain,
configurable event has occurred (e.g. that a received signal is above a certain power
level).
Configuration and status information are sent via the 4-wire SPI interface as described
in Chapter 2.5.4. The configuration data determines the behavior of the receiver, which
comprises
•
•
•
scheduling the inactive power-saving phases as well as the active receive phases,
selecting the properties of the RF/IF interface configuration (e.g. carrier frequency
selection, filter settings),
configuring the properties of a received message (e.g. if the received signal strength
is above a certain configurable RSSI threshold level).
Note that the TDA5225 receiver IC supports reception of multiple configuration sets on
multiple channels in a time-based manner without reconfiguration. Thus, the RF/IF
interface as well as the message properties support alternative settings, which can be
activated autonomously by the receiver as part of the scheduling process.
In contrast to the high-level interface used for communicating configuration instructions
and status information, alerts are emitted by the receiver on a digital output pin that may
trigger external interrupts in the Application Controller. Note that the alerting conditions
as well as the polarity of the output pin are configurable, see Chapter 2.5.3.
2.5.1.2
Data Interface
The data interface between the Application Controller and the TDA5225 receiver IC is
used for the transport of the received data, see Figure 22. The features of the data
interface depend on the selected mode of operation.
There are two possible receive modes:
•
•
Transparent Mode - Matched Filter (TMMF)
Transparent Mode - Raw Data Slicer (TMRDS)
Access points for these receive modes can be seen in Figure 15.
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
Transparent Mode - Matched Filter (TMMF)
The received data after the Matched Filter (Two-Chip Matched Filter) with an additional
SIGN function is provided via the DATA_MATCHFIL signal (PPx pin). In this mode
sensitivity measurements with ideal data clock can be performed very simple. For further
details see the block diagram in Figure 15.
Sensitivity in this transparent mode is significantly depending on the implemented clock
and data recovery algorithm of the user software in the application controller.
data
interface
RF Interface
RX data
Application Controller
TDA5225
scheduler
Figure 23
Data interface for the Transparent Mode
Transparent Mode - Raw Data Slicer (TMRDS)
This mode supports processing of data even without bi-phase encoding (e.g. NRZ
encoding) by providing the received data via the One-Chip Matched Filter on the DATA
signal (PPx pin). See more details in the block diagram in Figure 15.
Sensitivity in this transparent mode is significantly depending on the implemented clock
and data recovery algorithm of the user software in the application controller.
The data interface can be seen from Figure 23.
Self Polling capabilities are possible as well, so Constant On-Off Mode and Wake-up on
RSSI can be used. See also example for Configuration B in Figure 24. The needed On
time (latency through TDA5225) is configured in the corresponding On time registers of
the chip. The interrupt for Wake-Up Config B (WUB) is enabled and suitable RSSI
thresholds are set.
If the RSSI signal is in a valid threshold area, the TDA5225 changes to Run Mode Self
Polling and an interrupt can be signaled to the Application Controller.
In case the RSSI signal is outside the valid threshold area, the chip stays in Self Polling
Mode and the external controller gets no interrupt (as the desired RSSI level is not
reached).
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
When the actual processed configuration is the last configuration before the Off time,
then the next programmed channel within the polling cycle would be the sequence of the
Off time.
When data is available and the RSSI is within a valid threshold area, an interrupt is
generated (NINT). So the Application Controller can process the data and decide about
valid data.
In case the controller decides that wrong data was sent, the microcontroller can send the
register command "EXTTOTIM" (see Figure 43 and EXTPCMD register).
When the microcontroller detects valid data, then the controller can send the register
command "EXTEOM found" (see Figure 43 and EXTPCMD register) after completing
the data reception.
The functionality described above can also be used for the receive mode TMMF, where
the external microcontroller takes on responsibility for further data processing.
Good input signal
Wrong input signal
No input signal
SelfPolling Mode
SelfPolling scenario
Sleep Mode
Figure 24
Data Sheet
ConfigA
ConfigB
OFF-time
RSSI level too low Î
Chip stays in Self Polling Mode
and sends no interrupt
Interrupt signal
for RSSI
RunMode SelfPolling
SelfPolling / Sleep
Interrupt signal
for RSSI
RunMode SelfPolling
µC detects invalid data and sends
„EXTTOTIM“Î goto SPM
SelfPolling / Sleep
Interrupt signal
for RSSI
µC finished data reception,
sends „EXTEOM found“
RunMode SelfPolling
SelfPolling / Sleep
External Data Processing
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TDA5225
Functional Description
2.5.2
Digital Output Pins
As long as the P_ON pin is high, all digital output pins operate as described. If the P_ON
pin is low, all digital output pins are switched to high impedance mode.
The digital outputs PP0, PP1, PP2 and PP3 are configurable, where each of the signals
CLK_OUT, RX_RUN, NINT, a LOW level (GND) and a HIGH level, DATA and
DATA_MATCHFIL can be routed to any of the four output pins. There is only one
exception, CLK_OUT is not available on PP3. The default configuration for these four
output pins can be seen in Table 1.
Each port pin can be inverted by usage of PPCFG2 register.
The RX_RUN signal is active high for all Configurations by default. It can be deactivated
for every Configuration separately. Every PPx can be configured with an individual
RX_RUN setup. This can be set in RXRUNCFG0 and RXRUNCFG1 registers.
Interfacing to 3.3V Logic:
The TDA5225 is able to interface directly to a 3.3V logic, when chip is operated in 3.3V
environment.
Interfacing to 5V Logic:
The TDA5225 is able to interface directly to a 5V logic, when chip is operated in 5V
environment.
EMC Reduction of Digital I/Os:
Because electromagnetic distortion generated by digital I/Os may interfere with the high
sensitivity radio receiver, it is recommended that all inputs are filtered by adding an RC
low pass circuit.
2.5.3
Interrupt Generation Unit
The TDA5225 is able to signal interrupts (NINT signal) to the external Application
Controller on one of the PPx port pins (for further details see Chapter 2.5.2 Digital
Output Pins). The Interrupt Generation Unit receives all possible interrupts and sets the
NINT signal based on the configuration of the Interrupt Mask registers (IM0 and IM1).
The Interrupt Status registers (IS0 and IS1) are set from the Interrupt Generation Unit,
depending on which interrupt occurred. The polarity of the interrupt can be changed in
the PPCFG2 register. Please note that during power up and brownout reset, the polarity
of NINT signal is always as described in Chapter 2.4.9.2 Chip Reset.
A Reset event has the highest priority. It sets all bits in the Status registers to “1” and
sets the interrupt signal to “0”. The first interrupt after the Reset event will clear the Status
registers and will set the interrupt signal to “1”, even if this interrupt is masked.
An WU interrupt clears the complementary flags for WU.
Data Sheet
48
V1.0, 2010-02-19
TDA5225
Functional Description
The Interrupt Status register is always cleared after read out via SPI.
WU Cfg A
WUA
WU Cfg B
WUB
WU Cfg C
WUC
WUD
WU Cfg D
Power-Up / Brownout
It is not possible to disable the Power On Reset Indicator Interrupt using the Interrupt
Mask registers.
Interrupt-Mask
IS1 + IS0
IM1 + IM0
NINT
Reset
Interrupt-Signalling
NINT signal
Figure 25
Interrupt Generation Unit
RESET
PP2_select=NINT
PP2INV
SPI READ IS0
IS0
X
FF
01
10
00
PP2(NINT)
WU(A,B)
ConfigA
Figure 26
Data Sheet
ConfigB
Interrupt Generation Waveform (Example for Configuration A+B)
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TDA5225
Functional Description
The following handling mechanism for read-clear registers was chosen due to
implementation of the Burst Read command:
•
•
the current Interrupt Status (ISx) register 8-bit content is latched into the SPI shift
register after the last address bit is clocked-in (point A in Figure 27)
the IS register is then cleared after last IS register bit is clocked out of the SPI
interface (point B in Figure 27)
Consequence: any interrupt event occurring in the window-time between points A and B
is cleared at point B and not stored/shown in an later readout of ISx.
(However: NINT signal is toggling in any case, if occurring interrupt is not masked in IMx
register)
A
B
8-bit @2MHz = 4us
irq1 (masked?)
irq2 (masked?)
nint
ncs
SPI IF
inst
addr
read /readb data = IS(t+0)
read/capture IS*
content
SFR IS* IS(t-1)
IS(t+0)
SFR IS* read clear
@end of data frame
IS(t+1) 0x00
NOTE:
SFR IS(j) status flag is cleared
before it can be read if an IRQ
occurs during SPI data frame
Figure 27
ISx Readout Set Clear Collision
Please see also the IMPORTANT NOTE in the Burst Read section !
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
2.5.4
Digital Control (4-wire SPI Bus)
The control interface used for device control is a 4-wire SPI interface.
•
•
•
•
NCS - select input, active low
SDI
- data input
SDO - data output
SCK - clock input: Data bits on SDI are read in at rising SCK edges and written out
on SDO at falling SCK edges.
Level definition:
logic 0 = low voltage level
logic 1 = high voltage level
Note for non-Burst modes: It is possible to send multiple frames while the device is
selected. It is also possible to change the access mode while the device is selected by
sending a different instruction.
Note: In all bus transfers MSB is sent first.
To read from the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
data byte at this address is then shifted out on SDO. After completing the read operation,
the master sets the NCS line to high.
NCS
Frame
1
8
1
Frame
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
SDO
Register Address
Instruction
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
high impedance Z
Figure 28
Data Sheet
Register Address
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
Data Out
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Read Register
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TDA5225
Functional Description
To read from the device in Burst mode, the SPI master has to select the SPI slave unit
first. Therefore the master has to drive the NCS line to low. After the instruction byte and
the start address byte have been transferred to the SPI slave (MSB first), the slave unit
will respond by transferring the register contents beginning from the given start address
(MSB first). Driving the NCS line to high will end the Burst frame.
NCS
1
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
Register Start Address
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
Data Out (i)
SDO
high impedance Z
Figure 29
Data Out (i+1)
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7
Data Out (i+x)
D0 D7 D6 D5 D4 D3 D2 D1 D0
Burst Read Registers
IMPORTANT NOTE - for being upwards compatible with further versions of the
product, we give following strong recommendation:
For read-clear registers at address (N), no read-burst access stopping at address
(N-1) is allowed, because read-clear register will be cleared without being read out.
Use single read command to read out the register at address (N-1) or extend the
burst read to include the read-clear register at address (N).
To write to the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
following data byte is then stored at this address.
After completing the writing operation, the master sets the NCS line to high.
Additionally the received address byte is stored into the register SPIAT and the received
data byte is stored into the register SPIDT. These two trace registers are readable.
Therefore, an external controller is able to check the correct address and data
transmission by reading out these two registers after each write instruction. The trace
Data Sheet
52
V1.0, 2010-02-19
TDA5225
Functional Description
registers are updated at every write instruction, so only the last transmission can be
checked by a read out of these two registers.
NCS
Frame
1
8
1
Frame
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
SDO
Register Address
Data Byte
Instruction
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Register Address
Data Byte
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
high impedance Z
Figure 30
Write Register
To write to the device in Burst mode, the SPI master has to select the SPI slave unit
first. Therefore the master has to drive the NCS line to low. After the instruction byte and
the start address byte have been transferred to the SPI slave (MSB first) the successive
data bytes will be stored into the automatically addressed registers.
To verify the SPI Burst Write transfer, the current address (start address, start address
+ 1, etc.) is stored in register SPIAT and the current data field of the frame is stored in
register SPIDT. At the end of the Burst Write frame the latest address as well as the
latest data field can be read out to verify the transfer. Note that some error in one of the
intermediate data bytes can not be detected by reading SPIDT.
Driving the NCS line to high will end the Burst frame.
A single SPI Burst Write command can be applied very efficiently for data transfer either
within a register block of configuration dependent registers or within the block of
configuration independent registers.
NCS
1
8
1
8
1
8
1
8
1
8
SCK
Instruction
SDI
SDO
Register Start Address
Data Byte (i)
Data Byte (i+1)
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Data Byte (i+x)
D7 D6 D5 D4 D3 D2 D1 D0
high impedance Z
Figure 31
Data Sheet
Burst Write Registers
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TDA5225
Functional Description
The SPI also includes a safety feature by which the checksum is calculated with an
XOR operation from the address and the data when writing SFR registers. The
checksum is in fact an XOR of the data 8-bitwise after every 8 bits of the SPI write
command. The calculated checksum value is automatically written in the SPICHKSUM
register and can be compared with the expected value. After the SPICHKSUM register
is read, its value is cleared.
In case of an SPI Burst Write frame, a checksum is calculated from the SPI start address
and consecutive data fields.
enable every 8 bit
SPI shift register
Checksum SFR
XOR
Figure 32
SPI Checksum Generation
Table 4
Instruction Set
read/clear
Instruction
Description
Instruction Format
WR
Write to chip
0000 0010
RD
Read from chip
0000 0011
WRB
Write to chip in Burst mode
0000 0001
RDB
Read from chip in Burst mode 0000 0101
Data Sheet
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V1.0, 2010-02-19
TDA5225
Functional Description
2.5.4.1
Timing Diagrams
tDeselect
NCS
tnot_hold
tSetup
tCLK_H
thold
tnot_setup
SCK
tSDI_setup
tSDI_hold
tCLK_L
SDI
high impedance Z
SDO
Figure 33
Serial Input Timing
NCS
tCLK_H
SCK
tCLK_SDO
tCLK_SDO
tCLK_L
tSDO_r
tSDO_disable
tSDO_f
Z
SDO
SDI
Z
ADDR LSB
Figure 34
Data Sheet
Serial Output Timing
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TDA5225
Functional Description
Table 5
SPI Bus Timing Parameter
Symbol
Parameter
fclock
Clock frequency
tCLK_H
Clock High time
tCLK_L
Clock Low time
tsetup
Active setup time
tnot_setup
Not active setup time
thold
Active hold time
tnot_hold
Not active hold time
tDeselect
Deselect time
tSDI_setup
SDI setup time
tSDI_hold
SDI hold time
tCLK_SDO
Clock low to SDO valid
tSDO_r
SDO rise time
tSDO_f
SDO fall time
tSDO_disable
SDO disable time
2.5.5
Chip Serial Number
Every device contains a unique, preprogrammed 32-bit wide serial number. This number
can be read out from SN3, SN2, SN1 and SN0 registers via the SPI interface. The
TDA5225 always has SN0.6 set to 0 and SN0.5 set to 1.
SN0
......
......
Fuses
FuseReadoutInterface
SN1
SN2
SN3
Figure 35
Data Sheet
Chip Serial Number
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V1.0, 2010-02-19
TDA5225
Functional Description
2.6
System Management Unit (SMU)
The System Management Unit consists of two main units:
•
•
Master Control Unit, where the various operating modes can be configured.
Polling Timer Unit, where the receiver’s On and Off times and modes are defined.
The Polling Timer Unit is only working in the Self Polling Mode.
2.6.1
Master Control Unit (MCU)
2.6.1.1
Overview
The Master Control Unit controls the operation modes and the global states.
The transparent data stream can be processed externally by the Application Controller
(see Chapter 2.5.1.2 Data Interface).
The following operation modes and the behavior of the Master Control Unit are fully
automatic and only influenced by SFR settings and by incoming RF data streams.
The TDA5225 has two major operation modes, which are switched by SFR bit MSEL.
In Slave Mode the device is controlled via SPI by the external microcontroller. This mode
supports:
•
•
•
Run Mode Slave (RMS), where the receiver is continuously active
SLEEP Mode, where the receiver is switched off for power saving. This mode can
also be used to change register settings
HOLD Mode, allows register settings to be changed. The change to HOLD Mode and
back to RMS is faster than changing to SLEEP Mode and back to RMS.
In Slave Mode, switching between configurations and channels, as well as between Run
and SLEEP Mode must be initiated by the microcontroller.
In Self Polling Mode, TDA5225 autonomously polls for incoming RF signals. The
receiver switches automatically between up to four configurations (Configuration A, B, C
and D) and up to 3 channels per configuration (Further information can be found in
Chapter 2.6.2).
Between the RF signal scans, the receiver is automatically switched to Low Power Mode
for reducing the average power consumption. If an incoming signal fulfills the selected
wake-up criterion an interrupt can be generated and Run Mode Self Polling will be
entered.
Data Sheet
57
V1.0, 2010-02-19
TDA5225
Functional Description
Init
Reset
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == 0
Bit:MSEL == 0
Sleep Mode
Initialize RX-Part
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Chip is idle
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Bit:SLRXEN == 1
Bit:MSEL == 0
Run Mode
Slave
Bit:SLRXEN == 1
Bit:MSEL == 0
Chip is permanently
active
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
Init
Initialize RX-Part
Bit:SLRXEN == X
Bit:MSEL == 0
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
ToTim Timeout == X
Self Polling
Mode
Bit:SLRXEN == X
Bit:MSEL == 1
EOM found == 1
Chip is periodically active
and searching for
WU criteria
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 1
Run Mode
Self Polling
Chip is permanently
active
Figure 36
2.6.1.2
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 0
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 1
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 0
Global State Diagram
Run Mode Slave (RMS)
In Run Mode Slave, the receiver is able to continuously scan for incoming data streams.
Detection and validation of a wake-up criterion are not performed.
The transparent data stream can be processed externally by the Application Controller
(see Chapter 2.5.1.2 Data Interface).
Run Mode Slave is entered by setting SFR CMC0 bits MSEL to 0 and SLRXEN to 1.
Configurations are switched via SFR bit group MCS in the CMC0 register. The RF
channel in use can be selected in the x_CHCFG register, the frequency selection is
defined by SFRs x_PLLINTCy, x_PLLFRAC0Cy, x_PLLFRAC1Cy, x_PLLFRAC2Cy,
where x = A, B, C or D and y = 1, 2 or 3.
The configuration may be changed only in SLEEP or in HOLD Mode before returning to
the previously selected operation mode. This is necessary to restart the state machine
Data Sheet
58
V1.0, 2010-02-19
TDA5225
Functional Description
with defined settings at a defined state. Otherwise the state machine may hang up.
Reconfigurations in HOLD Mode are faster, because there is no Start-Up sequence.
The following flowchart and explanation show and help to understand the internal
behavior of the Finite State Machine (FSM) in Run Mode Slave.
1
Wait
Startup Finished == 0
Wait Till Startup
Has Finished
Startup Finished == 1
2
INIT
3
Receive
Hold == 0
4
Hold
Ready for
reconfiguration
Figure 37
2.6.1.3
Hold == 1
No Change in
Operating Mode
Data Available
At Port Pin
Run Mode Slave
HOLD Mode
This state (item 4 in Figure 37) is used for fast reconfiguration of the chip in Run Mode
Slave. HOLD state can be reached after the Start-Up Sequencer and Initialization of the
chip have been completed and the chip is working in state 3. To reconfigure the chip the
SFR control bit HOLD must be set. After reconfiguration in this state the SFR control bit
HOLD must be cleared again. After leaving the HOLD state, the INIT state is entered and
the receiver can work with the new settings. Be aware that the time between changing
the configuration and reinitialization of the chip has to be at least 40us. Take note that
one SPI command for clearing the SFR control bit HOLD needs 24 bits or 12μs at an SPI
data rate of 2.0Mbit/s. The remaining 28μs must be guaranteed by the application.
FSM State
SPI Command
Data available at Port Pin
Instruction Address
Write
CMC0
0x02
Data
HOLD=1
HOLD
Instruction Address
Data
Write
x_CHCFG/ (sel. other
0x02
x_PLL..
channel)
INIT
Instruction Address
Write
CMC0
0x02
Data
available at
Port Pin
Data
HOLD=0
12us @ 2. 0MHz
40us
Figure 38
Data Sheet
HOLD State Behavior (INITPLLHOLD disabled)
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V1.0, 2010-02-19
TDA5225
Functional Description
In case of large frequency steps, an additional VAC routine (VCO Automatic Calibration)
has to be activated when recovering from HOLD Mode (INITPLLHOLD bit). The
maximum allowed frequency step in HOLD Mode without activation of VAC routine is
depending on the selected frequency band. The limits are +/- 1 MHz for the 315 MHz
band, +/- 1.5 MHz for the 434 MHz band and +/- 3 MHz for the 868/915 MHz band.
When this additional VAC routine is enabled, the TDA5225 starts initialization of the
Digital Receiver block after release from HOLD and an additional Channel Hop time.
FSM State
SPI Command
Data available at Port Pin
Instruction Address
Write
CMC0
0x02
Data
HOLD=1
VAC
HOLD
Instruction Address
Data
Write
x_CHCFG/ (sel. other
0x02
x_PLL..
channel)
Instruction Address
Write
CMC0
0x02
VAC
INIT
Data
available at
Port Pin
Data
HOLD=0
12us @ 2.0MHz
t C_ Hop
40us
Figure 39
HOLD State Behavior (INITPLLHOLD enabled)
HOLD Mode is only available in Run Mode Slave. Configuration changes in Self Polling
Mode have to be done by switching to SLEEP Mode and returning to Self Polling Mode
after reconfiguration.
2.6.1.4
SLEEP Mode
The SLEEP Mode is a power save mode. The complete RF part is switched off and the
oscillator is in Low Power Mode. As in HOLD Mode, the chip can be reconfigured. When
switching from SLEEP to Run Mode Slave, the state machine starts with the internal
Start-Up Sequence.
2.6.1.5
Self Polling Mode (SPM)
In Self Polling Mode TDA5225 autonomously polls for incoming RF wake-up data
streams. At that time there is no processing load on the host microcontroller. When a
wake-up criterion has been found, an interrupt can be generated and the TDA5225 mode
will be changed to Run Mode Self Polling.
A general overview on a typically transmitted protocol and the behaviour of the TDA5225
is given in Figure 40.
Data Sheet
60
V1.0, 2010-02-19
TDA5225
Functional Description
TX - RX interaction in RX - Self Polling Mode
TX Telegram:
Wake-up Frame
Wake-up Frame continued
RUNIN + Wake-up sequence
or Gap
1)
Data Frame
(RUNIN)
TSI
PAYLOAD
EOM
RX Mode:
On time 2)
Self Polling Mode
On time 2)
Self Polling Mode
a
b
Run Mode Self Polling
Legend:
1) There can either be a Wake -up Frame directly followed by a Data Frame or the Wake -up Frame is separated from the Data Frame by a Gap in -between .
2) The position of the O n time can vary (a, b, ...) as there is no synchronization between transmitted telegram and start of the receiver’s On time.
Figure 40
SPM - TX-RX Interaction
The transparent data stream can be processed externally by the Application Controller
(see Chapter 2.5.1.2 Data Interface).
Self Polling Mode is entered by setting the MSEL register bit to 1.
Configuration changes are allowed only by switching to SLEEP Mode, and returning to
Self Polling Mode after reconfiguration.
The Polling Timer Unit controls the timing for scanning (On time) and sleeping (Off
time, SPM_OFF). Up to four independent configuration sets (A, B, C and D) can
automatically be processed, thus enabling scanning from different transmit sources.
Additionally, up to 3 different frequency channels within each configuration may be
scanned to support Multi-Channel applications. See also Chapter 2.6.2 Polling Timer
Unit. So a total number of up to 12 different frequency channels is supported.
The Wake-Up Generation Unit identifies, whether an incoming data stream matches
the configurable wake-up criterion.
After fulfillment of the wake-up criterion, modulation can be switched automatically.
See also Chapter 2.6.1.6 Automatic Modulation Switching and Chapter 2.5.1.2 Data
Interface (in Subsection TMRDS).
The following state diagrams and explanations help to illustrate the behavior during Self
Polling Mode. First there is a search for a wake-up criterion according to Configuration
A on up to three different channels. Then, there is an optional search for a wake-up
criterion according to Configuration B, C and D, again including up to 3 channels.
In applications using only Single-Configuration, settings are always taken from
Configuration A.
Data Sheet
61
V1.0, 2010-02-19
TDA5225
Functional Description
RX_RUN=0
RX_RUN == 0
1
IDLE
Chip is idle
RX_RUN == 1
2
Wait
Startup Finished == 0
Wait Till Startup
Has Finished
From Run Mode Self Polling
Startup Finished == 1
Init
Loop Counter
3
CfgLoopCounter ,
Loop Counter
is Initialized
WU Search With
Configuration A
Modulation
Switching CFG A
4
Modulation Selection
Depending On Register
Setting
Init With
CFG A
5
Initialize RX- Part
Configuration A
Loop Counter == 10
Load
Channel 1
6
11
Initialize RX- Part
Multi Channel A
Load
Channel 2
Initialize RX-Part
Multi Channel A
Loop Counter == 11
11
Load
Channel 3
Initialize RX-Part
Multi Channel A
Const On Time
7
ON Time elapsed == 0
WU Found == 0
WU Search
CFG A COOT
Search For A Configurated
Wake Up Criteria
Const On Off
ON Time elapsed == 1
WU Found == 0
ON Time elapsed == X
WU Found == 1
9
10
Compare
Compare Loop Counter
Against Number Of
Channels
Loop Counter Equal ANOC == 1
CfgLoopCounter <> CfgNr
Loop Counter <> ANOC
Increment
Loop Counter
Incrementation Of
The Loop Counter
Loop Counter == ANOC
CfgLoopCounter == CfgNr
8
Store
Channel
Store The Current Channel
Configuration Into Actual
Channel Register
12
Generating CFG A
Interrupt If Not Masked
Run Mode
Self Polling
Chip is permanently
active
To Init Loop Counter
of Config B
Figure 41
Data Sheet
From Compare of
Config B, C, D
Wake-up Search with Configuration A
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V1.0, 2010-02-19
TDA5225
Functional Description
From Compare of
Config A, B, C
To Idle of
Config A
WU Search With
Configuration B, C, D
3
Init
Loop Counter
Loop Counter Is
Initialized
4
Modulation
Switching CFG B,C,D
Modulation Selection
Depending On Register
Setting
5
Init With
CFG B,C,D
Initialize RX-Part
Configuration B ,C,D
Loop Counter == 10
6
Load
Channel 1
11
Initialize RX-Part
Multi Channel B,C,D
Load
Channel 2
Loop Counter == 11
11
Initialize RX- Part
Multi Channel B,C,D
Load
Channel 3
Initialize RX-Part
Multi Channel B,C,D
Const On Time
7
ON Time elapsed == 0
WU Found == 0
WU Search
CFG B,C,D COOT
Search For A Configurated
Wake Up Criteria
Const On Off
ON Time elapsed == X
WU Found == 1
ON Time elapsed == 1
WU Found == 0
9
10
Compare
Compare Loop Counter
Against Number Of
Channels
Loop Counter Equal (B,C,D)NOC == 1
CfgLoopCounter <> CfgNr
Incrementation Of
The Loop Counter
Store
Channel
Store The Current Channel
Configuration Into Actual
Channel Register
12
Generating CFG B ,C,D
Interrupt If Not Masked
Run Mode
Self Polling
Chip is permanently
active
To Init Loop Counter
of Config C,D
Data Sheet
Increment
Loop Counter
Loop Counter == (B,C,D)NOC
CfgLoopCounter == CfgNr
8
Figure 42
Loop Counter <> (B,C,D)NOC
Wake-up Search with Configuration B, C, D
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TDA5225
Functional Description
2.6.1.6
Automatic Modulation Switching
In Self Polling Mode, the chip is able to automatically change the type of modulation
after a wake-up criterion was fulfilled in a received data stream. The type of modulation
used in the different operational modes is selected by the SFR control bit MT.
2.6.1.7
Multi-Channel in Self Polling Mode
As previously mentioned, in Self Polling Mode the TDA5225 allows RF scans on up to
three RF channels per configuration, this can be defined in the x_CHCFG register.
Channel frequencies are defined in registers x_PLLINTCy, x_PLLFRAC0Cy,
x_PLLFRAC1Cy, x_PLLFRAC2Cy, where x = A, B, C or D and y = 1, 2 or 3.
The channel number at which a wake-up criterion has been found is available in register
RFPLLACC. See also Chapter 2.4.5 Sigma-Delta Fractional-N PLL Block.
2.6.1.8
Run Mode Self Polling (RMSP)
Wake-Up criterion fulfillment in Self Polling Mode for RSSI leads to a change to Run
Mode Self Polling and a transparent data stream can be processed externally by the
Application Controller (see Chapter 2.5.1.2 Data Interface).
Modulation switching is performed automatically, depending on register settings (see
Chapter 2.6.1.6 Automatic Modulation Switching)
Depending on interrupt masking, the host microcontroller is alerted when the level
criterion RSSI is fulfilled. See also Chapter 2.5.3 Interrupt Generation Unit
Run Mode Self Polling is left, when the timeout timer command “EXTTOTIM” is sent by
the Application Controller, or when an “EXTEOM found” command is sent by the
microcontroller and the SFR bit EOM2SPM is activated, or when the operating mode is
switched to SLEEP or Run Mode Slave by the host microcontroller.
When the TDA5225 gets the “EXTTOTIM” command, the receiver proceeds with Self
Polling Mode and with searching for a suitable wake-up criterion on the next
programmed channel (either next RF channel or next configuration, depending on the
selected mode - Multi-Configuration or Multi-Channel or a mix of both) or a search for a
wake-up criterion in Configuration A is initiated.
As long as the chip is in Run Mode Self Polling, the transparent data stream can be
processed externally by the Application Controller.
After an EOM was found, the information about the RF channel and the configuration of
the actual payload data is saved in the RFPLLACC register.
After receiving the “EXTEOM found” command the TDA5225 can either proceed with a
search for a wake-up criterion in the next configuration or a search for wake-up in
Data Sheet
64
V1.0, 2010-02-19
TDA5225
Functional Description
Configuration A can follow or the TDA5225 can proceed receiving another (redundant)
payload data frame within the same configuration.
The transparent data stream has to be processed externally by the Application
Controller. Therefore the external controller needs the possibility to send following
commands (see Figure 43 and EXTPCMD register as well):
•
•
EXTTOTIM: So the TDA5225 can proceed with Self Polling Mode (either with the
next programmed channel or with Configuration A).
EXTEOM found: In this case the TDA5225 can either proceed with Self Polling Mode
(either with the next configuration or with Configuration A) or stay in Run Mode Self
Polling.
When the actual processed configuration is right before the Off time and the Application
Controller sends one of the above mentioned commands, then the TDA5225 can
proceed with the Off time (in case next configuration is selected).
In Constant On-Off Time Mode the Polling Timer is always initialized after a TOTIM or
EOM event. This means a new On period is always started.
Data Sheet
65
V1.0, 2010-02-19
TDA5225
Functional Description
1
10
Modulation
Switching
Modulation Selection
Depending On Register
Setting
INIT
All Operations Are Done With
The Wake Up Configuration
INITDRXES==1
Init Digital Receiver
2
INIT
To Self Polling Mode
(WU Search With
Configuration A )
INITDRXES==0
To Self Polling Mode
(WU Search With
Configuration A)
EOM2nCfg == 0
To Self Polling Mode
(WU Search With
Next Configuration)
Receive
Data Avaialble
At Port Pin
EOM2nCfg == 1
9
To Self Polling Mode
(WU Search With Next
Programmed Channel)
3
Goto
Next Config
After EOM
TOTIM2nCH == 0
5
TOTIM2nCH == 1
Goto SP Next
Programmed
Channel
No Change in
Operating Mode
EOM2SPM == 0
EOM2SPM == 1
8
Goto SelfPolling
After EOM
7
Save
Channel and
Configuration
Information
4
6
EOM Found == 1
Figure 43
Data Sheet
EXTEOM Found
EXTTOTIM
Command Sent by
External Controller
Command Sent by
External Controller
ToTim Timeout == 1
Run Mode Self Polling
66
V1.0, 2010-02-19
TDA5225
Functional Description
SPMIP
Timer-Status
Timer-Status
SPM
Active-Idle Period Timer
(5 / 8 Bit)
Timer-Control
fOnOff
Receiver-Enable
Self-Polling-Mode (SPM)
FSM
No WU
SPMC
Polling Mode
Figure 44
SPMAP
SPMOFFT1
SPMOFFT0
SPM
On-Off-Timer
(14 Bit)
fRT
Timer-Control
SPM
Reference-Timer
(8 Bit)
Timer-Control
f sys / 64
SPMONTx1
SPMONTx0
Polling Timer Unit
SPMRT
2.6.2
to
Master-Control-Unit
Polling Timer Unit
The Polling Timer Unit consists of a Counter Stage and a Control FSM (Finite State
Machine).
The Counter Stage is divided into three sub-modules.
The Reference Timer is used to divide the state machine clock (fsys/64) into the slower
clock required for the SPM timers.
The On-Off Timer and the Active Idle Period Timer are used to generate the polling
signal. The entire unit is controlled by the SPM FSM.
The TDA5225 is able to handle up to four different sets of configurations automatically.
However, the example and figure in this subsection only show up to two configuration
sets for the sake of clarity.
Data Sheet
67
V1.0, 2010-02-19
TDA5225
Functional Description
2.6.2.1
Self Polling Mode
An actual value for RSSI exceeding a certain adjustable threshold forces the TDA5225
into Run Mode Self Polling.
The timing resolution is defined by the Reference Timer, which scales the incoming
frequency (fsys/64) corresponding to the value, which is defined in the Self Polling Mode
Reference Timer (SPMRT) register. Changing values of SPMRT helps to fit the final OnOff timing to the calculated ideal timing.
2.6.2.2
Constant On-Off Time (COO)
In this mode there is a constant On and a constant Off time. Therefore also the resulting
master period time is constant. The On and Off time are set in the SPMONTA0,
SPMONTA1, SPMONTB0, SPMONTB1, SPMONTC0, SPMONTC1, SPMONTD0,
SPMONTD1, SPMOFFT0 and SPMOFFT1 registers. The On time configuration is done
separately for Configuration A, B, C and D.
When Single-Configuration is selected then only Configuration A is used. The number
of RF channels is defined in the A_CHCFG register (Single-Channel or Multi-Channel
Mode).
Multi-Configuration Mode allows reception of up to 4 different transmit sources. The
corresponding RF channels can be defined in the A_CHCFG, B_CHCFG, C_CHCFG
and D_CHCFG registers. In the case of Multi-Channel or combination of Multi-Channel
and Multi-Configuration Mode, the configured On time is used for each RF channel in a
configuration. The diagram below shows possible scenarios.
All receive modes described in Chapter 2.5.1.2 Data Interface can be used.
Data Sheet
68
V1.0, 2010-02-19
TDA5225
Functional Description
Single Channel, Single Config
run mode
RX polling
sleep mode
A
1
TAON
Channels = 1
TMasterPeriod = TAON + TOFF
TOFF
TMasterPeriod
Multi Channel, Single Config
run mode
RX polling
sleep mode
A
1
A
2
A
3
TAON T AON TAON
Channels = m
TMasterPeriod = m*TAON + TOFF
TOFF
TMasterPeriod
Multi Channel, Multi Config
run mode
RX polling
sleep mode
A
1
A
2
A
3
B
1
TAON T AON TAON TBON
B
2
TBON
Channels Config A = m
Channels Config B = n
TMasterPeriod = m*TAON + n*T BON+ TOFF
TOFF
TMasterPeriod
Figure 45
Constant On-Off Time
Calculation of the On time:
The On time for each channel must be long enough to ensure proper detection of a
specified wake-up criterion. Therefore the On time depends on the wake-up pattern. It
has to include transmitter data rate tolerances.
TON also must include the relevant start-up times. In case of the first channel after TOFF,
this is the Receiver Start-Up Time. In case of following channels (RF Receiver is already
on, there is only a change of the channel or the configuration), e.g. if Configuration B is
used, this is the Channel Hop Latency Time.
Calculation of the Off time:
The longer the Off time, the lower the average power consumption in Self Polling Mode.
On the other hand, the Off time has to be short enough that no transmitted wake-up
pattern is missed. Therefore the Off time depends mainly on the duration of the expected
wake-up pattern.
If there are further channels scanned, TOFF has to be reduced by the related additional
On times.
Data Sheet
69
V1.0, 2010-02-19
TDA5225
Functional Description
For basic timing of WU on RSSI in COO mode, please see Figure 46.
RF signal
e.g . ASK
t
RX ON
SLEEP
t
t WULOT t WULOT
t Startup
1
t WULOT t WULOT_part
n-1
2
npartially
last observation time
window is forced to end by
end of t ON
latest decision here !
tON
Figure 46
COO Polling in WU on RSSI Mode
Always check at the end of the current observation time window, if there is a WU (WakeUp) event or NOT. This means, in algorithmic description (see also Figure 10,
Chapter 2.4.7 RSSI Peak Detector and Chapter 2.4.8.2 Wake-Up Generator):
if (RSSIPWU_value > x_WURSSITHy) and (RSSIPWU_value > x_WURSSIBHy)
then WU
else NOT
Here, ‘NOT‘ means to keep on evaluating and move on to the next observation time
window, also keep on peak value tracking of RSSIPWU signal. Keep on walking through
the observation time windows until there is a WU event from the algorithm above or
finally decide at the end of the On time with the following algorithm:
if (RSSIPWU_value > x_WURSSITHy) and (RSSIPWU_value < x_WURSSIBLy or
RSSIPWU_value > x_WURSSIBHy)
then WU
else NOT
If there is a WU event at the end of an observation time window while walking through
the observation time windows, freeze/hold this decision/peak value in register RSSIPWU
for optional read out and switch to run mode self polling.
Data Sheet
70
V1.0, 2010-02-19
TDA5225
Functional Description
2.6.2.3
Active Idle Period Selection
This mode is used to deactivate some polling periods and can additionally be applied to
the above mentioned Polling Mode.
Normally, polling starts again after the TMasterPeriod. With this Active Idle Period selection
some of the polling periods can be deactivated, independent from the Polling Mode. The
active and the idle sequence is set with the SPMAP and the SPMIP registers. The values
of these registers determine the factor M and N.
run mode
RX polling
sleep mode
TOn
TOff
TMasterPeriod
Figure 47
Data Sheet
M*TMasterPeriod
N*TMasterPeriod
Active
Idle
Active Idle Period
71
V1.0, 2010-02-19
TDA5225
Functional Description
2.7
Definitions
2.7.1
Definition of Bit Rate
The definition for the bit rate in the following description is:
symbols
bitrate = ---------------------s
If a symbol contains n chips (for Manchester n=2; for NRZ n=1) the chip rate is n times
the bit rate:
chiprate = n × bitrate
2.7.2
Definition of Manchester Duty Cycle
Several different definitions for the Manchester duty cycle (MDC) are in place. To avoid
wrong interpretation some of the definitions are given below.
Level-based Definition
MDC = Duration of H-level / Symbol period
bit = 1
1
0
0
1
0
1
1. chip
2. chip
Tb it
Tc hip
MDC < 50%
1
1
0
TH
ΔT
TH
Tb it
Tc hip
Tb it
MDC > 50%
ΔT
Tc hip
Figure 48
TH
TH
Tb it
Tb it
Definition A: Level-based definition
This definition determinates the duty cycle to be the ratio of the high pulse width and the
ideal symbol period. The DC content is constant and directly proportional to the specified
duty cycle.
For ΔT > 0 the high period is longer than the chip-period and for ΔT < 0 the high period
is shorter than the chip-period.
Data Sheet
72
V1.0, 2010-02-19
TDA5225
Functional Description
Depending on the bit content, the same type of edge (e.g. rising edge) is sometimes
shifted and sometimes not.
With this definition the Manchester duty cycle is calculated to
T chip + ΔT
TH
MDC A = --------- = --------------------------T bit
T bit
Chip-based Definition
MDC = Duration of the first chip / Symbol period
bit = 1
1
0
0
1
0
1
1. chip
2. chip
Tb it
Tc hip
MDC < 50%
1
1
ΔT
0
T1 .ch ip
T1.ch ip
Tb it
Tc hip
Tbit
MDC > 50%
ΔT
Tc hip
Figure 49
T1.ch ip
T1 .chip
Tb it
Tbit
Definition B: Chip-based definition
This definition determinates the duty cycle to be the ratio of the first symbol chip and the
ideal symbol period independently of the information bit content. The DC content
depends on the information bit and it is balanced only if the message itself is balanced.
For ΔT > 0 the first chip-period is longer than the ideal chip-period and for ΔT < 0 the first
chip-period is shorter than the ideal chip-period.
Depending on the bit content, the same type of edge (e.g. rising edge) is sometimes
shifted and sometimes not.
Data Sheet
73
V1.0, 2010-02-19
TDA5225
Functional Description
With this definition the Manchester duty cycle is calculated to
T chip + ΔT
T 1.chip
MDC B = ---------------- = -------------------------T bit
T bit
Edge delay Definition
MDC = Duration delayed edge / Symbol period
bit = 1
1
0
0
1
1
1. chip
2. chip
Tb it
Tc hip
MDC < 50% Tf = 0
1
Tr
ΔT
1
0
0
Tb it
Tbit
Tb it
TH
Tc hip
Tr
TH
MDC > 50% Tr = 0
1
1
ΔT
Tc hip
Figure 50
0
0
Tf
1
Tf
TH
TH
Tb it
Tbit
Tb it
Definition C: Edge delay definition
This definition determinates the duty cycle to be the ratio of the duration of the delayed
high-chip and the ideal symbol period independently of the information bit content. The
position of the high-chip is determined by the delayed rising edge and/or the delayed
falling edge. For ΔT = Tfall -Trise the Manchester duty cycle is calculated to
T chip + ΔT
T chip + T fall – T rise
T delayedHighchip
MDC C = ---------------------------------------- = -------------------------- = -----------------------------------------------T bit
T bit
T bit
Independent on the bit content, the same type of edge (rising edge and/or falling edge)
is shifted.
Data Sheet
74
V1.0, 2010-02-19
TDA5225
Functional Description
2.7.3
Definition of Power Level
The reference plane for the power level is the input of the receiver board. This means,
the power level at this point (Pr) is corrected for all offsets in the signal path (e.g.
attenuation of cables, power combiners etc.).
The specification value of power levels in terms of sensitivity is related to the peak power
of Pr in case of On-Off Keying (OOK). This is noted by the unit dBm peak.
Specification value of power levels is related to a Manchester encoded signal with a
Manchester duty cycle of 50% in case of ASK modulation.
An RF signal generator usually displays the level of the unmodulated carrier (Pcarrier).
This has following consequences for the different modulation types:
Table 6
Power Level
Modulation
scheme
Realization with RF signal
generator
Power level specification
value
ASK
AM 100%
Pr = Pcarrier + 6dB
ASK
Pulse modulation (=OOK)
Pr = Pcarrier
FSK
FM with deviation Δf:
f1 = fcarrier - Δf
f2 = fcarrier + Δf
Pr = Pcarrier
For power levels in sensitivity parameters given as average power, this is noted by the
unit dBm. Peak power can be calculated by adding 3 dB to the average power level in
case of ASK modulation and a Manchester duty cycle of 50%.
2.7.4
Figure 51
Data Sheet
Symbols of SFR Registers and Control Bits
CONTROL
Symbolizes unique SFR registers or SFR control bit (s),
which are common for all configuration sets .
CONTROL
Symbolizes SFR registers or SFR control bit (s) with
Multi-Configuration capability (protocol specific).
In case of SFR register, the name starts with A _, B_, C_
or D_, depending on the selected configuration. This is
generally noted by the prefix „x _“.
SFR Symbols
75
V1.0, 2010-02-19
TDA5225
Functional Description
2.8
Digital Control (SFR Registers)
2.8.1
SFR Address Paging
An SPI instruction allows a maximum address space of 8 bit. The address space for
supporting more than one configuration set is exceeding this 8 bit address room.
Therefore a page switch is introduced, which can be applied via register SFRPAGE (see
Figure 52).
logical address space
0x000
Configuration A 1) - Page 0
physical address space
0
d
Reserved 2)
0x080
0x0FF
0x100
Common Registers
Reserved
Reserved 2)
3)
4)
Configuration B 1) - Page 1
128 d
255 d
256 d
Reserved 2)
0x180
0x1FF
0x200
Common Registers 3)
Reserved 4)
Configuration C
1)
- Page 2
0x2FF
0x300
Common Registers 3)
Reserved 4)
Configuration D
1)
- Page 3
0x3FF
1)
2), 4)
3)
Figure 52
2.8.2
Reserved
4)
Configuration B 1) - Page 1
384 d
511 d
512 d
Configuration C 1) - Page 2
Reserved 2)
640 d
767 d
768 d
Reserved 2)
0x380
Common Registers 3)
Reserved 2)
Reserved 2)
0x280
Configuration A 1) - Page 0
Configuration D
1)
- Page 3
Reserved 2)
Common Registers 3)
896 d
Reserved 4)
1023 d
Configuration dependent register block (4 protocol specific sets)
page switch via SFRPAGE register
Reserved – Forbidden area
Configuration independent registers (common for all configurations )
map (“mirror“ ) to the same physical address space
SFR Address Paging
SFR Register List and Detailed SFR Description
The register list is attached in the Appendix at the end of the document.
Registers for Configurations B, C and D are equivalent and not shown in detail.
All registers with prefix “A_” are related to Configuration A. All these registers are also
available for Configuration B, C and D having the prefix “B_”, “C_” and “D_”.
Data Sheet
76
V1.0, 2010-02-19
TDA5225
Applications
3
Applications
RF in
SAW
filter
to µC
SPI Bus
SDI 18
SCK 17
NCS 16
XTAL2 15
11 PP1
12 PP2
13 P_ON
14 XTAL1
SDO 19
T1 20
T2 21
LNA_INN 22
LNA_INP 23
GNDRF 24
PP3 25
RSSI 26
IFMIX_INP
IFMIX_INN
VDD5V
VDDD
VDDD1V5
GNDD
4
5
6
7
8
9
10 PP0
GNDA
TDA5225
3
IFBUF_OUT
2
VDDA 27
IFBUF_IN
1
IF CER
filter
(opt.)
IF_OUT 28
VS
IF CER
filter
(opt.)
VS
to/from µC
Figure 53
Typical Application Schematic
Note: As a good practice in any RF design, shielding around sensitive nodes can
improve the EMC performance of the application.
For achieving the best sensitivity results the following has to be kept in mind. Every
digital system generates certain frequencies (fSRC, e.g. the crystal frequency or a
microcontroller clock) and harmonics (N * fSRC) of it, which can act as interferer (EMI
source) and therefore sensitivity can be reduced.
Data Sheet
77
V1.0, 2010-02-19
TDA5225
Applications
There are two different cases, which need to be checked for the desired receive
channel(s):
Elimination of in-band EMI mixing with (2*M + 1) * fLO, where M > 0:
A square wave is used as LO (Local Oscillator) for the switching-type mixer, which also
has odd harmonics. When the harmonics of the EMI source are exactly the IF frequency
away from the harmonics of the LO, these spurs will be down-converted to the IF
frequency and act as a co-channel interferer within the receiver’s channel bandwidth
mainly in the 315 MHz band.
In this case a change of the LO injection side (high side or low side injection) can be
applied.
Example (Low Side LO-injection):
Wanted channel fRF = 314.233MHz ==> fLO = 303.533MHz ==> 3*fLO = 910.599MHz
fXOSC = 21.948717 MHz ==> 41 * fXOSC = 899.8974 MHz
Resulting IF = 910.599 - 899.8974 MHz = 10.702 MHz ==> co-channel interferer
within the receiver’s channel bandwidth ==> change LO injection side
Example (High Side LO-injection):
Wanted channel fRF = 314.233 MHz ==> fLO = 324.933 MHz ==> 3*fLO = 974.799 MHz
fXOSC = 21.948717 MHz ==> 44 * fXOSC = 965.744 MHz; 45 * fXOSC = 987.692 MHz
==> both XOSC harmonics are not generating a co-channel interferer at 10.7 MHz
A final sensitivity measurement on the application hardware is recommended.
Elimination of in-band EMI mixing with 1 * fLO:
Assuming a harmonic (N * fSRC) is falling within the BW of the wanted channel and has
an impact on the sensitivity there. In this case another XTAL frequency shall be selected,
e.g. 10 kHz away
| N * fSRC - fLocalOscillator | < BWChannel
Example (e.g. EMI source TDA5225 XOSC):
fXOSC = 21.948717 MHz ==> 42 * fXOSC = 921.846114 MHz
For further details please refer to the corresponding application note or to the latest
configuration software.
3.1
Configuration Example
Please see configuration files supplied with the Explorer tool.
Data Sheet
78
V1.0, 2010-02-19
TDA5225
Reference
4
Reference
4.1
Electrical Data
4.1.1
Absolute Maximum Ratings
Attention: The maximum ratings must not be exceeded under any circumstances,
not even momentarily and individually, as permanent damage to the IC
may result.
Table 7
#
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit Remarks
A1
Supply Voltage at VDD5V pin
Vsmax
-0.3
+6
V
A2
Supply Voltage at VDDD,
VDDA pin
Vsmax
-0.3
+4
V
A3
Voltage between VDD5V vs
VDDD and VDD5V vs VDDA
Vsmax
-0.3
+4
V
A4
Junction Temperature
Tj
-40
+125
°C
A5
Storage Temperature
Ts
-40
+150
°C
A6
Thermal resistance junction to
air
Rth(ja)
140
K/W
A7
Total power dissipation at
Tamb = 105°C
Ptot
100
mW
A8
ESD HBM integrity
VHBMRF
-2
2
KV
A9
ESD SDM integrity (All pins
except corner pins)
VSDM
-500
500
V
A10
ESD SDM integrity (All corner
pins)
VSDM
-750
750
V
A11
Latch up
ILU
100
A12
Maximum input voltage at
digital input pins
Vinmax
-0.3
A13
Maximum current into digital
input and output pins
IIOmax
Data Sheet
79
According to ESD
Standard JEDEC EIA /
JESD22-A114-B
mA
AEC-Q100 (transient
current)
VDD5V+0.5
or 6.0
V
whichever is lower
4
mA
V1.0, 2010-02-19
TDA5225
Reference
4.1.2
Operating Range
Table 8
#
Supply Operating Range and Ambient Temperature
Parameter
Symbol
Limit Values
min.
max.
Unit Remarks
B1
Supply voltage at pin VDD5V
VDD5V
4.5
5.5
V
Supply voltage range 1
B2
Supply voltage at pin
VDD5V=VDDD=VDDA
VDD3V3
3.0
3.6
V
Supply voltage range 2
B3
Ambient temperature
Tamb
-40
105
°C
Data Sheet
80
V1.0, 2010-02-19
TDA5225
Reference
4.1.3
AC/DC Characteristics
Supply voltage VDD5V = 4.5 to 5.5 Volt or VDD5V = VDDA = VDDD = 3.0 to 3.6 Volt
Ambient temperature Tamb = -40...105oC; Tamb = +25oC and VDD5V = 5.0V or VDD5V =
VDDA = VDDD = 3.3V for typical parameters, unless otherwise specified.
■ not subject to production test - verified by characterization/design
Table 9
#
AC/DC Characteristics
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
General DC Characteristics
C1.1
Supply Current
in Run Mode and
Double Down
Conversion Mode
IRun, Double
12
15
mA
ASK or FSK mode
Pin < -50dBm
C1.2
Supply Current
in Run Mode and
Single Down
Conversion Mode
IRun, Single
10.5
14
mA
ASK or FSK mode
Pin < -50dBm
C2
Supply current
in Sleep Mode
Isleep_low
crystal oscillator in Low
Power Mode;
clock generator off;
valid for SLEEP Mode
and during SPM Off time
Tamb = 25 °C
40
50
µA
Tamb = 85 °C
60
110
µA
Tamb = 105 °C
90
160
µA
115
350
µA
Tamb = 25 °C
0.8
1.5
µA
Tamb = 85 °C
3.7
13
µA
■
Tamb = 105 °C
9.0
27
µA
■
C3
Supply current
in Sleep Mode
Isleep_high
C4
Supply current
IPDN
in Power Down Mode
■
■
crystal oscillator in High
Precision Mode
Cload = 25 pF;
clock generator off;
valid for SLEEP Mode
and during SPM Off time
C5
Supply current
clock generator
Iclock
23
27
µA
fclockout = 1 kHz
Cload = 10 pF
■
C6
Supply current
IF-Buffer
IBuffer
0.5
0.7
mA
fIF_1 = 10.7 MHz
Rload = 330 Ω
no AC signal
■
Data Sheet
81
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Supply current
during RF-FE startup
/ BPF calibration
IRF-FE-
C8
Brownout detector
threshold
VBOR
2.3
C9
Receiver reset time
tReset
1.0
C10
Receiver startup
time
tRXstartup
455
C11
RF Channel Hop
Latency Time and
Configuration (Hop)
Change Latency
Time (e.g. Cfg A to
Cfg B)
tC_Hop
C12
RF Frontend startup
delay
C13
C7
Unit
Test Conditions
Remarks
max.
■
2.2
2.9
mA
2.45
2.6
V
3.0
ms
Note: No SPI
communication is allowed
before XOSC start-up is
finished and chip reset is
already finished
455
455
µs
Time to startup RF
frontend (comprises time
required to switch crystal
oscillator from Low Power
Mode to High Precision
Mode
■
111
111
111
µs
Time to switch RF PLL
between different RF
Channels (does not
include settling of Data
Clock Recovery) and time
to change Configuration
■
tRFstartdelay
350
350
350
µs
Delay of startup of RF
frontend
■
P_ON pulse width
tP_ON
15
µs
Minimal pulse width to
reset the chip
■
C14
NINT pulse length
tNINT_Pulse
µs
Pulse width of interrupt
■
C15
Accuracy of Temperature Sensor
startup,BPFcal
12
Valid for temperature
range -40°C .. +105°C;
using upper 8 ADC bits
(ADCRESH)
C15.1 uncalibrated
TError, uncal
+/- 23
°C
uncalibrated (3 sigma)
value
■
C15.2 calibrated
TError, cal
+/- 4.5
°C
after 1-point calibration at
room temperature (3
sigma)
■
C16
Accuracy of VDDD readout
C16.1 uncalibrated
Valid for temperature
range -40°C .. +105°C;
using upper 8 ADC bits
(ADCRESH)
VDDD, Error,
+/- 200
mV
uncalibrated (3 sigma)
value
■
+/- 25
mV
after 1-point calibration at
room temperature (3
sigma)
■
uncal
C16.2 calibrated
VDDD, Error,
cal
Data Sheet
82
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
1st Local Oscillator
Low Side LO-injection
and High Side LOinjection allowed;
See also Chapter 3
max.
General RF Characteristics (overall)
D1
Frequency
Range 1
fband_1
300
320
MHz
Range 2
fband_2
425
450
MHz
Range 3
fband_3
863
870
MHz
Range 4
fband_4
902
928
MHz
D2
Frequency step of
Sigma-Delta PLL
fstep
10.5
D3
ASK Demodulation
Data Rate
Rdata
0.5
40
kchip/s
■
Data rate tol.
Rdata_tol
-10
+10
%
■
Modulation index
mASK
50
100
%
ASK
■
mOOK
99
100
%
ON-OFF keying
■
Data Rate
Rdata
0.5
112
kchip/s
including tolerance
■
Data rate tol.
Rdata_tol
-10
+10
%
Frequency deviation
Δf
1
64
kHz
Modulation index
mFSK
1.0
D4
D5
Hz
fstep = fXTAL / 221
■
FSK Demodulation
■
frequency deviation
zero-peak
■
m = frequency_
deviationzero-peak /
maximum_occuring_data
_frequency;
m >= 1.25 is
recommended at small
frequency deviation
■
Decoding schemes
Manchester, differential Manchester,
Bi-phase Mark / Bi-phase Space
D6
Duty cycle ASK
Tchip/
Tdata
35
55
%
see Chapter 2.7.2
Definition C
■
Duty cycle FSK
Tchip/
Tdata
45
55
%
see Chapter 2.7.2
Definition B
■
Overall noise figure
Noise figure
Data Sheet
NF
6
83
8
dB
RF input matched to 50 Ω
@ Tamb = 25 °C
■
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
min. typ.
D7
Unit
Test Conditions
Remarks
max.
BER Sensitivity (FSK)
Manchester coding;
for additional test conditions see right after this
table
BER = 2*10-3
RF input matched to 50 Ω
@ Tamb = 25 °C;
Single-Ended Matching
without SAW;
Insertion loss of input
matching network = 1dB;
Receive Mode = TMMF
(sampled with ideal data
clock);
Double Down Conversion
D7.1
Data Rate 2 kBit/s;
Δf = 10 kHz
SFSK1BER
-119
-116
dBm
2nd IF BW = 50 kHz
PDF = 33 kHz, AFC off,
IFATT=0
■
D7.2
Data Rate 10 kBit/s;
Δf = 14 kHz
SFSK2BER
-114
-111
dBm
2nd IF BW = 50 kHz
PDF = 65 kHz, AFC off,
IFATT=0
■
D7.3
Data Rate 10 kBit/s;
Δf = 50 kHz
SFSK3BER
-112
-109
dBm
2nd IF BW = 125 kHz
PDF = 132 kHz, AFC off,
IFATT=0
■
D7.4
Data Rate 50 kBit/s;
Δf = 50 kHz
SFSK4BER
-105
-102
dBm
2nd IF BW = 300 kHz
PDF = 239 kHz, AFC off,
IFATT=0
■
D7.5
Data Rate 2 kBit/s;
Δf = 10 kHz
SFSK5BER
-110
-107
dBm
2nd IF BW = 300 kHz
PDF = 282kHz, IFATT=7
■
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
D7.6
Data Rate 10 kBit/s;
Δf = 14 kHz
SFSK6BER
-106
-103
dBm
2nd IF BW = 300 kHz
PDF = 282kHz, IFATT=7
■
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
D7.7
Data Rate 10 kBit/s;
Δf = 50 kHz
SFSK7BER
-110
-107
dBm
2nd IF BW = 300 kHz
PDF = 282kHz, IFATT=7
■
Note: 3dB sensitivity loss
@ foffset=+/-90kHz @ AFC on
Data Sheet
84
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
min. typ.
D8
Unit
Test Conditions
Remarks
max.
BER Sensitivity (OOK)
Manchester coding;
for additional test conditions see right after this
table
BER = 2*10-3
RF input matched to 50 Ω
@ Tamb = 25 °C,
peak power level (see
Chapter 2.7.3);
Single-Ended Matching
without SAW;
Insertion loss of input
matching network = 1dB;
Receive Mode = TMMF
(sampled with ideal data
clock);
Double Down Conversion
D8.1
Data Rate 0.5 kBit/s
SASK1BER
-120
-117
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
■
D8.2
Data Rate 2 kBit/s
SASK2BER
-116
-113
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
■
D8.3
Data Rate 10 kBit/s
SASK3BER
-111
-108
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 50 kHz
■
D8.4
Data Rate 16 kBit/s
SASK4BER
-109
-106
dBm
peak
m = 100%, IFATT=0
2nd IF BW = 80 kHz
■
D8.5
Data Rate 0.5 kBit/s
SASK5BER
-115
-112
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
■
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
D8.6
Data Rate 2 kBit/s
-112
SASK6BER
-109
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
■
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
D8.7
Data Rate 10 kBit/s
-106
SASK7BER
-103
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
■
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
D8.8
Data Rate 16 kBit/s
-104
SASK8BER
-101
dBm
peak
m = 100%, IFATT=7
2nd IF BW = 300 kHz;
■
Note: 3dB sensitivity loss
@ foffset = +/-100 kHz
D9.1
Sensitivity increase
for Single Down
Conversion mode
ΔSSDC
D9.2
Double Down
Conversion sensitivity
decrease for higher
blocking performance
(IFATT=0 => IFATT=7)
ΔSDDC,
Data Sheet
0
0.5
1
dB
■
1
2
dB
■
IFATT7
85
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
min. typ.
D9.3
Single Down Conversion
sensitivity decrease for
higher blocking
performance
(IFATT=4 => IFATT=7)
ΔSSDC,
0.5
Unit
Test Conditions
Remarks
max.
1
dB
■
IFATT7
D10.1 Sensitivity variation
due to temperature
(-40...+105°C)
ΔPin
2
dB
relative to Tamb = 25 °C;
temperature drift of crystal
not considered
■
D10.2 Sensitivity variation
due to frequency
offset 1)
ΔPin
3
dB
AFC inactive;
For Sensitivity Bandwidth
see Table 10
■
D10.3 Sensitivity variation
due to frequency
offset
ΔPin
3
dB
AFC active, slow AFC;
For Sensitivity Bandwidth
see Table 10 and applied
AFCLIMIT
■
D10.4 Sensitivity loss when
AFC active at center
frequency
ΔPin
1
dB
AFC active;
center frequency - no
AFC wander (see
Chapter 2.4.6.3)
■
D11
3rd order intercept
IIP3
PIIP3
-16
-14
dBm
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB;
IFATT = 7;
valid for Single and
Double Down Conversion
Mode
■
D12
1 dB compression
point CP1dB
PCP1dB
-27
-25
dBm
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB;
IFATT = 7;
valid for Single and
Double Down Conversion
Mode
■
D13
1st IF image rejection dimage1
30
40
dB
1st IF = 10.7 MHz
without front end SAW
filter;
valid for Double Down
Conversion Mode
D14
2nd IF image
rejection
30
34
dB
2nd IF = 274 kHz
without 1st IF CER filter;
valid for Single and
Double Down Conversion
Mode
Data Sheet
dimage2
86
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
RF Front End Characteristics
(Unless otherwise noted, all values apply for the specified frequency ranges)
E1
LNA input impedance
E1.1
fRF = 315 MHz
E1.2
E1.3
E1.4
E1.5
E1.6
E1.7
E1.8
fRF = 434MHz
fRF = 868MHz
fRF = 915MHz
fRF = 315 MHz
fRF = 434MHz
fRF = 868MHz
fRF = 915MHz
Rin_p,diff
680
Ω
Cin_p,diff
1.05
pF
Rin_p,diff
570
Ω
■
Cin_p,diff
0.87
pF
■
Rin_p,diff
550
Ω
■
Cin_p,diff
0.63
pF
■
Rin_p,diff
540
Ω
■
Cin_p,diff
0.63
pF
■
Rin_p, SE
500
Ω
Cin_p, SE
1.87
pF
Rin_p, SE
400
Ω
Cin_p, SE
1.63
pF
■
Rin_p, SE
322
Ω
■
Cin_p, SE
1.59
pF
■
Rin_p, SE
312
Ω
■
Cin_p, SE
1.56
pF
■
differential parallel
equivalent input between
LNA_INP and LNA_INN
single-ended parallel
equivalent input between
LNA_INP and GNDRF /
LNA_INN and GNDRF
E2
FE output
impedance
Rout_IF
290
330
380
Ω
fIF = 10.7 MHz
E3
FE voltage
conversion gain
AVFE, max
34
36
38
dB
min. IF attenuation
(IFATT = 0);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
Rload_IF = 330 Ω;
tested at 434 MHz
E4
FE voltage
conversion gain
AVFE_7
29
31
33
dB
IF attenuation
(IFATT = 7);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
Rload_IF = 330 Ω;
tested at 434 MHz
Data Sheet
87
■
■
■
■
■
■
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
E5
FE voltage
conversion gain
E6
FE voltage
conversion gain step
Symbol
AVFE, min
Limit Values
min. typ.
max.
22
26
24
0.8
Unit
Test Conditions
Remarks
dB
max. IF attenuation
(IFATT = 15);
input matched to 50 Ω;
Insertion loss of input
matching network = 1dB
Rload_IF = 330 Ω;
tested at 434 MHz
dB
12dB / 15 = 0.8dB/step
■
Double Down
Conversion: 16 gain
settings (4 bit)
Single Down Conversion:
7 gain settings
E7
1st Local Oscillator SSB Noise
E7.1
PLL loop Bandwidth
BW
E7.2
fin_R1 = 315MHz
dSSB_LO
E7.3
E7.4
E7.5
fin_R2 = 434MHz
fin_R3 = 868MHz
fin_R4 = 915MHz
dSSB_LO
dSSB_LO
dSSB_LO
closed loop
100
150
200
kHz
BW and its tolerances
■
-81
-76
dBc/Hz
@ foffset = 1 kHz
■
-85
-80
@ foffset = 10 kHz
■
-82
-77
@ foffset = 100 kHz
■
-120
-115
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
-78
-73
@ foffset = 1 kHz
■
-83
-78
@ foffset = 10 kHz
■
-82
-77
@ foffset = 100 kHz
■
-117
-112
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
-75
-70
@ foffset = 1 kHz
■
-79
-74
@ foffset = 10 kHz
■
-77
-72
@ foffset = 100 kHz
■
-114
-109
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
-71
-66
@ foffset = 1 kHz
■
-79
-74
@ foffset = 10 kHz
■
-77
-72
@ foffset = 100 kHz
■
-116
-111
@ foffset = 1 MHz
■
-130
-125
@ foffset => 10 MHz
■
dBc/Hz
dBc/Hz
dBc/Hz
E8.1
Spurious emission < 1 GHz
-57
dBm
■
E8.2
Spurious emission > 1 GHz
-47
dBm
■
Data Sheet
88
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
min. typ.
E9
Inband fractional spur
E10
3dB Overall Analog
Frontend Bandwidth
Test Conditions
Remarks
max.
-40
■
dBc
230
BWANA
Unit
kHz
LNA input to Limiter
output, excluding external
CER filter
■
1st IF Buffer Characteristics
F1
Input impedance
Rin_IF
290
330
370
Ω
fIF = 10...12 MHz
■
F2
Output impedance
Rout_IF
290
330
370
Ω
fIF = 10...12 MHz
■
F3
Voltage gain
AVBuffer
3
4
5
dB
fIF = 10...12 MHz
Zsource = 330 Ω
Zload = 330 Ω
F4
Buffer switch
disolation
isolation (CERFSEL)
dB
fIF = 10...12 MHz
see Figure 6
■
Ω
fIF = 10...12 MHz
■
60
2nd IF Mixer, RSSI and Filter Characteristics
G1
Mixer input
impedance
G6
RSSI
G2.1
Dynamic range
(Linearity +/- 2 dB)
Rin_IF
290
330
390
Related to RF input
matched to 50 Ω
DRRSSI
-110
-30
dBm
applies for digital RSSI;
AGC on
■
-115
-60
dBm
applies for analog RSSI
@ 50kHz BPF, AFGC off
■
-110
-50
dBm
applies for analog RSSI
■
@ 300kHz BPF, AFGC off
G2.2
Linearity
DRLIN
-1
+1
dB
-95 dBm...-35 dBm;
applies for digital RSSI
■
G2.3
Temperature drift
within linear dynamic
range
DRTEMP
-2.5
+1.5
dB
-95 dBm...-35 dBm;
applies for digital RSSI
■
G2.4
Output dynamic
range
VRSSI+
0.8
2.0
V
G2.5
analog RSSI error,
untrimmed
DRSSIana
-4
+2
dB
at RSSI pin
G2.6
analog RSSI slope,
untrimmed
dVRSSI/
dVmix_in
8
12
mV/dB
at RSSI pin;
typical 600 mV/60 dB =
10 mV/dB
G2.7
digital RSSI error,
untrimmed
DRSSIdig_u -4
+2
dB
RSSI register readout
Data Sheet
10
89
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
Unit
Test Conditions
Remarks
min. typ.
max.
+1
dB
RSSI register readout
G2.8
digital RSSI error,
user trimmed via
SFRs RSSISLOPE
and RSSIOFFS
DRSSIdig_t
-1
G2.9
digital RSSI slope,
untrimmed
dVRSSI/
dVmix_in
2
2.5
3
LSB
/dB
RSSI register readout;
typical 600 mV/60 dB =
10 mV/dB,
1mV = 1 LSB (10-bit ADC)
8-bit readout: 4mV=1LSB
G2.10 digital RSSI slope,
user trimmed via
SFRs RSSISLOPE
and RSSIOFFS
dVRSSI/
dVmix_in
2.35
2.5
2.65
LSB
/dB
RSSI register readout;
typical 600 mV/60 dB =
10 mV/dB,
1mV = 1 LSB (10-bit ADC)
8-bit readout: 4mV=1LSB
G2.11 Resistive load at
RSSI pin
RL,RSSImax
100
G2.12 Capacitive load at
RSSI pin
CL,RSSI
■
■
kΩ
■
20
pF
■
288
kHz
G3
2nd IF Filter (3rd order Bandpass Filter)
G3.1
Center frequency
fcenter
G3.2
-3 dB BW
BW-3dB
G3.3
-3 dB BW tolerance
tol_BW-3dB -5
+5
%
For BW = 125, 200, 300
kHz
■
G3.4
-3 dB BW tolerance
tol_BW-3dB -6
+6
%
For BW = 50, 80 kHz
■
Data Sheet
262
274
■
kHz
50
80
125
200
300
90
Asymmetric BPF corners:
f_center=sqrt(flow * fhigh);
Use AFC for more
symmetry
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Crystal Oscillator Characteristics
H1
Frequency range
fXTAL
H2
Crystal parameters
H2.1
Motional
capacitance
C1
H2.2
Motional resistance
H2.3
MHz
21.948
717
6
10
fF
■
R1
18
80
Ω
■
Shunt capacitance
C0
2
4
pF
■
H2.4
Load capacitance
CLoad
12
H2.5
Initial frequency
tolerance
fXTAL_Tol
-30
H2.6
Frequency trimming
range
ΔfXTAL
-50
H2.7
Trimming step
ΔfX_step
H3
Clock output
fclock_out
frequency at PPx pin
H4
Crystal oscillator
settling time
(switching from Low
Power to High
Precision Mode)
tCOSCsettle
H5
Start up time
tstart_up
Data Sheet
3
pF
nominal value
■
+30
ppm
oscillator untrimmed (trim
capacitor default settings,
usage of recommended
crystal);
not including crystal
tolerances
■
+50
ppm
larger trimming range
possible via SD PLL
4
ppm
see also step size of
SD PLL
5.5M
Hz
10pF load
292
292
µs
0.45
1
ms
1
11
292
91
■
■
crystal type:
NDK NX5032SD;
See also BOM for ext.
load caps;
Note: No SPI
communication is allowed
before XOSC start-up is
finished and chip reset is
already finished
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
max.
Digital Inputs/Outputs Characteristics
I1
High level input
voltage
VIn_High
I2
High level input
leakage current
IIn_High
I3
Low level input
voltage (except
P_ON pin)
VIn_Low
I4
0.7*
VDDD
VDD5V V
+0.1
5
µA
0
0.8
V
Low level input
voltage (at P_ON
pin)
VIn_Low_PON 0
0.5
V
I5
Low level input
leakage current
IIn_Low
-5
I6
High level output
voltage 1
VOut_High1
VDD5V
-0.4
VDD5V V
IOH=-500 µA, static driver
capability;
Normal Pad Mode
(see register PPCFG2
and CMC0)
I7
Low level output
voltage 1
VOut_Low1
0
0.4
IOL=500 µA, static driver
capability;
Normal Pad Mode
(see register PPCFG2
and CMC0)
I8
High level output
voltage 2
VOut_High2
VDD5V
-0.8
VDD5V V
IOH=-4 mA, static driver
capability;
High Power Pad Mode
(see register PPCFG2
and CMC0)
I9
Low level output
voltage 2
VOut_Low2
0
0.8
IOL=4 mA, static driver
capability;
High Power Pad Mode
(see register PPCFG2
and CMC0)
Data Sheet
µA
92
V
V
V1.0, 2010-02-19
TDA5225
Reference
#
Parameter
Symbol
Limit Values
min. typ.
Unit
Test Conditions
Remarks
MHz
Note: A high SPI clock
rate during data reception
can reduce sensitivity
max.
Timing SPI-Bus Characteristics
J1
Clock frequency
fclock
2.2
J2
Clock High time
tCLK_H
200
ns
■
J3
Clock Low time
tCLK_L
200
ns
■
J4
Active setup time
tsetup
200
ns
■
J5
Not active setup time tnot_setup
200
ns
■
J6
Active hold time
thold
200
ns
■
J7
Not active hold time
tnot_hold
200
ns
■
J8
Deselect time
tDeselect
200
ns
■
J9
SDI setup time
tSDI_setup
100
ns
■
J10
SDI hold time
tSDI_hold
100
ns
■
J11
Clock low to SDO
valid
tCLK_SDO
145
ns
@ Cload = 80 pF
High Power Pad not
enabled (Normal Mode)
(see register PPCFG2
and CMC0)
J12
Clock low to SDO
valid
tCLK_SDO
40
ns
@ Cload = 10 pF
High Power Pad not
enabled (Normal Mode)
(see register PPCFG2
and CMC0)
J13
SDO rise time
tSDO_r
90
ns
@ Cload = 80 pF
■
J14
SDO fall time
tSDO_f
90
ns
@ Cload = 80 pF
■
J15
SDO rise time
tSDO_r
15
ns
@ Cload = 10 pF
■
J16
SDO fall time
tSDO_f
15
ns
@ Cload = 10 pF
■
J17
SDO disable time
tSDO_disable
25
ns
■
■
1) Please note that the system bandwidth is smaller than the smallest bandwidth in the signal path.
Data Sheet
93
V1.0, 2010-02-19
TDA5225
Reference
Unless explicitly otherwise noted, the following test conditions apply to the given
specification values in the items D7 and D8:
* Hardware: TDA5240 Platform Testboard V1.0
* Single-Ended Matching for 315.0 MHz / 433.92 MHz / 868.3 MHz / 915.0 MHz
* RF input matched to 50 Ω; Insertion loss of input matching network = 1dB
* Receive Frequency 315.0 MHz / 433.92 MHz / 868.3 MHz / 915.0 MHz; Lo-Side LO-Injection
* Reference Clock: XTAL=21.948717 MHz
* IF-Gain: Attenuation set to default value (IFATT = 7)
* Double Down Conversion
* 1 IF-Filter: Center=10.7MHz; BW=330kHz; Connected between IF_OUT and IFBUF_IN
* 2nd IF Filter BW: Depending on Data Rate and FSK Deviation
* Received Signal at zero Offset to IF Center Frequency
* RSSI trimmed
* FSK Pre-Demodulation Filter (PDF) BW: Depending on Data Rate and FSK Deviation
* No SPI-traffic during telegram reception, CLK_OUT disabled
* AFC and AGC are OFF, unless otherwise noted
BER sensitivity measurements use Receive Mode TMMF (sampled with ideal data clock)
* DRE ... Data Date Error of received telegram vs. adjusted Data Rate
* DC ... Duty Cycle
* BER ... Bit Error Rate (using a PRBS9 Pseudo-Random Binary Sequence)
[BER = 1 - (number_of_correctly_received_bits / number_of_transmitted bits)]
Data Sheet
94
V1.0, 2010-02-19
TDA5225
Reference
Table 10
Typical Achievable Sensitivity Bandwidth [kHz]
Ceramic Filter BW = 330 kHz
Table is valid for DDC (Double Down Conversion) and SDC (Single Down Conversion)
Valid for AFC=off; For FSK & AFC=on the BW can be increased by 2*AFCLIMIT, where AFCLIMIT < 43 kHz
BPF/PDF
Filter [Hz]
BPF = 300 k
PDF = 282 k
Modulation FSK Deviation
[+/- Hz]
ASK
FSK
-
0.5 k
1k
5k
10 k
15 k
20 k
40 k
50 k
Data Sheet
Sensitivity
Loss
Data Rate [bit/s], Manchester
0.5 k
1k
5
10 k
20 k
50 k
3 dB
230
230
230
230
230
-
6 dB
280
280
280
280
280
-
3 dB
160
150
-
-
-
-
6 dB
230
220
-
-
-
-
3 dB
140
160
-
-
-
-
6 dB
220
230
-
-
-
-
3 dB
120
130
150
140
-
-
6 dB
200
210
220
220
-
-
3 dB
120
120
140
140
150
-
6 dB
180
190
210
210
210
-
3 dB
-
-
130
140
150
-
6 dB
-
-
200
200
210
-
3 dB
110
-
130
130
140
-
6 dB
160
-
190
190
190
-
3 dB
-
-
-
120
-
-
6 dB
-
-
-
160
-
-
3 dB
110
110
110
110
100
100
6 dB
140
140
140
140
140
140
95
V1.0, 2010-02-19
TDA5225
Reference
Table 10
Typical Achievable Sensitivity Bandwidth [kHz]
Ceramic Filter BW = 330 kHz
Table is valid for DDC (Double Down Conversion) and SDC (Single Down Conversion)
Valid for AFC=off; For FSK & AFC=on the BW can be increased by 2*AFCLIMIT, where AFCLIMIT < 43 kHz
BPF/PDF
Filter [Hz]
BPF = 200 k
PDF = 239 k
Modulation FSK Deviation
[+/- Hz]
ASK
FSK
-
0.5 k
1k
5k
10 k
15 k
20 k
40 k
50 k
Data Sheet
Sensitivity
Loss
Data Rate [bit/s], Manchester
0.5 k
1k
5
10 k
20 k
50 k
3 dB
180
180
180
180
180
-
6 dB
220
220
220
220
220
-
3 dB
140
140
-
-
-
-
6 dB
190
190
-
-
-
-
3 dB
130
130
-
-
-
-
6 dB
180
190
-
-
-
-
3 dB
100
120
130
130
-
-
6 dB
160
170
180
180
-
-
3 dB
100
100
120
120
140
-
6 dB
140
150
170
170
170
-
3 dB
-
-
110
110
120
-
6 dB
-
-
150
150
160
-
3 dB
90
-
100
100
110
-
6 dB
130
-
140
150
150
-
3 dB
-
-
-
90
-
-
6 dB
-
-
-
120
-
-
3 dB
-
-
-
-
-
-
6 dB
-
-
-
-
-
-
96
V1.0, 2010-02-19
TDA5225
Reference
Table 10
Typical Achievable Sensitivity Bandwidth [kHz]
Ceramic Filter BW = 330 kHz
Table is valid for DDC (Double Down Conversion) and SDC (Single Down Conversion)
Valid for AFC=off; For FSK & AFC=on the BW can be increased by 2*AFCLIMIT, where AFCLIMIT < 43 kHz
BPF/PDF
Filter [Hz]
BPF = 125 k
PDF = 132 k
Modulation FSK Deviation
[+/- Hz]
ASK
FSK
-
0.5 k
1k
5k
10 k
15 k
20 k
40 k
50 k
Data Sheet
Sensitivity
Loss
Data Rate [bit/s], Manchester
0.5 k
1k
5
10 k
20 k
50 k
3 dB
120
120
120
120
120
-
6 dB
150
150
150
150
150
-
3 dB
100
100
-
-
-
-
6 dB
120
120
-
-
-
-
3 dB
90
100
-
-
-
-
6 dB
120
120
-
-
-
-
3 dB
70
80
80
90
-
-
6 dB
100
110
110
110
-
-
3 dB
70
70
80
80
80
-
6 dB
90
100
100
100
100
-
3 dB
-
-
70
80
80
-
6 dB
-
-
90
90
100
-
3 dB
60
-
70
70
70
-
6 dB
80
-
90
90
90
-
3 dB
-
-
-
-
-
-
6 dB
-
-
-
-
-
-
3 dB
-
-
-
-
-
-
6 dB
-
-
-
-
-
-
97
V1.0, 2010-02-19
TDA5225
Reference
4.2
Figure 54
Data Sheet
Test Circuit - Evaluation Board v1.0
Test Circuit Schematic
98
V1.0, 2010-02-19
TDA5225
Reference
4.3
Test Board Layout - Evaluation Board v1.0
Figure 55
Test Board Layout, Top View
Figure 56
Test Board Layout, Bottom View
Data Sheet
99
V1.0, 2010-02-19
TDA5225
Reference
Figure 57
Data Sheet
Test Board Layout, Component View
100
V1.0, 2010-02-19
TDA5225
Reference
4.4
Bill of Materials
Pos
Part
Value
1
IC1
TDA5225
PG-TSSOP-28
2
C1
3.9 pF
0603
C0G
+/- 0.1 pF
crystal oscillator load
3
C2
3.9 pF
0603
C0G
+/- 0.1 pF
crystal oscillator load
4
C3
100 nF
0603
X7R
+/- 10 %
5
C4
100 nF
0603
X7R
+/- 10 %
6
C5
100 nF /
( 1 µF )
0603
X7R /
X5R
+/- 10 %
7
C6
100 nF
0603
X7R
+/- 10 %
8
C7
1 pF
0603
C0G
+/- 0.1 pF
matching for 315MHz
0.5 pF
0603
C0G
+/- 0.1 pF
matching for 434MHz
open
0603
C0G
1 pF
0603
C0G
open
0603
C0G
matching for 315MHz
open
0603
C0G
matching for 434MHz
2.7 pF
0603
C0G
+/- 0.1 pF
matching for 868MHz
5.1 pF
0603
C0G
+/- 0.1 pF
matching for 915MHz
polarized capacitor
9
C8
Package
Device /
Type
Tolerance
Manufacturer
Remark/Options
(RF+supply variant)
Infineon
3.3V /
( 5 V environment)
matching for 868MHz
+/- 0.1 pF
matching for 915MHz
10
C9
1 µF
SMC-A
Tantal
+/- 10%
11
C10
100 nF
0603
X7R
+/- 10%
12
C11
10 nF
0603
X7R
+/- 10%
13
L1
68 nH
0603
+/- 2%
matching for 315MHz
39 nH
0603
+/- 2%
matching for 434MHz
22 nH
0603
+/- 2%
matching for 868MHz
15 nH
0603
+/- 2%
matching for 915MHz
14
R1
10 Ohm /
(open)
0603
+/- 5%
3.3 V /
( 5 V environment)
15
R2
4.7 Ohm /
(open)
0603
+/- 5%
3.3 V /
( 5 V environment)
16
R3
4.7 Ohm /
(22 Ohm)
0603
+/- 5%
3.3 V /
( 5 V environment)
17
R4
0 Ohm
0603
18
IF1
SFECF10
M7EA00
19
Q1
21.948717 NX5032SD
MHz
Data Sheet
C0=1.7 pF
C1=7 fF
CL=12 pF
101
Murata
BW = 330 kHz
NDK (Frischer
Electronic),
EXS00ACS01580
SMD crystal
V1.0, 2010-02-19
TDA5225
Reference
Pos
Part
Value
Package
Device /
Type
Tolerance
Manufacturer
Remark/Options
(RF+supply variant)
Interface / optional
20
IC2
AT24C32 SOIC8
C-SH-B or
AT24C512
EEPROM for board
detection
21
C12
open
0603
X7R
+/- 10%
22
C13
100 nF
0603
X7R
+/- 10%
23
C14
1 µF
SMC-A
Tantal
+/- 10%
polarized capacitor
24
C15
10 nF
0603
X7R
+/- 10%
filter network on
supply line
25
C16
10 nF
0603
X7R
+/- 10%
filter network on
supply line
26
L2
0 Ohm
0603
no filter network on
supply line
27
R5
open
0603
RSSI measurement
low pass
28
R6
1 kOhm
0603
29
R7
0 Ohm
0603
30
D1
LED
31
IF2
open
32
X1
SMA
socket
RF input
33
X2
3 pins
Board supply
34
X3
2 pins
Chip supply current
(jumper closed)
35
X4
50 pins
36
X5
2 pins
RSSI measuring
point
37
X6
12 pins
Interface line
measuring point
38
X7
4 pins
GND
39
X8
4 pins
GND
40
Jumper 1
2 pins
Jumper for X3
41
Jumper 2
2 pins
Jumper for X2 Supply by interface
RSSI measurement
low pass
write protection for
EEPROM
LS M676P251-1
status indication LED
Murata
SIB-QTS-02501-X-D-RA
Samtec
2nd IF filter is
optional
Connector to
PC/µC/Interface
Board material 1.5mm FR4 with 35µm copper on both sides
Data Sheet
102
V1.0, 2010-02-19
TDA5225
Package Outlines
Package Outlines
0˚...8˚
B
-0.035
1.2 MAX.
1 +0.05
-0.2
0.1 ±0.05
4.4 ±0.1 1)
0.125 +0.075
5
0.65
0.22 +0.08
-0.03
C
2)
0.1
0.6 +0.15
-0.1
0.1 M A C 28x
28
6.4
15
1
0.2 B 28x
14
9.7 ±0.1 1)
A
Index Marking
1)
2)
Does not include plastic or metal protrusion of 0.15 max. per side
Does not include dambar protrusion
Figure 58
PG-TSSOP-28 Package Outline (green package)
Table 11
Order Information
Type
TDA5225
Ordering Code
Package
SP000507672
PG-TSSOP-28
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”:http://www.infineon.com/products
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
103
V1.0, 2010-02-19
TDA5225
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Data Sheet
Page
Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AGC Settings 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AGC Settings 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SPI Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Supply Operating Range and Ambient Temperature . . . . . . . . . . . . . . 80
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Typical Achievable Sensitivity Bandwidth [kHz] . . . . . . . . . . . . . . . . . . 95
Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
104
V1.0, 2010-02-19
TDA5225
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Data Sheet
Page
Pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TDA5225 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Diagram RF Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Single Down Conversion (SDC, no external filters required) . . . . . . . . 19
Double Down Conversion (DDC) with one external filter . . . . . . . . . . . 20
Double Down Conversion (DDC) with two external filters . . . . . . . . . . 20
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
External Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Synthesizer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Functional Block Diagram ASK/FSK Demodulator . . . . . . . . . . . . . . . 26
AFC Loop Filter (I-PI Filtering and Mapping) . . . . . . . . . . . . . . . . . . . . 28
Analog RSSI output curve with AGC action ON (blue) vs. OFF (black) 29
Peak Detector Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Peak Detector Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Functional Block Diagram Digital Baseband Receiver. . . . . . . . . . . . . 36
Wake-Up Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RSSI Blocking Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3 Volts and 5 Volts Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Supply Current Ramp Up/Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Logical and electrical System Interfaces of the TDA5225 . . . . . . . . . . 44
Data interface for the Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . 46
External Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interrupt Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupt Generation Waveform (Example for Configuration A+B). . . . 49
ISx Readout Set Clear Collision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Burst Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Burst Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SPI Checksum Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chip Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Global State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Run Mode Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
HOLD State Behavior (INITPLLHOLD disabled) . . . . . . . . . . . . . . . . . 59
HOLD State Behavior (INITPLLHOLD enabled) . . . . . . . . . . . . . . . . . 60
SPM - TX-RX Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Wake-up Search with Configuration A . . . . . . . . . . . . . . . . . . . . . . . . . 62
Wake-up Search with Configuration B, C, D . . . . . . . . . . . . . . . . . . . . 63
105
V1.0, 2010-02-19
TDA5225
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Data Sheet
Run Mode Self Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Polling Timer Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Constant On-Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
COO Polling in WU on RSSI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Active Idle Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Definition A: Level-based definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Definition B: Chip-based definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Definition C: Edge delay definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SFR Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SFR Address Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Test Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Test Board Layout, Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Test Board Layout, Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Test Board Layout, Component View . . . . . . . . . . . . . . . . . . . . . . . . 100
PG-TSSOP-28 Package Outline (green package). . . . . . . . . . . . . . . 103
106
V1.0, 2010-02-19
TDA5225
Appendix - Registers Chapter
Data Sheet
107
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Appendix - Registers Chapter
Register Overview
Table 1
Register Overview
Register Short Name
Register Long Name
Offset Address
Page Number
Appendix - Registers Chapter, Register Description
A_IF1
IF1 Register
016H
122
A_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 01BH
122
A_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
01CH
123
A_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
01DH
123
A_WURSSITH2
RSSI Wake-Up Threshold for Channel 2 Register 01EH
124
A_WURSSIBL2
RSSI Wake-Up Blocking Level Low Channel 2
Register
01FH
124
A_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
020H
124
A_WURSSITH3
RSSI Wake-Up Threshold for Channel 3 Register 021H
125
A_WURSSIBL3
RSSI Wake-Up Blocking Level Low Channel 3
Register
022H
125
A_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
023H
126
A_WULOT
Wake-up on Level Observation Time Register
025H
126
A_AFCLIMIT
AFC Limit Configuration Register
02AH
127
A_AFCAGCD
AFC/AGC Freeze Delay Register
02BH
127
A_AFCSFCFG
AFC Start/Freeze Configuration Register
02CH
128
A_AFCK1CFG0
AFC Integrator 1 Gain Register 0
02DH
129
A_AFCK1CFG1
AFC Integrator 1 Gain Register 1
02EH
129
A_AFCK2CFG0
AFC Integrator 2 Gain Register 0
02FH
129
A_AFCK2CFG1
AFC Integrator 2 Gain Register 1
030H
130
A_PMFUDSF
Peak Memory Filter Up-Down Factor Register
031H
130
A_AGCSFCFG
AGC Start/Freeze Configuration Register
032H
131
A_AGCCFG0
AGC Configuration Register 0
033H
132
A_AGCCFG1
AGC Configuration Register 1
034H
133
A_AGCTHR
AGC Threshold Register
035H
133
A_DIGRXC
Digital Receiver Configuration Register
036H
134
A_ISUPFCSEL
Image Supression Fc Selection Register
038H
134
A_PDECF
Pre Decimation Factor Register
039H
135
A_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
03AH
135
A_PDECSCASK
Pre Decimation Scaling Register ASK Mode
03BH
136
Data Sheet
108
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
A_MFC
Matched Filter Control Register
03CH
136
A_SRC
Sampe Rate Converter NCO Tune
03DH
137
A_EXTSLC
Externel Data Slicer Configuration
03EH
137
A_CHCFG
Channel Configuration Register
058H
138
A_PLLINTC1
PLL MMD Integer Value Register Channel 1
059H
139
A_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 05AH
139
A_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 05BH
140
A_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 05CH
140
A_PLLINTC2
PLL MMD Integer Value Register Channel 2
05DH
141
A_PLLFRAC0C2
PLL Fractional Division Ratio Register 0 Channel 2 05EH
141
A_PLLFRAC1C2
PLL Fractional Division Ratio Register 1 Channel 2 05FH
142
A_PLLFRAC2C2
PLL Fractional Division Ratio Register 2 Channel 2 060H
142
A_PLLINTC3
PLL MMD Integer Value Register Channel 3
061H
143
A_PLLFRAC0C3
PLL Fractional Division Ratio Register 0 Channel 3 062H
143
A_PLLFRAC1C3
PLL Fractional Division Ratio Register 1 Channel 3 063H
143
A_PLLFRAC2C3
PLL Fractional Division Ratio Register 2 Channel 3 064H
144
SFRPAGE
Special Function Register Page Register
080H
144
PPCFG0
PP0 and PP1 Configuration Register
081H
145
PPCFG1
PP2 and PP3 Configuration Register
082H
146
PPCFG2
PPx Port Configuration Register
083H
147
RXRUNCFG0
RX RUN Configuration Register 0
084H
148
RXRUNCFG1
RX RUN Configuration Register 1
085H
149
CLKOUT0
Clock Divider Register 0
086H
150
CLKOUT1
Clock Divider Register 1
087H
150
CLKOUT2
Clock Divider Register 2
088H
151
RFC
RF Control Register
089H
151
BPFCALCFG0
BPF Calibration Configuration Register 0
08AH
152
BPFCALCFG1
BPF Calibration Configuration Register 1
08BH
152
XTALCAL0
XTAL Coarse Calibration Register
08CH
153
XTALCAL1
XTAL Fine Calibration Register
08DH
153
RSSIMONC
RSSI Monitor Configuration Register
08EH
154
ADCINSEL
ADC Input Selection Register
08FH
155
RSSIOFFS
RSSI Offset Register
090H
155
RSSISLOPE
RSSI Slope Register
091H
156
IM0
Interrupt Mask Register 0
094H
156
IM1
Interrupt Mask Register 1
095H
157
SPMAP
Self Polling Mode Active Periods Register
096H
157
SPMIP
Self Polling Mode Idle Periods Register
097H
158
Data Sheet
109
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
SPMC
Self Polling Mode Control Register
098H
158
SPMRT
Self Polling Mode Reference Timer Register
099H
159
SPMOFFT0
Self Polling Mode Off Time Register 0
09AH
159
SPMOFFT1
Self Polling Mode Off Time Register 1
09BH
160
SPMONTA0
Self Polling Mode On Time Config A Register 0
09CH
160
SPMONTA1
Self Polling Mode On Time Config A Register 1
09DH
161
SPMONTB0
Self Polling Mode On Time Config B Register 0
09EH
161
SPMONTB1
Self Polling Mode On Time Config B Register 1
09FH
162
SPMONTC0
Self Polling Mode On Time Config C Register 0
0A0H
162
SPMONTC1
Self Polling Mode On Time Config C Register 1
0A1H
163
SPMONTD0
Self Polling Mode On Time Config D Register 0
0A2H
163
SPMONTD1
Self Polling Mode On Time Config D Register 1
0A3H
164
EXTPCMD
External Processing Command Register
0A4H
164
CMC1
Chip Mode Control Register 1
0A5H
165
CMC0
Chip Mode Control Register 0
0A6H
166
RSSIPWU
Wakeup Peak Detector Readout Register
0A7H
167
IS0
Interrupt Status Register 0
0A8H
167
IS1
Interrupt Status Register 1
0A9H
168
RFPLLACC
RF PLL Actual Channel and Configuration
Register
0AAH
169
RSSIPRX
RSSI Peak Detector Readout Register
0ABH
169
ADCRESH
ADC Result High Byte Register
0AEH
170
ADCRESL
ADC Result Low Byte Register
0AFH
170
VACRES
VCO Autocalibration Result Readout Register
0B0H
171
AFCOFFSET
AFC Offset Read Register
0B1H
171
AGCGAINR
AGC Gain Readout Register
0B2H
172
SPIAT
SPI Address Tracer Register
0B3H
172
SPIDT
SPI Data Tracer Register
0B4H
172
SPICHKSUM
SPI Checksum Register
0B5H
173
SN0
Serial Number Register 0
0B6H
173
SN1
Serial Number Register 1
0B7H
174
SN2
Serial Number Register 2
0B8H
174
SN3
Serial Number Register 3
0B9H
174
RSSIRX
RSSI Readout Register
0BAH
175
RSSIPMF
RSSI Peak Memory Filter Readout Register
0BBH
175
B_IF1
IF1 Register
116H
B_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 11BH
B_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
Data Sheet
110
11CH
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
B_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
11DH
B_WURSSITH2
RSSI Wake-Up Threshold for Channel 2 Register 11EH
B_WURSSIBL2
RSSI Wake-Up Blocking Level Low Channel 2
Register
11FH
B_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
120H
B_WURSSITH3
RSSI Wake-Up Threshold for Channel 3 Register 121H
B_WURSSIBL3
RSSI Wake-Up Blocking Level Low Channel 3
Register
122H
B_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
123H
B_WULOT
Wake-Up on Level Observation Time Register
125H
B_AFCLIMIT
AFC Limit Configuration Register
12AH
B_AFCAGCD
AFC/AGC Freeze Delay Register
12BH
B_AFCSFCFG
AFC Start/Freeze Configuration Register
12CH
B_AFCK1CFG0
AFC Integrator 1 Gain Register 0
12DH
B_AFCK1CFG1
AFC Integrator 1 Gain Register 1
12EH
B_AFCK2CFG0
AFC Integrator 2 Gain Register 0
12FH
B_AFCK2CFG1
AFC Integrator 2 Gain Register 1
130H
B_PMFUDSF
Peak Memory Filter Up-Down Factor Register
131H
B_AGCSFCFG
AGC Start/Freeze Configuration Register
132H
B_AGCCFG0
AGC Configuration Register 0
133H
B_AGCCFG1
AGC Configuration Register 1
134H
B_AGCTHR
AGC Threshold Register
135H
B_DIGRXC
Digital Receiver Configuration Register
136H
B_ISUPFCSEL
Image Supression Fc Selection Register
138H
B_PDECF
Pre Decimation Factor Register
139H
B_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
13AH
B_PDECSCASK
Pre Decimation Scaling Register ASK Mode
13BH
B_MFC
Matched Filter Control Register
13CH
B_SRC
Sampe Rate Converter NCO Tune
13DH
B_EXTSLC
Externel Data Slicer Configuration
13EH
B_CHCFG
Channel Configuration Register
158H
B_PLLINTC1
PLL MMD Integer Value Register Channel 1
159H
B_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 15AH
B_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 15BH
B_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 15CH
B_PLLINTC2
PLL MMD Integer Value Register Channel 2
Data Sheet
111
Page Number
15DH
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
B_PLLFRAC0C2
PLL Fractional Division Ratio Register 0 Channel 2 15EH
B_PLLFRAC1C2
PLL Fractional Division Ratio Register 1 Channel 2 15FH
B_PLLFRAC2C2
PLL Fractional Division Ratio Register 2 Channel 2 160H
B_PLLINTC3
PLL MMD Integer Value Register Channel 3
B_PLLFRAC0C3
PLL Fractional Division Ratio Register 0 Channel 3 162H
B_PLLFRAC1C3
PLL Fractional Division Ratio Register 1 Channel 3 163H
B_PLLFRAC2C3
PLL Fractional Division Ratio Register 2 Channel 3 164H
C_IF1
IF1 Register
C_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 21BH
C_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
21CH
C_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
21DH
C_WURSSITH2
RSSI Wake-Up Threshold for Channel 2 Register 21EH
C_WURSSIBL2
RSSI Wake-Up Blocking Level Low Channel 2
Register
21FH
C_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
220H
C_WURSSITH3
RSSI Wake-Up Threshold for Channel 3 Register 221H
C_WURSSIBL3
RSSI Wake-Up Blocking Level Low Channel 3
Register
222H
C_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
223H
C_WULOT
Wake-Up on Level Observation Time Register
225H
C_AFCLIMIT
AFC Limit Configuration Register
22AH
C_AFCAGCD
AFC/AGC Freeze Delay Register
22BH
C_AFCSFCFG
AFC Start/Freeze Configuration Register
22CH
C_AFCK1CFG0
AFC Integrator 1 Gain Register 0
22DH
C_AFCK1CFG1
AFC Integrator 1 Gain Register 1
22EH
C_AFCK2CFG0
AFC Integrator 2 Gain Register 0
22FH
C_AFCK2CFG1
AFC Integrator 2 Gain Register 1
230H
C_PMFUDSF
Peak Memory Filter Up-Down Factor Register
231H
C_AGCSFCFG
AGC Start/Freeze Configuration Register
232H
C_AGCCFG0
AGC Configuration Register 0
233H
C_AGCCFG1
AGC Configuration Register 1
234H
C_AGCTHR
AGC Threshold Register
235H
C_DIGRXC
Digital Receiver Configuration Register
236H
C_ISUPFCSEL
Image Supression Fc Selection Register
238H
C_PDECF
Pre Decimation Factor Register
239H
C_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
23AH
Data Sheet
Offset Address
Page Number
161H
216H
112
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
C_PDECSCASK
Pre Decimation Scaling Register ASK Mode
23BH
C_MFC
Matched Filter Control Register
23CH
C_SRC
Sampe Rate Converter NCO Tune
23DH
C_EXTSLC
Externel Data Slicer Configuration
23EH
C_CHCFG
Channel Configuration Register
258H
C_PLLINTC1
PLL MMD Integer Value Register Channel 1
259H
C_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 25AH
C_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 25BH
C_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 25CH
C_PLLINTC2
PLL MMD Integer Value Register Channel 2
C_PLLFRAC0C2
PLL Fractional Division Ratio Register 0 Channel 2 25EH
C_PLLFRAC1C2
PLL Fractional Division Ratio Register 1 Channel 2 25FH
C_PLLFRAC2C2
PLL Fractional Division Ratio Register 2 Channel 2 260H
C_PLLINTC3
PLL MMD Integer Value Register Channel 3
C_PLLFRAC0C3
PLL Fractional Division Ratio Register 0 Channel 3 262H
C_PLLFRAC1C3
PLL Fractional Division Ratio Register 1 Channel 3 263H
C_PLLFRAC2C3
PLL Fractional Division Ratio Register 2 Channel 3 264H
D_IF1
IF1 Register
D_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 31BH
D_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
31CH
D_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
31DH
D_WURSSITH2
RSSI Wake-Up Threshold for Channel 2 Register 31EH
D_WURSSIBL2
RSSI Wake-Up Blocking Level Low Channel 2
Register
31FH
D_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
320H
D_WURSSITH3
RSSI Wake-Up Threshold for Channel 3 Register 321H
D_WURSSIBL3
RSSI Wake-Up Blocking Level Low Channel 3
Register
322H
D_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
323H
D_WULOT
Wake-Up on Level Observation Time Register
325H
D_AFCLIMIT
AFC Limit Configuration Register
32AH
D_AFCAGCD
AFC/AGC Freeze Delay Register
32BH
D_AFCSFCFG
AFC Start/Freeze Configuration Register
32CH
D_AFCK1CFG0
AFC Integrator 1 Gain Register 0
32DH
D_AFCK1CFG1
AFC Integrator 1 Gain Register 1
32EH
D_AFCK2CFG0
AFC Integrator 2 Gain Register 0
32FH
Data Sheet
Page Number
25DH
261H
316H
113
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
D_AFCK2CFG1
AFC Integrator 2 Gain Register 1
330H
D_PMFUDSF
Peak Memory Filter Up-Down Factor Register
331H
D_AGCSFCFG
AGC Start/Freeze Configuration Register
332H
D_AGCCFG0
AGC Configuration Register 0
333H
D_AGCCFG1
AGC Configuration Register 1
334H
D_AGCTHR
AGC Threshold Register
335H
D_DIGRXC
Digital Receiver Configuration Register
336H
D_ISUPFCSEL
Image Supression Fc Selection Register
338H
D_PDECF
Pre Decimation Factor Register
339H
D_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
33AH
D_PDECSCASK
Pre Decimation Scaling Register ASK Mode
33BH
D_MFC
Matched Filter Control Register
33CH
D_SRC
Sampe Rate Converter NCO Tune
33DH
D_EXTSLC
Externel Data Slicer Configuration
33EH
D_CHCFG
Channel Configuration Register
358H
D_PLLINTC1
PLL MMD Integer Value Register Channel 1
359H
D_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 35AH
D_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 35BH
D_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 35CH
D_PLLINTC2
PLL MMD Integer Value Register Channel 2
D_PLLFRAC0C2
PLL Fractional Division Ratio Register 0 Channel 2 35EH
D_PLLFRAC1C2
PLL Fractional Division Ratio Register 1 Channel 2 35FH
D_PLLFRAC2C2
PLL Fractional Division Ratio Register 2 Channel 2 360H
D_PLLINTC3
PLL MMD Integer Value Register Channel 3
D_PLLFRAC0C3
PLL Fractional Division Ratio Register 0 Channel 3 362H
D_PLLFRAC1C3
PLL Fractional Division Ratio Register 1 Channel 3 363H
D_PLLFRAC2C3
PLL Fractional Division Ratio Register 2 Channel 3 364H
Table 2
Page Number
35DH
361H
Register Overview and Reset Value
Register Short Name
Register Long Name
Offset Address
Reset Value
Appendix - Registers Chapter, Register Description
A_IF1
IF1 Register
016H
20H
A_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 01BH
00H
A_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
01CH
FFH
A_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
01DH
00H
A_WURSSITH2
RSSI Wake-Up Threshold for Channel 2 Register 01EH
00H
Data Sheet
114
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
A_WURSSIBL2
RSSI Wake-Up Blocking Level Low Channel 2
Register
01FH
FFH
A_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
020H
00H
A_WURSSITH3
RSSI Wake-Up Threshold for Channel 3 Register 021H
00H
A_WURSSIBL3
RSSI Wake-Up Blocking Level Low Channel 3
Register
022H
FFH
A_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
023H
00H
A_WULOT
Wake-up on Level Observation Time Register
025H
00H
A_AFCLIMIT
AFC Limit Configuration Register
02AH
02H
A_AFCAGCD
AFC/AGC Freeze Delay Register
02BH
00H
A_AFCSFCFG
AFC Start/Freeze Configuration Register
02CH
00H
A_AFCK1CFG0
AFC Integrator 1 Gain Register 0
02DH
00H
A_AFCK1CFG1
AFC Integrator 1 Gain Register 1
02EH
00H
A_AFCK2CFG0
AFC Integrator 2 Gain Register 0
02FH
00H
A_AFCK2CFG1
AFC Integrator 2 Gain Register 1
030H
00H
A_PMFUDSF
Peak Memory Filter Up-Down Factor Register
031H
42H
A_AGCSFCFG
AGC Start/Freeze Configuration Register
032H
00H
A_AGCCFG0
AGC Configuration Register 0
033H
2BH
A_AGCCFG1
AGC Configuration Register 1
034H
03H
A_AGCTHR
AGC Threshold Register
035H
08H
A_DIGRXC
Digital Receiver Configuration Register
036H
40H
A_ISUPFCSEL
Image Supression Fc Selection Register
038H
07H
A_PDECF
Pre Decimation Factor Register
039H
00H
A_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
03AH
00H
A_PDECSCASK
Pre Decimation Scaling Register ASK Mode
03BH
20H
A_MFC
Matched Filter Control Register
03CH
07H
A_SRC
Sampe Rate Converter NCO Tune
03DH
00H
A_EXTSLC
Externel Data Slicer Configuration
03EH
02H
A_CHCFG
Channel Configuration Register
058H
44H
A_PLLINTC1
PLL MMD Integer Value Register Channel 1
059H
93H
A_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 05AH
F3H
A_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 05BH
07H
A_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 05CH
09H
A_PLLINTC2
PLL MMD Integer Value Register Channel 2
05DH
13H
A_PLLFRAC0C2
PLL Fractional Division Ratio Register 0 Channel 2 05EH
F3H
A_PLLFRAC1C2
PLL Fractional Division Ratio Register 1 Channel 2 05FH
07H
A_PLLFRAC2C2
PLL Fractional Division Ratio Register 2 Channel 2 060H
09H
Data Sheet
115
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
A_PLLINTC3
PLL MMD Integer Value Register Channel 3
061H
13H
A_PLLFRAC0C3
PLL Fractional Division Ratio Register 0 Channel 3 062H
F3H
A_PLLFRAC1C3
PLL Fractional Division Ratio Register 1 Channel 3 063H
07H
A_PLLFRAC2C3
PLL Fractional Division Ratio Register 2 Channel 3 064H
09H
SFRPAGE
Special Function Register Page Register
080H
00H
PPCFG0
PP0 and PP1 Configuration Register
081H
50H
PPCFG1
PP2 and PP3 Configuration Register
082H
12H
PPCFG2
PPx Port Configuration Register
083H
00H
RXRUNCFG0
RX RUN Configuration Register 0
084H
FFH
RXRUNCFG1
RX RUN Configuration Register 1
085H
FFH
CLKOUT0
Clock Divider Register 0
086H
0BH
CLKOUT1
Clock Divider Register 1
087H
00H
CLKOUT2
Clock Divider Register 2
088H
00H
RFC
RF Control Register
089H
07H
BPFCALCFG0
BPF Calibration Configuration Register 0
08AH
07H
BPFCALCFG1
BPF Calibration Configuration Register 1
08BH
04H
XTALCAL0
XTAL Coarse Calibration Register
08CH
10H
XTALCAL1
XTAL Fine Calibration Register
08DH
00H
RSSIMONC
RSSI Monitor Configuration Register
08EH
01H
ADCINSEL
ADC Input Selection Register
08FH
00H
RSSIOFFS
RSSI Offset Register
090H
80H
RSSISLOPE
RSSI Slope Register
091H
80H
IM0
Interrupt Mask Register 0
094H
00H
IM1
Interrupt Mask Register 1
095H
00H
SPMAP
Self Polling Mode Active Periods Register
096H
01H
SPMIP
Self Polling Mode Idle Periods Register
097H
01H
SPMC
Self Polling Mode Control Register
098H
00H
SPMRT
Self Polling Mode Reference Timer Register
099H
01H
SPMOFFT0
Self Polling Mode Off Time Register 0
09AH
01H
SPMOFFT1
Self Polling Mode Off Time Register 1
09BH
00H
SPMONTA0
Self Polling Mode On Time Config A Register 0
09CH
01H
SPMONTA1
Self Polling Mode On Time Config A Register 1
09DH
00H
SPMONTB0
Self Polling Mode On Time Config B Register 0
09EH
01H
SPMONTB1
Self Polling Mode On Time Config B Register 1
09FH
00H
SPMONTC0
Self Polling Mode On Time Config C Register 0
0A0H
01H
SPMONTC1
Self Polling Mode On Time Config C Register 1
0A1H
00H
SPMONTD0
Self Polling Mode On Time Config D Register 0
0A2H
01H
SPMONTD1
Self Polling Mode On Time Config D Register 1
0A3H
00H
Data Sheet
116
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
EXTPCMD
External Processing Command Register
0A4H
00H
CMC1
Chip Mode Control Register 1
0A5H
04H
CMC0
Chip Mode Control Register 0
0A6H
10H
RSSIPWU
Wakeup Peak Detector Readout Register
0A7H
00H
IS0
Interrupt Status Register 0
0A8H
FFH
IS1
Interrupt Status Register 1
0A9H
FFH
RFPLLACC
RF PLL Actual Channel and Configuration
Register
0AAH
00H
RSSIPRX
RSSI Peak Detector Readout Register
0ABH
00H
ADCRESH
ADC Result High Byte Register
0AEH
00H
ADCRESL
ADC Result Low Byte Register
0AFH
00H
VACRES
VCO Autocalibration Result Readout Register
0B0H
00H
AFCOFFSET
AFC Offset Read Register
0B1H
00H
AGCGAINR
AGC Gain Readout Register
0B2H
00H
SPIAT
SPI Address Tracer Register
0B3H
00H
SPIDT
SPI Data Tracer Register
0B4H
00H
SPICHKSUM
SPI Checksum Register
0B5H
00H
SN0
Serial Number Register 0
0B6H
00H
SN1
Serial Number Register 1
0B7H
00H
SN2
Serial Number Register 2
0B8H
00H
SN3
Serial Number Register 3
0B9H
00H
RSSIRX
RSSI Readout Register
0BAH
00H
RSSIPMF
RSSI Peak Memory Filter Readout Register
0BBH
00H
B_IF1
IF1 Register
116H
20H
B_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 11BH
00H
B_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
11CH
FFH
B_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
11DH
00H
B_WURSSITH2
RSSI Wake-Up Threshold for Channel 2 Register 11EH
00H
B_WURSSIBL2
RSSI Wake-Up Blocking Level Low Channel 2
Register
11FH
FFH
B_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
120H
00H
B_WURSSITH3
RSSI Wake-Up Threshold for Channel 3 Register 121H
00H
B_WURSSIBL3
RSSI Wake-Up Blocking Level Low Channel 3
Register
122H
FFH
B_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
123H
00H
B_WULOT
Wake-Up on Level Observation Time Register
125H
00H
Data Sheet
117
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
B_AFCLIMIT
AFC Limit Configuration Register
12AH
02H
B_AFCAGCD
AFC/AGC Freeze Delay Register
12BH
00H
B_AFCSFCFG
AFC Start/Freeze Configuration Register
12CH
00H
B_AFCK1CFG0
AFC Integrator 1 Gain Register 0
12DH
00H
B_AFCK1CFG1
AFC Integrator 1 Gain Register 1
12EH
00H
B_AFCK2CFG0
AFC Integrator 2 Gain Register 0
12FH
00H
B_AFCK2CFG1
AFC Integrator 2 Gain Register 1
130H
00H
B_PMFUDSF
Peak Memory Filter Up-Down Factor Register
131H
42H
B_AGCSFCFG
AGC Start/Freeze Configuration Register
132H
00H
B_AGCCFG0
AGC Configuration Register 0
133H
2BH
B_AGCCFG1
AGC Configuration Register 1
134H
03H
B_AGCTHR
AGC Threshold Register
135H
08H
B_DIGRXC
Digital Receiver Configuration Register
136H
40H
B_ISUPFCSEL
Image Supression Fc Selection Register
138H
07H
B_PDECF
Pre Decimation Factor Register
139H
00H
B_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
13AH
00H
B_PDECSCASK
Pre Decimation Scaling Register ASK Mode
13BH
20H
B_MFC
Matched Filter Control Register
13CH
07H
B_SRC
Sampe Rate Converter NCO Tune
13DH
00H
B_EXTSLC
Externel Data Slicer Configuration
13EH
02H
B_CHCFG
Channel Configuration Register
158H
44H
B_PLLINTC1
PLL MMD Integer Value Register Channel 1
159H
93H
B_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 15AH
F3H
B_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 15BH
07H
B_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 15CH
09H
B_PLLINTC2
PLL MMD Integer Value Register Channel 2
15DH
13H
B_PLLFRAC0C2
PLL Fractional Division Ratio Register 0 Channel 2 15EH
F3H
B_PLLFRAC1C2
PLL Fractional Division Ratio Register 1 Channel 2 15FH
07H
B_PLLFRAC2C2
PLL Fractional Division Ratio Register 2 Channel 2 160H
09H
B_PLLINTC3
PLL MMD Integer Value Register Channel 3
161H
13H
B_PLLFRAC0C3
PLL Fractional Division Ratio Register 0 Channel 3 162H
F3H
B_PLLFRAC1C3
PLL Fractional Division Ratio Register 1 Channel 3 163H
07H
B_PLLFRAC2C3
PLL Fractional Division Ratio Register 2 Channel 3 164H
09H
C_IF1
IF1 Register
216H
20H
C_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 21BH
00H
C_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
21CH
FFH
C_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
21DH
00H
Data Sheet
118
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
C_WURSSITH2
RSSI Wake-Up Threshold for Channel 2 Register 21EH
00H
C_WURSSIBL2
RSSI Wake-Up Blocking Level Low Channel 2
Register
21FH
FFH
C_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
220H
00H
C_WURSSITH3
RSSI Wake-Up Threshold for Channel 3 Register 221H
00H
C_WURSSIBL3
RSSI Wake-Up Blocking Level Low Channel 3
Register
222H
FFH
C_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
223H
00H
C_WULOT
Wake-Up on Level Observation Time Register
225H
00H
C_AFCLIMIT
AFC Limit Configuration Register
22AH
02H
C_AFCAGCD
AFC/AGC Freeze Delay Register
22BH
00H
C_AFCSFCFG
AFC Start/Freeze Configuration Register
22CH
00H
C_AFCK1CFG0
AFC Integrator 1 Gain Register 0
22DH
00H
C_AFCK1CFG1
AFC Integrator 1 Gain Register 1
22EH
00H
C_AFCK2CFG0
AFC Integrator 2 Gain Register 0
22FH
00H
C_AFCK2CFG1
AFC Integrator 2 Gain Register 1
230H
00H
C_PMFUDSF
Peak Memory Filter Up-Down Factor Register
231H
42H
C_AGCSFCFG
AGC Start/Freeze Configuration Register
232H
00H
C_AGCCFG0
AGC Configuration Register 0
233H
2BH
C_AGCCFG1
AGC Configuration Register 1
234H
03H
C_AGCTHR
AGC Threshold Register
235H
08H
C_DIGRXC
Digital Receiver Configuration Register
236H
40H
C_ISUPFCSEL
Image Supression Fc Selection Register
238H
07H
C_PDECF
Pre Decimation Factor Register
239H
00H
C_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
23AH
00H
C_PDECSCASK
Pre Decimation Scaling Register ASK Mode
23BH
20H
C_MFC
Matched Filter Control Register
23CH
07H
C_SRC
Sampe Rate Converter NCO Tune
23DH
00H
C_EXTSLC
Externel Data Slicer Configuration
23EH
02H
C_CHCFG
Channel Configuration Register
258H
44H
C_PLLINTC1
PLL MMD Integer Value Register Channel 1
259H
93H
C_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 25AH
F3H
C_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 25BH
07H
C_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 25CH
09H
C_PLLINTC2
PLL MMD Integer Value Register Channel 2
25DH
13H
C_PLLFRAC0C2
PLL Fractional Division Ratio Register 0 Channel 2 25EH
F3H
C_PLLFRAC1C2
PLL Fractional Division Ratio Register 1 Channel 2 25FH
07H
Data Sheet
Offset Address
119
Reset Value
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
C_PLLFRAC2C2
PLL Fractional Division Ratio Register 2 Channel 2 260H
09H
C_PLLINTC3
PLL MMD Integer Value Register Channel 3
261H
13H
C_PLLFRAC0C3
PLL Fractional Division Ratio Register 0 Channel 3 262H
F3H
C_PLLFRAC1C3
PLL Fractional Division Ratio Register 1 Channel 3 263H
07H
C_PLLFRAC2C3
PLL Fractional Division Ratio Register 2 Channel 3 264H
09H
D_IF1
IF1 Register
316H
20H
D_WURSSITH1
RSSI Wake-Up Threshold for Channel 1 Register 31BH
00H
D_WURSSIBL1
RSSI Wake-Up Blocking Level Low Channel 1
Register
31CH
FFH
D_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
31DH
00H
D_WURSSITH2
RSSI Wake-Up Threshold for Channel 2 Register 31EH
00H
D_WURSSIBL2
RSSI Wake-Up Blocking Level Low Channel 2
Register
31FH
FFH
D_WURSSIBH2
RSSI Wake-Up Blocking Level High Channel 2
Register
320H
00H
D_WURSSITH3
RSSI Wake-Up Threshold for Channel 3 Register 321H
00H
D_WURSSIBL3
RSSI Wake-Up Blocking Level Low Channel 3
Register
322H
FFH
D_WURSSIBH3
RSSI Wake-Up Blocking Level High Channel 3
Register
323H
00H
D_WULOT
Wake-Up on Level Observation Time Register
325H
00H
D_AFCLIMIT
AFC Limit Configuration Register
32AH
02H
D_AFCAGCD
AFC/AGC Freeze Delay Register
32BH
00H
D_AFCSFCFG
AFC Start/Freeze Configuration Register
32CH
00H
D_AFCK1CFG0
AFC Integrator 1 Gain Register 0
32DH
00H
D_AFCK1CFG1
AFC Integrator 1 Gain Register 1
32EH
00H
D_AFCK2CFG0
AFC Integrator 2 Gain Register 0
32FH
00H
D_AFCK2CFG1
AFC Integrator 2 Gain Register 1
330H
00H
D_PMFUDSF
Peak Memory Filter Up-Down Factor Register
331H
42H
D_AGCSFCFG
AGC Start/Freeze Configuration Register
332H
00H
D_AGCCFG0
AGC Configuration Register 0
333H
2BH
D_AGCCFG1
AGC Configuration Register 1
334H
03H
D_AGCTHR
AGC Threshold Register
335H
08H
D_DIGRXC
Digital Receiver Configuration Register
336H
40H
D_ISUPFCSEL
Image Supression Fc Selection Register
338H
07H
D_PDECF
Pre Decimation Factor Register
339H
00H
D_PDECSCFSK
Pre Decimation Scaling Register FSK Mode
33AH
00H
D_PDECSCASK
Pre Decimation Scaling Register ASK Mode
33BH
20H
D_MFC
Matched Filter Control Register
33CH
07H
Data Sheet
Offset Address
120
Reset Value
V1.0, 2010-02-19
TDA5225
Appendix
Register Overview
Table 2
Register Overview and Reset Value (cont’d)
Register Short Name
Register Long Name
Offset Address
Reset Value
D_SRC
Sampe Rate Converter NCO Tune
33DH
00H
D_EXTSLC
Externel Data Slicer Configuration
33EH
02H
D_CHCFG
Channel Configuration Register
358H
44H
D_PLLINTC1
PLL MMD Integer Value Register Channel 1
359H
93H
D_PLLFRAC0C1
PLL Fractional Division Ratio Register 0 Channel 1 35AH
F3H
D_PLLFRAC1C1
PLL Fractional Division Ratio Register 1 Channel 1 35BH
07H
D_PLLFRAC2C1
PLL Fractional Division Ratio Register 2 Channel 1 35CH
09H
D_PLLINTC2
PLL MMD Integer Value Register Channel 2
35DH
13H
D_PLLFRAC0C2
PLL Fractional Division Ratio Register 0 Channel 2 35EH
F3H
D_PLLFRAC1C2
PLL Fractional Division Ratio Register 1 Channel 2 35FH
07H
D_PLLFRAC2C2
PLL Fractional Division Ratio Register 2 Channel 2 360H
09H
D_PLLINTC3
PLL MMD Integer Value Register Channel 3
361H
13H
D_PLLFRAC0C3
PLL Fractional Division Ratio Register 0 Channel 3 362H
F3H
D_PLLFRAC1C3
PLL Fractional Division Ratio Register 1 Channel 3 363H
07H
D_PLLFRAC2C3
PLL Fractional Division Ratio Register 2 Channel 3 364H
09H
Data Sheet
121
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Register Description
IF1 Register
A_IF1
Offset
IF1 Register
Reset Value
016H
8186('
66%6(/
Z
20H
%3)%:6(/
6'&6(/
,)%8)(1
&(5)6(/
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
SSBSEL
6
w
RXRF Receive Side Band Select
0B
RF = LO + IF1 (Lo-side LO-injection)
1B
RF = LO - IF1 (Hi-side LO-injection)
Reset: 0H
BPFBWSEL
5:3
w
Band Pass Filter Bandwidth Selection
000B 50 kHz
001B 80 kHz
010B 125 kHz
011B 200 kHz
100B 300 kHz
101B not used
110B not used
111B not used
Reset: 4H
SDCSEL
2
w
Single / Double Conversion Selection
0B
Double Conversion (10.7 MHz/274 kHz)
1B
Single Conversion (274 kHz)
Reset: 0H
IFBUFEN
1
w
IF Buffer Enable
0B
Disabled
1B
Enabled
Reset: 0H
CERFSEL
0
w
Number of external Ceramic Filters
0B
1 Ceramic Filter
1B
2 Ceramic Filters
Reset: 0H
RSSI Wake-Up Threshold for Channel 1 Register
Data Sheet
122
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
A_WURSSITH1
Offset
Reset Value
RSSI Wake-Up Threshold for Channel 1
Register
01BH
00H
:8566,7+
Z
Field
Bits
Type
Description
WURSSITH1
7:0
w
Wake Up on RSSI Threshold level for Channel 1
Wake Up Request generated when actual RSSI level is above this
threshold
Reset: 00H
RSSI Wake-Up Blocking Level Low Channel 1 Register
A_WURSSIBL1
Offset
Reset Value
RSSI Wake-Up Blocking Level Low Channel 1
Register
01CH
FFH
:8566,%/
Z
Field
Bits
Type
Description
WURSSIBL1
7:0
w
Wake Up on RSSI Blocking Level LOW for Channel 1
Reset: FFH
RSSI Wake-Up Blocking Level High Channel 1 Register
A_WURSSIBH1
Offset
Reset Value
RSSI Wake-Up Blocking Level High Channel
1 Register
01DH
00H
:8566,%+
Z
Data Sheet
123
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
WURSSIBH1
7:0
w
Wake Up on RSSI Blocking Level HIGH for Channel 1
Reset: 00H
RSSI Wake-Up Threshold for Channel 2 Register
A_WURSSITH2
Offset
RSSI Wake-Up Threshold for Channel 2
Register
Reset Value
01EH
00H
:8566,7+
Z
Field
Bits
Type
Description
WURSSITH2
7:0
w
Wake Up on RSSI Threshold level for Channel 2
Wake Up Request generated when actual RSSI level is above this
threshold
Reset: 00H
RSSI Wake-Up Blocking Level Low Channel 2 Register
A_WURSSIBL2
Offset
RSSI Wake-Up Blocking Level Low Channel 2
Register
Reset Value
01FH
FFH
:8566,%/
Z
Field
Bits
Type
Description
WURSSIBL2
7:0
w
Wake Up on RSSI Blocking Level LOW for Channel 2
Reset: FFH
RSSI Wake-Up Blocking Level High Channel 2 Register
Data Sheet
124
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
A_WURSSIBH2
Offset
RSSI Wake-Up Blocking Level High Channel
2 Register
Reset Value
020H
00H
:8566,%+
Z
Field
Bits
Type
Description
WURSSIBH2
7:0
w
Wake Up on RSSI Blocking Level HIGH for Channel 2
Reset: 00H
RSSI Wake-Up Threshold for Channel 3 Register
A_WURSSITH3
Offset
RSSI Wake-Up Threshold for Channel 3
Register
Reset Value
021H
00H
:8566,7+
Z
Field
Bits
Type
Description
WURSSITH3
7:0
w
Wake Up on RSSI Threshold level for Channel 3
Wake Up Request generated when actual RSSI level is above this
threshold
Reset: 00H
RSSI Wake-Up Blocking Level Low Channel 3 Register
A_WURSSIBL3
RSSI Wake-Up Blocking Level Low Channel 3
Register
Offset
Reset Value
022H
FFH
:8566,%/
Z
Data Sheet
125
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
WURSSIBL3
7:0
w
Wake Up on RSSI Blocking Level LOW for Channel 3
Reset: FFH
RSSI Wake-Up Blocking Level High Channel 3 Register
A_WURSSIBH3
Offset
RSSI Wake-Up Blocking Level High Channel
3 Register
Reset Value
023H
00H
:8566,%+
Z
Field
Bits
Type
Description
WURSSIBH3
7:0
w
Wake Up on RSSI Blocking Level HIGH for Channel 3
Reset: 00H
Wake-up on Level Observation Time Register
A_WULOT
Offset
Wake-up on Level Observation Time Register
Reset Value
025H
00H
:8/2736
:8/27
Z
Z
Field
Bits
Type
Description
WULOTPS
7:5
w
Wake-Up Level Observation Time PreScaler
000B 4
001B 8
010B 16
011B 32
100B 64
101B 128
110B 256
111B 512
Reset: 0H
Data Sheet
126
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
WULOT
4:0
w
Wake-Up Level Observation Time
Min. 01h : Twulot = 1 * WULOTPS * 64 / Fsys
Max 1Fh : Twulot = 31 * WULOTPS * 64 / Fsys
Value 00h : Twulot = 32 * WULOTPS * 64 / Fsys
Reset: 00H
AFC Limit Configuration Register
A_AFCLIMIT
Offset
Reset Value
AFC Limit Configuration Register
02AH
02H
8186('
$)&/,0,7
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
AFCLIMIT
3:0
w
AFC Frequency Offset Saturation Limit ==> 1...15 x 21.4 kHz
Min: 1h = +/- Fsys / 2^(22-12) Hz
Max: Fh = +/- 15 * Fsys / 2^(22-12) Hz
Reg. value 0h = 0 Hz - no AFC correction
Reset: 2H
AFC/AGC Freeze Delay Register
A_AFCAGCD
Offset
Reset Value
AFC/AGC Freeze Delay Register
02BH
00H
$)&$*&'
Z
Field
Bits
Type
Description
AFCAGCD
7:0
w
AFC/AGC Freeze Delay Counter Division Ratio
The base period for the delay counter is the 8-16 samples/chip
(predecimation strobe) divided by 4
Reset: 00H
Data Sheet
127
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
AFC Start/Freeze Configuration Register
A_AFCSFCFG
Offset
Reset Value
AFC Start/Freeze Configuration Register
02CH
00H
8186('
$)&%/$6
.
$)&5(6$
7&&
$)&)5((=(
$)&67$57
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
AFCBLASK
6
w
AFC blocking during a low phase in the ASK signal
0B
Disabled
1B
Enabled
Reset: 0H
AFCRESATC
C
5
w
Enable AFC Restart at Channel Change and at the beginning of the
current configuration in Self Polling Mode
and at leaving the HOLD state (when bit CMC0.INITPLLHOLD is set) in
Run Mode Slave
0B
Disabled
1B
Enabled
Reset: 0H
AFCFREEZE
4:2
w
AFC Freeze Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
000B Stay ON
001B Freeze on RSSI Event + Delay (AFCAGCDEL)
010B not used
011B not used
100B SPI Command - write to EXTPCMD.AFCMANF bit
101B n.u.
110B n.u.
111B n.u.
Reset: 0H
AFCSTART
1:0
w
AFC Start Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
00B OFF
01B Direct ON
10B Start on RSSI event
11B not used
Reset: 0H
Data Sheet
128
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
AFC Integrator 1 Gain Register 0
A_AFCK1CFG0
Offset
Reset Value
AFC Integrator 1 Gain Register 0
02DH
00H
$)&.B
Z
Field
Bits
Type
Description
AFCK1_0
7:0
w
AFC Filter coefficient K1, AFCK1(11:0) = AFCK1_1(MSB) &
AFCK1_0(LSB)
Reset: 00H
AFC Integrator 1 Gain Register 1
A_AFCK1CFG1
Offset
AFC Integrator 1 Gain Register 1
Reset Value
02EH
00H
8186('
$)&.B
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
AFCK1_1
3:0
w
AFC Filter coefficient K1, AFCK1(11:0) = AFCK1_1(MSB) &
AFCK1_0(LSB)
Reset: 0H
AFC Integrator 2 Gain Register 0
A_AFCK2CFG0
Offset
AFC Integrator 2 Gain Register 0
02FH
Data Sheet
129
Reset Value
00H
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
$)&.B
Z
Field
Bits
Type
Description
AFCK2_0
7:0
w
AFC Filter coefficient K2, AFCK2(11:0) = AFCK2_1(MSB) &
AFCK2_0(LSB)
Reset: 00H
AFC Integrator 2 Gain Register 1
A_AFCK2CFG1
Offset
AFC Integrator 2 Gain Register 1
Reset Value
030H
00H
8186('
$)&.B
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
AFCK2_1
3:0
w
AFC Filter coefficient K2, AFCK2(11:0) = AFCK2_1(MSB) &
AFCK2_0(LSB)
Reset: 0H
Peak Memory Filter Up-Down Factor Register
A_PMFUDSF
Offset
Peak Memory Filter Up-Down Factor Register
Reset Value
031H
42H
8186('
30)83
8186('
30)'1
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
Data Sheet
130
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
PMFUP
6:4
w
Peak Memory Filter Attack (Up) Factor
000B 2^-1
001B 2^-2
010B 2^-3
011B 2^-4
100B 2^-5
101B 2^-6
110B 2^-7
111B 2^-8
Reset: 4H
UNUSED
3
-
UNUSED
Reset: 0H
PMFDN
2:0
w
Peak Memory Filter Decay (Down) Factor (additional to Attack
Factor)
000B 2^-2
001B 2^-3
010B 2^-4
011B 2^-5
100B 2^-6
101B 2^-7
110B 2^-8
111B 2^-9
Reset: 2H
AGC Start/Freeze Configuration Register
A_AGCSFCFG
Offset
AGC Start/Freeze Configuration Register
Reset Value
032H
00H
8186('
$*&5(6$
7&&
$*&)5((=(
$*&67$57
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
AGCRESATC
C
5
w
Enable AGC Restart at Channel Change and at the beginning of the
current configuration in Self Polling Mode
and at leaving the HOLD state (when bit CMC0.INITPLLHOLD is set) in
Run Mode Slave
0B
Disabled
1B
Enabled
Reset: 0H
Data Sheet
131
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
AGCFREEZE
4:2
w
AGC Freeze Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
000B Stay ON
001B Freeze on RSSI Event + Delay (AFCAGCDEL)
010B not used
011B not used
100B SPI Command - write to EXTPCMD.AGCMANF bit
101B n.u.
110B n.u.
111B n.u.
Reset: 0H
AGCSTART
1:0
w
AGC Start Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
00B OFF
01B Direct ON
10B Start on RSSI event
11B not used
Reset: 0H
AGC Configuration Register 0
A_AGCCFG0
Offset
AGC Configuration Register 0
Reset Value
033H
2BH
8186('
$*&'*&
$*&+<6
$*&*$,1
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
AGCDGC
6:4
w
AGC Digital RSSI Gain Correction Tuning
000B 14.5 dB
001B 15.0 dB
010B 15.5 dB
011B 16.0 dB
100B 16.5 dB
101B 17.0 dB
110B 17.5 dB
111B 18.0 dB
Reset: 2H
Data Sheet
132
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
AGCHYS
3:2
w
AGC Threshold Hysteresis
00B 12.8 dB
01B 17.1 dB
10B 21.3 dB
11B 25.6 dB
Reset: 2H
AGCGAIN
1:0
w
AGC Gain Control
00B 0 dB
01B -15 dB
10B -30 dB
11B Automatic
Reset: 3H
AGC Configuration Register 1
A_AGCCFG1
Offset
AGC Configuration Register 1
Reset Value
034H
03H
8186('
$*&7+2))6
Z
Field
Bits
Type
Description
UNUSED
7:2
-
UNUSED
Reset: 00H
AGCTHOFFS
1:0
w
AGC Threshold Offset
00B 25.5 dB
01B 38.3 dB
10B 51.1 dB
11B 63.9 dB
Reset: 3H
AGC Threshold Register
A_AGCTHR
Offset
AGC Threshold Register
035H
Data Sheet
Reset Value
08H
$*&783
$*&7/2
Z
Z
133
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
AGCTUP
7:4
w
AGC Upper Attack Threshold [dB]
AGC Upper Threshold = A_AGCCFG1.AGCTHOFFS + 25.6 +
AGCTUP*1.6
Reset: 0H
AGCTLO
3:0
w
AGC Lower Attack Threshold [dB]
AGC Lower Threshold = A_AGCCFG1.AGCTHOFFS + AGCTLO*1.6
Reset: 8H
Digital Receiver Configuration Register
A_DIGRXC
Offset
Digital Receiver Configuration Register
Reset Value
036H
40H
,1,7'5;
(6
8186('
',19(;7
$$)%<3
$$))&6(
/
Z
Z
Z
Z
Z
Field
Bits
Type
Description
INITDRXES
7
w
Init the Digital Receiver at EOM signal (e.g. for initialization of the
Peak Memory Filter)
0B
Disabled
1B
Enabled
Reset: 0H
UNUSED
6:3
w
UNUSED
Reset: 8H
DINVEXT
2
w
Data Inversion of signal DATA and DATA_MATCHFIL for External
Processing
0B
Not inverted
1B
Inverted
Reset: 0H
AAFBYP
1
w
Anti-Alliasing Filter Bypass for RSSI pin
0B
Not bypassed
1B
Bypassed
Reset: 0H
AAFFCSEL
0
w
Anti-Alliasing Filter Corner Frequency Select
0B
40 kHz
1B
80 kHz
Reset: 0H
Image Supression Fc Selection Register
Data Sheet
134
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
A_ISUPFCSEL
Offset
Image Supression Fc Selection Register
Reset Value
038H
07H
5HV
8186('
)&6(/
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
FCSEL
2:0
w
Image Supression Filter Corner Frequency Selection for FSK signal
path
000B 33 kHz
001B 46 kHz
010B 65 kHz
011B 93 kHz
100B 132 kHz
101B 190 kHz
110B 239 kHz
111B 282 kHz
Reset: 7H
Pre Decimation Factor Register
A_PDECF
Offset
Pre Decimation Factor Register
Reset Value
039H
00H
8186('
35('(&)
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
PREDECF
6:0
w
Predecimation Filter Decimation Factor
Predecimation Factor = PREDECF + 1
Reset: 00H
Pre Decimation Scaling Register FSK Mode
Data Sheet
135
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
A_PDECSCFSK
Offset
Reset Value
Pre Decimation Scaling Register FSK Mode
03AH
00H
5HV
,1732/(
1)
3'6&$/()
Z
Z
Field
Bits
Type
Description
INTPOLENF
5
w
FSK Data Interpolation Enable
0B
Disabled
1B
Enabled
Reset: 0H
PDSCALEF
4:0
w
Predecimation Block Scaling Factor for FSK
Min 00h : 2^-10
Max 17h : 2^13
Reset: 00H
Pre Decimation Scaling Register ASK Mode
A_PDECSCASK
Offset
Reset Value
Pre Decimation Scaling Register ASK Mode
03BH
20H
8186('
5HV
,1732/(
1$
3'6&$/($
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
INTPOLENA
5
w
ASK Data Interpolation Enable
0B
Disabled
1B
Enabled
Reset: 1H
PDSCALEA
4:0
w
Predecimation Block Scaling Factor for ASK
Min 00h : 2^-10
Max 17h : 2^13
Reset: 00H
Matched Filter Control Register
Data Sheet
136
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
A_MFC
Offset
Reset Value
Matched Filter Control Register
03CH
07H
8186('
0)/
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
MFL
3:0
w
Matched Filter Length
MF Length = MFL + 1
Reset: 7H
Sampe Rate Converter NCO Tune
A_SRC
Offset
Reset Value
Sampe Rate Converter NCO Tune
03DH
00H
65&1&2
Z
Field
Bits
Type
Description
SRCNCO
7:0
w
Sample Rate Converter NCO Tune
Min 00h : Fout = Fin
Max FFh : Fout = Fin / 2
Reset: 00H
Externel Data Slicer Configuration
A_EXTSLC
Offset
Externel Data Slicer Configuration
8186('
Data Sheet
5HV
Reset Value
03EH
02H
(6/&6&$
(6/&%:
Z
Z
137
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
ESLCSCA
4:3
w
External Slicer BW Selection Scaling
00B 1/2
01B 1/4
10B 1/8
11B 1/16
Reset: 0H
ESLCBW
2:0
w
External Slicer Manual BW Selection
000B 1/8
001B 1/16
010B 1/24
011B 1/32
100B 1/40
101B 1/48
110B n.u.
111B n.u.
Reset: 2H
Channel Configuration Register
A_CHCFG
Offset
Channel Configuration Register
Reset Value
058H
44H
8186('
(20630
12&
07
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 2H
EOM2SPM
4
w
Continue with Self Polling Mode after EOM detected in Run Mode
Self Polling
0B
Disabled - stay in Run Mode Self Polling (next Payload Frame is
expected)
1B
Enabled - leave Run Mode Self Polling after EOM
Reset: 0H
Data Sheet
138
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
NOC
3:2
w
Number of Channels (Run Mode Slave / Self Polling Mode - Run
Mode Self Polling)
00B Channel 1 / Channel 1
01B Channel 1 / Channel 1
10B Channel 2 / Channel 1 + 2
11B Channel 3 / Channel 1 + 2 + 3
Reset: 1H
MT
1:0
w
Modulation Type (Run Mode Slave / Self Polling Mode - Run Mode
Self Polling)
00B ASK / ASK - ASK
01B FSK / FSK - FSK
10B ASK / FSK - ASK
11B FSK / ASK - FSK
Reset: 0H
PLL MMD Integer Value Register Channel 1
A_PLLINTC1
Offset
PLL MMD Integer Value Register Channel 1
Reset Value
059H
93H
%$1'6(/
3//,17&
Z
Z
Field
Bits
Type
Description
BANDSEL
7:6
w
Frequency Band Selection
00B not used
01B 915MHz/868MHz
10B 434MHz
11B 315MHz
Reset: 2H
PLLINTC1
5:0
w
SDPLL Multi Modulus Divider Integer Offset value for Channel 1
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13H
PLL Fractional Division Ratio Register 0 Channel 1
A_PLLFRAC0C1
Offset
Reset Value
PLL Fractional Division Ratio Register 0
Channel 1
05AH
F3H
Data Sheet
139
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
3//)5$&&
Z
Field
Bits
PLLFRAC0C1 7:0
Type
Description
w
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3H
PLL Fractional Division Ratio Register 1 Channel 1
A_PLLFRAC1C1
Offset
Reset Value
PLL Fractional Division Ratio Register 1
Channel 1
05BH
07H
3//)5$&&
Z
Field
Bits
PLLFRAC1C1 7:0
Type
Description
w
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07H
PLL Fractional Division Ratio Register 2 Channel 1
A_PLLFRAC2C1
Offset
Reset Value
PLL Fractional Division Ratio Register 2
Channel 1
05CH
09H
8186('
3//)&20
3&
3//)5$&&
Z
Z
Data Sheet
140
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
PLLFCOMPC1 5
w
Fractional Spurii Compensation enable for Channel 1
0B
Disabled
1B
Enabled
Reset: 0H
PLLFRAC2C1 4:0
w
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09H
PLL MMD Integer Value Register Channel 2
A_PLLINTC2
Offset
Reset Value
PLL MMD Integer Value Register Channel 2
05DH
13H
8186('
3//,17&
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
PLLINTC2
5:0
w
SDPLL Multi Modulus Divider Integer Offset value for Channel 2
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13H
PLL Fractional Division Ratio Register 0 Channel 2
A_PLLFRAC0C2
PLL Fractional Division Ratio Register 0
Channel 2
Offset
Reset Value
05EH
F3H
3//)5$&&
Z
Data Sheet
141
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
PLLFRAC0C2 7:0
Type
Description
w
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 2
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3H
PLL Fractional Division Ratio Register 1 Channel 2
A_PLLFRAC1C2
Offset
PLL Fractional Division Ratio Register 1
Channel 2
Reset Value
05FH
07H
3//)5$&&
Z
Field
Bits
PLLFRAC1C2 7:0
Type
Description
w
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 2
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07H
PLL Fractional Division Ratio Register 2 Channel 2
A_PLLFRAC2C2
Offset
PLL Fractional Division Ratio Register 2
Channel 2
Reset Value
060H
09H
8186('
3//)&20
3&
3//)5$&&
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
w
Fractional Spurii Compensation enable for Channel 2
0B
Disabled
1B
Enabled
Reset: 0H
PLLFCOMPC2 5
Data Sheet
142
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
PLLFRAC2C2 4:0
Type
Description
w
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 2
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09H
PLL MMD Integer Value Register Channel 3
A_PLLINTC3
Offset
PLL MMD Integer Value Register Channel 3
Reset Value
061H
13H
8186('
3//,17&
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
PLLINTC3
5:0
w
SDPLL Multi Modulus Divider Integer Offset value for Channel 3
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13H
PLL Fractional Division Ratio Register 0 Channel 3
A_PLLFRAC0C3
Offset
PLL Fractional Division Ratio Register 0
Channel 3
Reset Value
062H
F3H
3//)5$&&
Z
Field
Bits
PLLFRAC0C3 7:0
Type
Description
w
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3H
PLL Fractional Division Ratio Register 1 Channel 3
Data Sheet
143
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
A_PLLFRAC1C3
Offset
PLL Fractional Division Ratio Register 1
Channel 3
Reset Value
063H
07H
3//)5$&&
Z
Field
Bits
PLLFRAC1C3 7:0
Type
Description
w
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07H
PLL Fractional Division Ratio Register 2 Channel 3
A_PLLFRAC2C3
Offset
PLL Fractional Division Ratio Register 2
Channel 3
Reset Value
064H
09H
8186('
3//)&20
3&
3//)5$&&
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
PLLFCOMPC3 5
w
Fractional Spurii Compensation enable for Channel 3
0B
Disabled
1B
Enabled
Reset: 0H
PLLFRAC2C3 4:0
w
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09H
Special Function Register Page Register
Data Sheet
144
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
SFRPAGE
Offset
Special Function Register Page Register
Reset Value
080H
00H
8186('
6)53$*(
Z
Field
Bits
Type
Description
UNUSED
7:2
-
UNUSED
Reset: 00H
SFRPAGE
1:0
w
Selection of Register Page File (Configuration A..D) for SPI
communication
00B Page 0 (Config. A, start address: 000H)
01B Page 1 (Config. B, start address: 100H)
10B Page 2 (Config. C, start address: 200H)
11B Page 3 (Config. D, start address: 300H)
Reset: 0H
PP0 and PP1 Configuration Register
PPCFG0
Offset
PP0 and PP1 Configuration Register
Reset Value
081H
50H
8186('
33&)*
8186('
33&)*
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
w
UNUSED
Reset: 0H
PP1CFG
6:4
w
Port Pin 1 Output Signal Selection
000B CLK_OUT
001B RX_RUN
010B NINT
011B LOW
100B HIGH
101B DATA
110B DATA_MATCHFIL
111B n.u.
Reset: 5H
Data Sheet
145
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
3
w
UNUSED
Reset: 0H
PP0CFG
2:0
w
Port Pin 0 Output Signal Selection
000B CLK_OUT
001B RX_RUN
010B NINT
011B LOW
100B HIGH
101B DATA
110B DATA_MATCHFIL
111B n.u.
Reset: 0H
PP2 and PP3 Configuration Register
PPCFG1
Offset
PP2 and PP3 Configuration Register
Reset Value
082H
12H
8186('
33&)*
8186('
33&)*
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
w
UNUSED
Reset: 0H
PP3CFG
6:4
w
Port Pin 3 Output Signal Selection
000B n.u.
001B RX_RUN
010B NINT
011B LOW
100B HIGH
101B DATA
110B DATA_MATCHFIL
111B n.u.
Reset: 1H
UNUSED
3
w
UNUSED
Reset: 0H
Data Sheet
146
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
PP2CFG
2:0
w
Port Pin 2 Output Signal Selection
000B CLK_OUT
001B RX_RUN
010B NINT
011B LOW
100B HIGH
101B DATA
110B DATA_MATCHFIL
111B n.u.
Reset: 2H
PPx Port Configuration Register
PPCFG2
Offset
PPx Port Configuration Register
Reset Value
083H
00H
33+33(
1
33+33(
1
33+33(
1
33+33(
1
33,19
33,19
33,19
33,19
Z
Z
Z
Z
Z
Z
Z
Z
Field
Bits
Type
Description
PP3HPPEN
7
w
PP3 High Power Pad Enable
0B
Normal
1B
High Power
Reset: 0H
PP2HPPEN
6
w
PP2 High Power Pad Enable
0B
Normal
1B
High Power
Reset: 0H
PP1HPPEN
5
w
PP1 High Power Pad Enable
0B
Normal
1B
High Power
Reset: 0H
PP0HPPEN
4
w
PP0 High Power Pad Enable
0B
Normal
1B
High Power
Reset: 0H
PP3INV
3
w
PP3 Inversion Enable
0B
Not Inverted
1B
Inverted
Reset: 0H
Data Sheet
147
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
PP2INV
2
w
PP2 Inversion Enable
0B
Not Inverted
1B
Inverted
Reset: 0H
PP1INV
1
w
PP1 Inversion Enable
0B
Not Inverted
1B
Inverted
Reset: 0H
PP0INV
0
w
PP0 Inversion Enable
0B
Not Inverted
1B
Inverted
Reset: 0H
RX RUN Configuration Register 0
RXRUNCFG0
Offset
RX RUN Configuration Register 0
Reset Value
084H
FFH
5;58133
'
5;58133
&
5;58133
%
5;58133
$
5;58133
'
5;58133
&
5;58133
%
5;58133
$
Z
Z
Z
Z
Z
Z
Z
Z
Field
Bits
Type
Description
RXRUNPP1D
7
w
RXRUN Active Level on PP1 for Configuration D
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP1C
6
w
RXRUN Active Level on PP1 for Configuration C
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP1B
5
w
RXRUN Active Level on PP1 for Configuration B
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP1A
4
w
RXRUN Active Level on PP1 for Configuration A
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP0D
3
w
RXRUN Active Level on PP0 for Configuration D
0B
Active Low
1B
Active High
Reset: 1H
Data Sheet
148
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
RXRUNPP0C
2
w
RXRUN Active Level on PP0 for Configuration C
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP0B
1
w
RXRUN Active Level on PP0 for Configuration B
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP0A
0
w
RXRUN Active Level on PP0 for Configuration A
0B
Active Low
1B
Active High
Reset: 1H
RX RUN Configuration Register 1
RXRUNCFG1
Offset
RX RUN Configuration Register 1
Reset Value
085H
FFH
5;58133
'
5;58133
&
5;58133
%
5;58133
$
5;58133
'
5;58133
&
5;58133
%
5;58133
$
Z
Z
Z
Z
Z
Z
Z
Z
Field
Bits
Type
Description
RXRUNPP3D
7
w
RXRUN Active Level on PP3 for Configuration D
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP3C
6
w
RXRUN Active Level on PP3 for Configuration C
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP3B
5
w
RXRUN Active Level on PP3 for Configuration B
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP3A
4
w
RXRUN Active Level on PP3 for Configuration A
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP2D
3
w
RXRUN Active Level on PP2 for Configuration D
0B
Active Low
1B
Active High
Reset: 1H
Data Sheet
149
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
RXRUNPP2C
2
w
RXRUN Active Level on PP2 for Configuration C
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP2B
1
w
RXRUN Active Level on PP2 for Configuration B
0B
Active Low
1B
Active High
Reset: 1H
RXRUNPP2A
0
w
RXRUN Active Level on PP2 for Configuration A
0B
Active Low
1B
Active High
Reset: 1H
Clock Divider Register 0
CLKOUT0
Offset
Clock Divider Register 0
Reset Value
086H
0BH
&/.287
Z
Field
Bits
Type
Description
CLKOUT0
7:0
w
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 0BH
Clock Divider Register 1
CLKOUT1
Clock Divider Register 1
Offset
Reset Value
087H
00H
&/.287
Z
Data Sheet
150
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
CLKOUT1
7:0
w
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 00H
Clock Divider Register 2
CLKOUT2
Offset
Clock Divider Register 2
Reset Value
088H
00H
8186('
&/.287
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
CLKOUT2
3:0
w
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 0H
RF Control Register
RFC
Offset
RF Control Register
089H
07H
8186('
5)2))
,)$77
Z
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
Data Sheet
Reset Value
151
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
RFOFF
4
w
Switch off RF-path (for RSSI trimming)
0B
RF path enabled
1B
RF path disabled
Reset: 0H
IFATT
3:0
w
Adjust IF attenuation from LNA_IN to IF_OUT (Double-Down
Conversion / Single-Down Conversion)
Used to trim out external component tolerances.
0000B 0 dB / n.u.
0001B 0.8 dB / n.u.
0010B 1.6 dB / n.u.
0011B 2.4 dB / n.u.
0100B 3.2 dB / 0 dB
0101B 4.0 dB / 0.8 dB
0110B 4.8 dB / 1.6 dB
0111B 5.6 dB / 2.4 dB
1000B 6.4 dB / 3.2 dB
1001B 7.2 dB / 4.0 dB
1010B 8.0 dB / 4.8 dB
1011B 8.8 dB / n.u.
1100B 9.6 dB / n.u.
1101B 10.4 dB / n.u.
1110B 11.2 dB / n.u.
1111B 12.0 dB / n.u.
Reset: 7H
BPF Calibration Configuration Register 0
BPFCALCFG0
Offset
Reset Value
BPF Calibration Configuration Register 0
08AH
07H
5HV
8186('
%3)&$/67
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
BPFCALST
3:0
w
BPF Calibration Time (use default = 07H)
Min: 0h= Txtal * 80 * 7 * (0 + 4)
Max: Fh= Txtal * 80 * 7 * (15 + 4)
Reset: 7H
BPF Calibration Configuration Register 1
Data Sheet
152
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
BPFCALCFG1
Offset
Reset Value
BPF Calibration Configuration Register 1
08BH
04H
8186('
%3)&$/%:
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
BPFCALBW
5:0
w
Band Pass Filter Bandwidth Selection during Calibration
04H - 50 kHz (=default)
0DH - 80 kHz
16H - 125 kHz
1FH - 200 kHz
27H - 300 kHz
Reset: 04H
XTAL Coarse Calibration Register
XTALCAL0
Offset
Reset Value
XTAL Coarse Calibration Register
08CH
10H
8186('
;7$/6:&
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
XTALSWC
4:0
w
Xtal Trim Capacitor Value
Min 00h: 0pF
Value 01h: 1pF
Max 18h: 24pF
higher values than 18h are automatically mapped to 24pF
Reset: 10H
XTAL Fine Calibration Register
Data Sheet
153
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
XTALCAL1
Offset
Reset Value
XTAL Fine Calibration Register
08DH
00H
8186('
;7$/6:)
;7$/6:)
;7$/6:)
;7$/6:)
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
XTALSWF3
3
w
Connect 500 fF XTAL Trim capacitor
0B
not connected
1B
connected
Reset: 0H
XTALSWF2
2
w
Connect 250 fF XTAL Trim capacitor
0B
not connected
1B
connected
Reset: 0H
XTALSWF1
1
w
Connect 125 fF XTAL Trim capacitor
0B
not connected
1B
connected
Reset: 0H
XTALSWF0
0
w
Connect 62.5 fF XTAL Trim capacitor
0B
not connected
1B
connected
Reset: 0H
RSSI Monitor Configuration Register
RSSIMONC
Offset
RSSI Monitor Configuration Register
08EH
01H
5HV
8186('
566,021
(1
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
Data Sheet
Reset Value
154
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
RSSIMONEN
0
w
Enable Buffer for RSSI pin
0B
Disabled
1B
Enabled
Reset: 1H
ADC Input Selection Register
ADCINSEL
Offset
ADC Input Selection Register
Reset Value
08FH
00H
8186('
$'&,16(/
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
ADCINSEL
2:0
w
ADC Input Selection
000B RSSI
001B Temperature
010B VDDD / 2
011B n.u.
100B n.u.
101B n.u.
110B n.u.
111B n.u.
Reset: 0H
RSSI Offset Register
RSSIOFFS
RSSI Offset Register
Offset
Reset Value
090H
80H
566,2))6
Z
Data Sheet
155
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
RSSIOFFS
7:0
w
RSSI Offset Compensation Value
Min: 00h= -256
Max: FFh= 254
Reset: 80H
RSSI Slope Register
RSSISLOPE
Offset
RSSI Slope Register
Reset Value
091H
80H
566,6/23(
Z
Field
Bits
Type
Description
RSSISLOPE
7:0
w
RSSI Slope Compensation Value (Multiplication Value)
Multiplication Factor = RSSISLOPE * 2^-7
Min: 00h= 0.0
Max: FFh= 1.992
Reset: 80H
Interrupt Mask Register 0
IM0
Offset
Interrupt Mask Register 0
Reset Value
094H
00H
8186('
,0:8%
8186('
,0:8$
Z
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
IMWUB
4
w
Mask Interrupt on "Wake-up" for Configuration B
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
Data Sheet
156
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
3:1
-
UNUSED
Reset: 0H
IMWUA
0
w
Mask Interrupt on "Wake-up" for Configuration A
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
Interrupt Mask Register 1
IM1
Offset
Interrupt Mask Register 1
Reset Value
095H
00H
8186('
,0:8'
8186('
,0:8&
Z
Z
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
IMWUD
4
w
Mask Interrupt on "Wake-up" for Configuration D
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
UNUSED
3:1
-
UNUSED
Reset: 0H
IMWUC
0
w
Mask Interrupt on "Wake-up" for Configuration C
0B
Interrupt enabled
1B
Interrupt disabled
Reset: 0H
Self Polling Mode Active Periods Register
SPMAP
Offset
Self Polling Mode Active Periods Register
Data Sheet
Reset Value
096H
01H
8186('
630$3
Z
157
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
SPMAP
4:0
w
Self Polling Mode Active Periods value
Min: 01h = 1 (Master) Period
Max: 1Fh = 31(Master) Periods
Reg. value 00h = 32 (Master) Periods
Reset: 01H
Self Polling Mode Idle Periods Register
SPMIP
Offset
Self Polling Mode Idle Periods Register
Reset Value
097H
01H
630,3
Z
Field
Bits
Type
Description
SPMIP
7:0
w
Self Polling Mode Idle Periods value
Min: 01h = 1 (Master) Period
Max: FFh = 255 (Master) Periods
Reg. value 00h = 256 (Master) Periods
Reset: 01H
Self Polling Mode Control Register
SPMC
Offset
Self Polling Mode Control Register
098H
00H
8186('
630$,(1
8186('
Z
Z
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
Data Sheet
Reset Value
158
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
SPMAIEN
2
w
Self Polling Mode Active Idle Enable
0B
Disabled
1B
Enabled
Reset: 0H
UNUSED
1:0
w
UNUSED
Reset: 0H
Self Polling Mode Reference Timer Register
SPMRT
Offset
Self Polling Mode Reference Timer Register
Reset Value
099H
01H
63057
Z
Field
Bits
Type
Description
SPMRT
7:0
w
Self Polling Mode Reference Timer value
The output of this timer is used as input for the On/Off Timer
Incoming Periodic Time = 64 / fsys
Output Periodic Time = TRT = (64 * SPMRT) / fsys
Min: 01h = (64*1) / fsys
Max: 00h = (64 * 256) / fsys
Reset: 01H
Self Polling Mode Off Time Register 0
SPMOFFT0
Offset
Reset Value
Self Polling Mode Off Time Register 0
09AH
01H
6302))7
Z
Data Sheet
159
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
SPMOFFT0
7:0
w
Self Polling Mode Off Time value: SPMOFFT(13:0) =
SPMOFFT1(MSB) & SPMOFFT0(LSB)
Off -Time = TRT * SPMOFFT
Min: 0001h = 1 * TRT
Reg.Value 3FFFh = 16383 * TRT
Max: 0000h = 16384 * TRT
Reset: 01H
Self Polling Mode Off Time Register 1
SPMOFFT1
Offset
Reset Value
Self Polling Mode Off Time Register 1
09BH
00H
8186('
6302))7
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMOFFT1
5:0
w
Self Polling Mode Off Time value: SPMOFFT(13:0) =
SPMOFFT1(MSB) & SPMOFFT0(LSB)
Off -Time = TRT * SPMOFFT
Min: 0001h = 1 * TRT
Reg.Value 3FFFh = 16383 * TRT
Max: 0000h = 16384 * TRT
Reset: 00H
Self Polling Mode On Time Config A Register 0
SPMONTA0
Offset
Reset Value
Self Polling Mode On Time Config A Register
0
09CH
01H
630217$
Z
Data Sheet
160
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
SPMONTA0
7:0
w
Set Value Self Polling Mode On Time: SPMONTA(13:0) =
SPMONTA1(MSB) & SPMONTA0(LSB)
On-Time = TRT *SPMONTA
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 01H
Self Polling Mode On Time Config A Register 1
SPMONTA1
Offset
Reset Value
Self Polling Mode On Time Config A Register
1
09DH
00H
8186('
630217$
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMONTA1
5:0
w
Set Value Self Polling Mode On Time: SPMONTA(13:0) =
SPMONTA1(MSB) & SPMONTA0(LSB)
On-Time = TRT *SPMONTA
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 00H
Self Polling Mode On Time Config B Register 0
SPMONTB0
Self Polling Mode On Time Config B Register
0
Offset
Reset Value
09EH
01H
630217%
Z
Data Sheet
161
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
SPMONTB0
7:0
w
Set Value Self Polling Mode On Time: SPMONTB(13:0) =
SPMONTB1(MSB) & SPMONTB0(LSB)
On-Time = TRT *SPMONTB
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 01H
Self Polling Mode On Time Config B Register 1
SPMONTB1
Offset
Self Polling Mode On Time Config B Register
1
Reset Value
09FH
00H
8186('
630217%
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMONTB1
5:0
w
Set Value Self Polling Mode On Time: SPMONTB(13:0) =
SPMONTB1(MSB) & SPMONTB0(LSB)
On-Time = TRT *SPMONTB
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 00H
Self Polling Mode On Time Config C Register 0
SPMONTC0
Offset
Reset Value
Self Polling Mode On Time Config C Register
0
0A0H
01H
630217&
Z
Data Sheet
162
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
SPMONTC0
7:0
w
Set Value Self Polling Mode On Time: SPMONTC(13:0) =
SPMONTC1(MSB) & SPMONTC0(LSB)
On-Time = TRT *SPMONTC
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 01H
Self Polling Mode On Time Config C Register 1
SPMONTC1
Offset
Reset Value
Self Polling Mode On Time Config C Register
1
0A1H
00H
8186('
630217&
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMONTC1
5:0
w
Set Value Self Polling Mode On Time: SPMONTC(13:0) =
SPMONTC1(MSB) & SPMONTC0(LSB)
On-Time = TRT *SPMONTC
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 00H
Self Polling Mode On Time Config D Register 0
SPMONTD0
Offset
Reset Value
Self Polling Mode On Time Config D Register
0
0A2H
01H
630217'
Z
Data Sheet
163
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
SPMONTD0
7:0
w
Set Value Self Polling Mode On Time: SPMONTD(13:0) =
SPMONTD1(MSB) & SPMONTD0(LSB)
On-Time = TRT *SPMONTD
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 01H
Self Polling Mode On Time Config D Register 1
SPMONTD1
Offset
Reset Value
Self Polling Mode On Time Config D Register
1
0A3H
00H
8186('
630217'
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
SPMONTD1
5:0
w
Set Value Self Polling Mode On Time: SPMONTD(13:0) =
SPMONTD1(MSB) & SPMONTD0(LSB)
On-Time = TRT *SPMONTD
Min: 0001h = 1*TRT
Reg.Value: 3FFFh = 16383*TRT
Max: 0000h = 16384*TRT
Reset: 00H
External Processing Command Register
EXTPCMD
Offset
Reset Value
External Processing Command Register
0A4H
00H
5HV
Data Sheet
8186('
$*&0$1)
$)&0$1)
(;7727,
0
(;7(20
ZF
ZF
ZF
ZF
164
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
6:4
-
UNUSED
Reset: 0H
AGCMANF
3
wc
AGC Manual Freeze
When *_AGCSFCFG.AGCFREEZE set to SPI Command, this bit sets the
AGC to freeze mode
0B
Inactive
1B
Active
Reset: 0H
AFCMANF
2
wc
AFC Manual Freeze
When *_AFCSFCFG.AFCFREEZE set to SPI Command, this bit sets the
AFC to freeze mode
0B
Inactive
1B
Active
Reset: 0H
EXTTOTIM
1
wc
Force TOTIM signal
0B
no external TOTIM signal forced
1B
external TOTIM signal forced
Reset: 0H
EXTEOM
0
wc
Force EOM signal
0B
no external EOM signal forced
1B
external EOM signal forced
Reset: 0H
Chip Mode Control Register 1
CMC1
Offset
Reset Value
Chip Mode Control Register 1
0A5H
04H
8186('
(201&)
*
727,01
&+
8186('
;7$/+30
6
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7:6
-
UNUSED
Reset: 0H
EOM2NCFG
5
w
Continue with next Configuration in Self Polling Mode after EOM
detected in Run Mode Self Polling
0B
Continue with Configuration A in Self Polling Mode
1B
Continue with next Configuration in Self Polling Mode
Reset: 0H
Data Sheet
165
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
TOTIM2NCH
4
w
Continue with next RF channel in Self Polling Mode after TOTIM
detected in Run Mode Self Polling. In case of single RF channel
application this means "continue with next Configuration" instead
of "continue with next RF channel".
0B
Continue with Configuration A in Self Polling Mode
1B
Continue with next RF channel in Self Polling Mode
Reset: 0H
UNUSED
3:1
w
UNUSED
Reset: 2H
XTALHPMS
0
w
XTAL High Precision Mode in Sleep Mode
0B
Disabled
1B
Enabled
Reset: 0H
Chip Mode Control Register 0
CMC0
Offset
Reset Value
Chip Mode Control Register 0
0A6H
10H
6'2+33(
1
,1,73//
+2/'
+2/'
&/.287(
1
Z
Z
Z
Z
0&6
6/5;(1
06(/
Z
Z
Z
Field
Bits
Type
Description
SDOHPPEN
7
w
SDO High Power Pad Enable
0B
Normal
1B
High Power
Reset: 0H
INITPLLHOLD 6
w
Init PLL after coming from HOLD (when new channel programmed).
This requires an additional Channel Hop Time before initialization of the
Digital Receiver.
0B
No init of PLL
1B
Init of PLL
Reset: 0H
HOLD
5
w
Holds the chip in the Register Configuration state (only in Run Mode
Slave)
0B
Normal Operation
1B
Jump into the Register Config state Hold
Reset: 0H
CLKOUTEN
4
w
CLK_OUT Enable
0B
Disabled
1B
Enable programmable clock output
Reset: 1H
Data Sheet
166
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
MCS
3:2
w
Multi Configuration Selection (Run Mode Slave / Self Polling Mode)
00B Config A / Config A
01B Config B / Config A + B
10B Config C / Config A + B + C
11B Config D / Config A + B + C + D
Reset: 0H
SLRXEN
1
w
Slave Receiver Enable
This Bit is only used in Operating Mode Run Mode Slave / Sleep Mode
0B
Receiver is in Sleep Mode
1B
Receiver is in Run Mode Slave
Reset: 0H
MSEL
0
w
Operating Mode Selection
0B
Run Mode Slave / Sleep Mode
1B
Self Polling Mode
Reset: 0H
Wakeup Peak Detector Readout Register
RSSIPWU
Offset
Reset Value
Wakeup Peak Detector Readout Register
0A7H
00H
566,3:8
U
Field
Bits
Type
Description
RSSIPWU
7:0
r
Peak Detector Level at Wakeup
Set at every WU event and also set at the end of every
configuration/channel cycle within a Self Polling period.
Cleared at Reset only.
Reset: 00H
Interrupt Status Register 0
IS0
Offset
Reset Value
Interrupt Status Register 0
0A8H
FFH
Data Sheet
8186('
:8%
8186('
:8$
UF
UF
UF
UF
167
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:5
rc
UNUSED
Reset: 7H
WUB
4
rc
Interrupt Request by "Wake Up" from Configuration B (Reset event
sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
UNUSED
3:1
rc
UNUSED
Reset: 7H
WUA
0
rc
Interrupt Request by "Wake Up" from Configuration A (Reset event
sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
Interrupt Status Register 1
IS1
Offset
Reset Value
Interrupt Status Register 1
0A9H
FFH
8186('
:8'
8186('
:8&
UF
UF
UF
UF
Field
Bits
Type
Description
UNUSED
7:5
rc
UNUSED
Reset: 7H
WUD
4
rc
Interrupt Request by "Wake Up" from Configuration D (Reset event
sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
UNUSED
3:1
rc
UNUSED
Reset: 7H
WUC
0
rc
Interrupt Request by "Wake Up" from Configuration C (Reset event
sets all Bits to 1)
0B
Not detected
1B
Detected
Reset: 1H
Data Sheet
168
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
RF PLL Actual Channel and Configuration Register
RFPLLACC
Offset
Reset Value
RF PLL Actual Channel and Configuration
Register
0AAH
00H
8186('
5063$&)*
8186('
630$&
U
U
U
U
Field
Bits
Type
Description
UNUSED
7:6
r
UNUSED
Reset: 0H
RMSPACFG
5:4
r
RF PLL Run Mode Self Polling Actual Configuration
00B Configuration A
01B Configuration B
10B Configuration C
11B Configuration D
Reset: 0H
UNUSED
3:2
r
UNUSED
Reset: 0H
SPMAC
1:0
r
RF PLL Self Polling Mode Actual Channel
00B No Wake Up from any Channel was actually found
01B Wake Up was found from Channel 1
10B Wake Up was found from Channel 2
11B Wake Up was found from Channel 3
Reset: 0H
RSSI Peak Detector Readout Register
RSSIPRX
Offset
Reset Value
RSSI Peak Detector Readout Register
0ABH
00H
566,35;
UF
Data Sheet
169
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
RSSIPRX
7:0
rc
RSSI Peak Level during Receiving
Tracking is active when Digital Receiver is enabled
Set at higher peak levels than stored
Cleared at Reset and SPI read out
Reset: 00H
ADC Result High Byte Register
ADCRESH
Offset
Reset Value
ADC Result High Byte Register
0AEH
00H
$'&5(6+
UF
Field
Bits
Type
Description
ADCRESH
7:0
rc
ADC Result Value ADCRES(9:0) = ADCRESH(7:0) & ADCRESL(1:0)
Note: RC for control signal generation only, no clear
Reset: 00H
ADC Result Low Byte Register
ADCRESL
Offset
Reset Value
ADC Result Low Byte Register
0AFH
00H
8186('
$'&(2&
$'&5(6/
U
U
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
ADCEOC
2
r
ADC End of Conversion detected
0B
not detected
1B
detected
Reset: 0H
Data Sheet
170
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
ADCRESL
1:0
r
ADC Result Value ADCRES(9:0) = ADCRESH(7:0) & ADCRESL(1:0)
The 2 LSBs of the ADC result are captured when the SFR register
ADCRESH is readout.
Reset: 0H
VCO Autocalibration Result Readout Register
VACRES
Offset
Reset Value
VCO Autocalibration Result Readout
Register
0B0H
00H
5HV
8186('
9$&5(6
U
Field
Bits
Type
Description
UNUSED
7:5
-
UNUSED
Reset: 0H
VACRES
3:0
r
VCO Autocalibration Result
Returns the VCO range selected by VCO Autocalibration
Reset: 0H
AFC Offset Read Register
AFCOFFSET
Offset
Reset Value
AFC Offset Read Register
0B1H
00H
$)&2))6
U
Field
Bits
Type
Description
AFCOFFS
7:0
r
Readout of the Frequency Offset found by AFC (AFC loop filter
output).
Value is in signed representation.
Frequency resolution is 2.68 kHz/digit
Output can be limited by x_AFCLIMIT register
Update rate is 548 kHz
Reset: 00H
Data Sheet
171
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
AGC Gain Readout Register
AGCGAINR
Offset
Reset Value
AGC Gain Readout Register
0B2H
00H
8186('
,)*$,1
0,;*$,
1
U
U
Field
Bits
Type
Description
UNUSED
7:3
-
UNUSED
Reset: 00H
IF2GAIN
2:1
r
AGC IF2 Gain Readout
00B 0 dB
01B -15 dB
10B -30 dB
11B n.u.
Reset: 0H
MIX2GAIN
0
r
AGC MIX2 Gain Readout
0B
0 dB
1B
-15 dB
Reset: 0H
SPI Address Tracer Register
SPIAT
Offset
Reset Value
SPI Address Tracer Register
0B3H
00H
63,$7
U
Field
Bits
Type
Description
SPIAT
7:0
r
SPI Address Tracer, Readout of the last address of a SFR Register
written by SPI
Reset: 00H
SPI Data Tracer Register
Data Sheet
172
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
SPIDT
Offset
Reset Value
SPI Data Tracer Register
0B4H
00H
63,'7
U
Field
Bits
Type
Description
SPIDT
7:0
r
SPI Data Tracer, Readout of the last written data to a SFR Register
by SPI
Reset: 00H
SPI Checksum Register
SPICHKSUM
Offset
Reset Value
SPI Checksum Register
0B5H
00H
63,&+.680
UF
Field
Bits
Type
Description
SPICHKSUM
7:0
rc
SPI Checksum Readout
Reset: 00H
Serial Number Register 0
SN0
Offset
Reset Value
Serial Number Register 0
0B6H
00H
61
U
Data Sheet
173
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
Field
Bits
Type
Description
SN0
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
Serial Number Register 1
SN1
Offset
Reset Value
Serial Number Register 1
0B7H
00H
61
U
Field
Bits
Type
Description
SN1
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
Serial Number Register 2
SN2
Offset
Reset Value
Serial Number Register 2
0B8H
00H
61
U
Field
Bits
Type
Description
SN2
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
Serial Number Register 3
SN3
Offset
Reset Value
Serial Number Register 3
0B9H
00H
Data Sheet
174
V1.0, 2010-02-19
TDA5225
Appendix
Register Description
61
U
Field
Bits
Type
Description
SN3
7:0
r
Serial Number: SN(31:0) = SN3(MSB) & SN2 & SN1 & SN0(LSB)
Reset: 00H
RSSI Readout Register
RSSIRX
Offset
Reset Value
RSSI Readout Register
0BAH
00H
566,5;
U
Field
Bits
Type
Description
RSSIRX
7:0
r
RSSI value after averaging over 4 samples
Reset: 00H
RSSI Peak Memory Filter Readout Register
RSSIPMF
Offset
Reset Value
RSSI Peak Memory Filter Readout Register
0BBH
00H
566,30)
U
Field
Bits
Type
Description
RSSIPMF
7:0
r
RSSI Peak Memory Filter Level
Reset: 00H
Data Sheet
175
V1.0, 2010-02-19
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG