KSZ9031MNX Eval-Sckt Board Rev1.1 Schematic PDF

1
2
3
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KSZ9031MNX Evaluation-Socket Board Revision 1.1
D
REVISION HISTORY
DATE
D
Table of Contents
DESCRIPTION
REVISION
8/16/12
Initial Release
1.0
9/28/12
Changed U1 (KSZ9031MNX) pin 62 from AVDDH to NC.
1.1
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
01:
02:
03:
04:
05:
06:
07:
08:
Revision History
Board Block Diagram
KSZ9031MNX Device
GMII loopback / MII Port
RJ-45 / Pulse H5007NL Transformer
TDK TLA-7T101LF Transformer (option)
USB Port for MDC/MDIO Register Access
Power
C
C
B
B
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ9031MNX Evaluation-Socket Board
Size
Document Number
Rev
1.1
Revision History
Date:
1
2
3
4
Friday, September 28, 2012
Sheet
5
1
of
8
1
2
3
4
5
KSZ9031MNX EVALUATION-SOCKET BOARD - BLOCK DIAGRAM
D
D
6 MHz
XTAL
5V to 12V DC
INPUT
25 MHz
XTAL
1.8V / 2.5V
VDD I/O LDO
(option)
3.3V
LDO
1.2V core
LDO
PMOS
(1.2V option)
RESET
MDC / MDIO
Voltage Translator
(option)
USB Port
(MDC/MDIO PHY registers access)
MODE[3:0]
select
C
C
Magnetics
4 TX / RX pairs
KSZ9031MNX
64-pin QFN
Pulse H5007NL
(TDK option)
GMII / MII
Signals
GMII RX Signals
(Socket / Solder Mounting)
Port Status
LED[2:1]
Indicators
B
PHYAD[2:0]
config
GMII Loopback Jumpers
RJ-45 Jack
4 TX / RX pairs
LED_MODE
CLK125_EN
config
B
MII Signals
MDC / MDIO
MII Port Connector
(Receptacle - Male)
10Base-T /
100Base-TX /
1000Base-T
GMII TX Signals
Control Network
MDC / MDIO
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ9031MNX Evaluation-Socket Board
Size
Document Number
Rev
1.1
Board Block Diagram
Date:
1
2
3
4
Friday, September 28, 2012
Sheet
5
2
of
8
1
2
3
4
5
Strapping Pins for MODE Selection
DVDDH
Q1
PHY Hardware Reset
AVDDL_PMOS
S
AVDDH
AVDDL_PMOS
Q2
PCB heat sink
1x1 inch
copper ground
D
D
D
D
NO POP
4
6
5
2
1
R1
D1
10K
BAV16W-7 SOD-123
G
S
C1
C2
C3
LDO_O
47uF/16V TANT C
LDO_O output drive range
C5
For AVDDH = 3.3V, range is 0.85V to 2.8V
0.1uF
3
LDO_O
C4
10nF
10uF/16V TANT A
DVDDH
R3
10K
R4
10K
DVDDH
AVDDH
AVDDL_PLL
3X1
2
4
DVDDL
TP1
XI
(6)
DVDDH
(1.2V Digital)
CLK125_NDO
TP2
R7
1K
JP4
1
2
3
RXD2
MODE2
3X1
R6
1K
R5
10K
JP3
1
2
3
RXD3
MODE3
RESET_N
25MHz
22pF
JP2
1
2
3
TX_CLK
XO
C6
JP1
1
2
3
RXD1
MODE1
3X1
R8
1K
3X1
RXD0
MODE0
R9
1K
D
SW PUSHBUTTON
22pF
Y1
(1.2V Analog) (3.3V Analog)
1
3
+
(No longer use)
For AVDDH = 2.5V, range is 0.85V to 2.0V
AVDDL
DVDDH
R2
10K
S1
G
+
D
DVDDH
Active Low
D
D
1
FDT434PTAB
2
AVDDH
(3.3V Digital)
CLK125_NDO
XI
MODE[3:0]
Description
0000
0001
0010-0011
0100
0101-0110
0111
reserved
GMII / MII mode
reserved
NAND Tree mode
reserved
Chip Power Down
MODE[3:0]
Description
1000-1111
reserved
(1.2V Analog for PLL)
R10
R11
4.7K
4.7K
JP5
2
MDIO_USB
3
INT_N
R12
MDIO_MII
1
TP3
INT_N
MDIO_MII
(6)
MDIO_USB
(8)
JP6
3x1
12.1K
MDC_MII
1
2
MDC_USB
3
MDIO
MDC_MII
(6)
MDC_USB
(8)
3x1
MDC
COL
RX_CLK
Differential
Pairs
(4,5)
(4,5)
TXRXP_A
TXRXM_A
(4,5)
(4,5)
TXRXP_B
TXRXM_B
(4,5)
(4,5)
TXRXP_C
TXRXM_C
(4,5)
(4,5)
TXRXP_D
TXRXM_D
RX_ER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TXRXP_A
TXRXM_A
TXRXP_B
TXRXM_B
TXRXP_C
TXRXM_C
TXRXP_D
TXRXM_D
AVDDH
TXRXP_A
TXRXM_A
AVDDL
AVDDL
NC
TXRXP_B
TXRXM_B
AGNDH
TXRXP_C
TXRXM_C
AVDDL
AVDDL
TXRXP_D
TXRXM_D
AVDDH
Paddle Ground
(bottom of chip)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RX_DV
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Layout Johnstech LBD_64_QFN_8.0x8.0_0.4_6190
Socket Footprint for U1
LINK
CRS
(6)
COL
(6)
RX_CLK
(6)
RX_ER
(6)
RX_DV
(6)
C
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
RXD[0:7]
TX_EN
LED2
DVDDH
LED1 / PME_N1
DVDDL
TXD0
TXD1
TXD2
TXD3
DVDDL
TXD4
TXD5
TXD6
TXD7
DVDDH
TX_ER
GTX_CLK
+3.3V
LED
RX_CLK
RX_ER
DVDDH
RX_DV
RXD0
RXD1
DVDDL
RXD2
DVDDH
RXD3
RXD4
RXD5
DVDDL
RXD6
RXD7
TX_EN
KSZ9031MNX
64-pin QFN
Footprint for Johnstech socket to
support both socket and direct
PCB mounting for U1.
B
Jumper setting:
1-2 -> MDIO/MDC Management data to/fr MII connector
2-3 -> MDIO/MDC Management data to/fr USB port
CRS
AGNDH
ISET
NC
XI
XO
AVDDL_PLL
LDO_O
TX_CLK
RESET_N
CLK125_NDO
DVDDL
INT_N / PME_N2
COL
MDIO
MDC
CRS
C
U1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P_GND PADDLE
Place GND hole on solder side,
Center and connect to Paddle
Ground of U1.
RXD[0:7]
(6)
TX_EN
(6)
For KSZ9021GN footprint compatibility, KSZ9031MNX
* Pin 62 (not bonded out) can be tied to AVDDH power.
KSZ9031MNX
JP7
D2
R13
220
B
LED2_SINGLE
1
2
LED2
GTX_CLK
GTX_CLK
(6)
TX_ER
(6)
TXD[0:7]
(6)
3
LED
D3
R14
220
LED1_SINGLE
TX_ER
3x1
ACTIVITY
+3.3V
TXD[0:7]
D4
R15
220
1
2
3
4
Green
Red
JP8
LED2_DUAL
1
2
LED1_DUAL
Dialight 598-8610-207F / 1210 SMD
3x1
Jumper setting:
1-2 -> For Single LED mode
2-3 -> For Tri-color dual LED mode
Single LED Mode
Tri-color Dual LED Mode
Pins
[LED2, LED1]
Dual LED
Color
Description
[0, 1]
Solid Color : 1G Link
[toggling, 1]
Blinking :
[1, 0]
Solid Color : 100M Link
[1, toggling]
Blinking :
[0, 0]
Solid Color : 10M Link
[toggling, toggling]
Blinking :
[1, 1]
Link off
Activity (RX, TX)
Activity (RX, TX)
Activity (RX, TX)
LED1
3
Orange
A
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
Pin
LED2
Description
Strapping Pin for
LED Mode
Strapping Pin for
CLK125 Enable
DVDDH
1 : Link off
DVDDH
R16
10K
0 : Link on (any speed), solid color
LED1
Blinking : Activity (RX, TX)
Red
1
2
3
3X1
DVDDH
R17
10K
JP9
Green
Strapping Pins for PHY Address
JP10
1
2
3
CLK125_NDO
3X1
R21
1K
R18
10K
JP11
RX_DV
R22
1K
DVDDH
1
2
3
3X1
R19
10K
JP12
RX_CLK
R23
1K
DVDDH
1
2
3
3X1
R20
10K
JP13
LED2
R24
1K
1
2
3
3X1
A
LED1
R25
1K
CONFIDENTIAL & PROPRIETARY
Orange
LED_MODE
None
CLK125_EN
Pull-up: Enable 125MHz
clock on Pin 56
Pull-up: Single LED Mode
PHYAD2
PHYAD1
PHYAD0
PHY address bits [4:3] are always set to "00"
Title
KSZ9031MNX Evaluation-Socket Board
Size
Document Number
Rev
1.1
KSZ9031MNX Device
Date:
1
2
3
4
Friday, September 28, 2012
5
Sheet
3
of
8
1
2
3
4
5
All Jumpers:
1-2 for GMII mode to loopback
2-3 for MII mode to connector
* GTX_CLK (sourced by GMAC) in GMII Mode for 1000Mbps speed
* TX_CLK (sourced by KSZ9031MNX) in MII Mode for 10/100Mbps speed
JP14
(3)
D
RX_CLK
RX_CLK
R30
0
GMII_CLK
1
2
3
MII_RX_CLK
D
3x1
(3)
GTX_CLK
(3)
TX_CLK
GTX_CLK
R31
0
MII_TX_CLK
TX_CLK
R64
0
RN1
(3)
(3)
(3)
RX_ER
RX_ER
RX_DV
RXD[0:7]
JP16
1
2
3
4
5
6
7
8
RX_DV
RXD0
RXD1
RXD2
RXD3
16
15
14
13
12
11
10
9
1
2
3
3x1
GMII_DATA_ER
MII_RX_ER
JP17
1
2
3
3x1
GMII_DATA_DV
MII_RX_DV
JP18
R-PACK 0
1
2
3
GMII_DATA3
3x1
Place series
termination resistors
close to KSZ9031MNX/
MAC output pins, if
needed.
C
MII_RXD3
JP19
1
2
3
3x1
GMII_DATA2
MII_RXD2
JP20
1
2
3
GMII_DATA1
C
MII_RXD1
JP21
3x1
GMII_DATA0
1
2
3
MII_RXD0
3x1
RN2
(3)
(3)
(3)
TX_EN
TX_ER
TXD[0:7]
TX_EN
JP22
1
2
3
4
5
6
7
8
TX_ER
TXD3
TXD2
TXD1
TXD0
16
15
14
13
12
11
10
9
1
2
3
3x1
MII_TX_ER
JP23
1
2
3
3x1
MII_TX_EN
JP24
R-PACK 0
1
2
3
3x1
MII_TXD3
JP25
1
2
3
3x1
MII_TXD2
JP26
B
1
2
3
MII_TXD1
JP27
3x1
MDIO_MII
(3)
MDC_MII
(3)
(3)
MII_TXD0
J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
MII_RX_DV
MII_RX_CLK
MII_RX_ER
MII_TX_ER
MII_TX_CLK
MII_TX_EN
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
A
B
3x1
MII Port
(3)
1
2
3
COL
CRS
VCC
MDIO
MDC
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_CLK
RX_ER
TX_ER
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
COL
CRS
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
(3)
TXD[0:7]
(3) RXD[0:7]
TXD7
TXD6
TXD5
TXD4
R32
R33
R34
R35
0
0
0
0
RXD7
RXD6
RXD5
RXD4
R36
R37
R38
R39
0
0
0
0
GMII_DATA7
GMII_DATA6
GMII_DATA5
GMII_DATA4
A
CONFIDENTIAL & PROPRIETARY
Male MII connector MDS-40-M/M-5-C1
Title
KSZ9031MNX Evaluation-Socket Board
Size
Document Number
Rev
1.1
GMII Loopback / MII Port
Date:
1
2
3
4
Friday, September 28, 2012
Sheet
5
4
of
8
1
2
3
4
5
D
D
Differential
Pair
Differential
Pair
(3,5)
TXRXP_A
12
TD4-
MX4-
13
(3,5)
TXRXM_A
11
TD4+
MX4+
14
10
TCT4
MCT4
15
ENET_CGND
75
10
0.1uF
1
DA+
2
DA-
3
DB+
4
DB-
5
DC+
6
DC-
7
DD+
8
DD-
Differential
Pair
TXRXP_B
TD3-
MX3-
16
C
TXRXM_B
TD3+
MX3+
17
RJ45 Belfuse SS-6488S-A-FLS-50
75
C8
TCT3
Differential
Pair
C
RJ1
7
TCT3
MCT3
18
MCT_CHASSIS
R27
Differential
Pair
TXRXP_C
6
TD2-
MX2-
19
(3,5)
TXRXM_C
5
TD2+
MX2+
20
9
(3,5)
NC
0.1uF
CGND
(3,5)
8
11
(3,5)
9
NC
MCT_CHASSIS
R26
12
TCT4
CGND
C7
Differential
Pair
ENET_CGND
75
C9
TCT2
Differential
Pair
B
MCT_CHASSIS
4
TCT2
MCT2
21
C10
R28
MCT_CHASSIS
1000pF / 2kV
0.1uF
C11
(3,5)
TXRXP_D
3
TD1-
MX1-
22
(3,5)
TXRXM_D
2
TD1+
MX1+
23
B
0.1uF 0805
Differential
Pair
C12
0.1uF 0805
C13
0.1uF 0805
FB1
1
75
C14
TCT1
1
TCT1
MCT1
24
R29
2
FBEAD
MCT_CHASSIS
0.1uF
GND
ENET_CGND
STEWARD
HI1206N101R-00
T1
PULSE H5007NL Transformer
Place FB1 ground bridge for ENET_CGND to
GND (signal ground) return close to GND at
input power to board.
A
A
(5)
TCT4
TCT4
(5)
TCT3
TCT3
(5)
TCT2
TCT2
(5)
TCT1
TCT1
CONFIDENTIAL & PROPRIETARY
Center tap connections to
TDK Transformer option
Title
KSZ9031MNX Evaluation-Socket Board
Size
Document Number
Rev
1.1
RJ-45 Connector / Pulse H5007NL Transformer
Date:
1
2
3
4
Friday, September 28, 2012
Sheet
5
5
of
8
5
4
3
2
1
TDK TLA-7T101LF Transformer Option
TDK Transformer has the same pinouts as the
Pulse H5007NL (T1), but is narrower.
Layout TDK Transformer as detailed on this page.
D
(3,4)
TXRXP_A
12
TD4-
MX4-
13
(3,4)
TXRXM_A
11
TD4+
MX4+
14
10
TCT4
MCT4
15
TCT4
(3,4)
TXRXP_B
9
TD3-
MX3-
16
(3,4)
TXRXM_B
8
TD3+
MX3+
17
7
TCT3
MCT3
18
D
When populating TDK Transformer, add rework wires to
connect the corresponding pads between TDK Transformer
and Pulse Transformer on the RJ-45 Jack side.
C
C
TCT3
KSZ9031MNX PHY Side
RJ-45 Jack Side
Overlay these pins with those
of Pulse H5007NL Transformer (T1)
Place PCB pads only for these pins
(3,4)
TXRXP_C
6
TD2-
MX2-
19
(3,4)
TXRXM_C
5
TD2+
MX2+
20
4
TCT2
MCT2
21
TCT2
B
B
(3,4)
TXRXP_D
3
TD1-
MX1-
22
(3,4)
TXRXM_D
2
TD1+
MX1+
23
1
TCT1
MCT1
24
TCT1
T2
TDK TLA-7T101LF Transformer
A
A
(4)
TCT4
TCT4
(4)
TCT3
TCT3
(4)
TCT2
TCT2
(4)
TCT1
TCT1
CONFIDENTIAL & PROPRIETARY
Center tap connections to
Pulse H5007NL Tranformer
Title
KSZ9031MNX Evaluation-Socket Board
Size
Document Number
Rev
1.1
TDK TLA-7T101LF Transformer (option)
Date:
5
4
3
2
Friday, September 28, 2012
Sheet
1
6
of
8
5
DC_IN
4
+(5V to 12V)
DC INPUT
3
STEWARD
HI1206N101R-00
U5
MIC5207-5.0YM5
C66
C65
+
10uF/16V TANT A
0.1uF
1
VIN
2
GND
3
EN
VOUT
5
BYP/ADJ
4
2
5V_USB
U6 - FTDI FT2232D
Decouple Pins (3, 42)
FB9
1
C67
C68
10uF/16V TANT A
0.1uF
1
USB Port - MDC/MDIO Register Access
2
FBEAD
+
C69
C70
C71
10uF/16V TANT A
0.1uF
0.1uF
+
C72
D
D
470pF
C73
STEWARD
HI1206N101R-00
+3.3V
27pF
XTIN
3.3V_USB
U6 - FTDI FT2232D
Decouple Pins (14, 31)
FB10
Y2
MIC5207-5.0YM5 has very low dropout voltage
(typically 165mV @ 150mA).
C75
1
2
FBEAD
6MHz
27pF
C74
C76
C77
10uF/16V TANT A
0.1uF
0.1uF
+
XTOUT
FTDI FT2232D can operate down to +4.35V for
its 5V input power (5V_USB).
C78
5V_USB
3.3V_USB
0.1uF
USB_5V
1K
R49
R50
470
C
C
3.3V_USB
R51
MDC/MDIO Voltage Translator option when DVDDH=1.8V or 2.5V
4.7K
R52
R54
R53
10K
10K
10K
1
2
3
RESET#_USB
4
RSTOUT#
5
3V3OUT
6
USBDP
7
USBDM
8
9
10
11
12
C79
33nF
EESK
EEDATA
VCC
RESET#
RSTOUT#
3V3OUT
USBDP
USBDM
GND
NOT_USED
GPIOH3
GPIOH2
DVDDH
NC
NC
GND
NC
NC
VCCIOB
NC
NC
NC
NC
NOT_USED
GND
36
35
34
33
32
31
30
29
28
27
26
25
U7
R55
R56
R57
200K
4.7K
4.7K
TI PCA9306
R58
1
GND
2
VREF1
MDC_USB
3
SCL1
SCL2
6
MDC_USB_IC
MDIO_USB
4
SDA1
SDA2
5
MDIO_USB_IC
R59
4.7K
10K
EN
8
VREF2
7
C80
VSSOP-DCU
GPIOH1
VCCIOA
GPIOH0
GPIOL3
GPIOL2
GND
GPIOL1
GPIOL0
TMS/CS
TDO/D1
TDI/D0
TCK/SK
USB_5V
B
0.1uF
2
13
14
15
16
17
18
19
20
21
22
23
24
B
3.3V_USB
FTDI FT2232D
EECS
TEST
AVCC
AGND
XTOUT
XTIN
VCC
PWREN#
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
U6
FB11
CN1
Jumper setting:
ON: DVDDH=3.3V without MDC/MDIO voltage translator option
OFF: DVDDH=1.8V or 2.5V with MDC/MDIO voltage translator option
FBEAD
1
CN-USB
R60
1.5K
RSTOUT#
MDC_USB_IC
1
2
3
4
R61
R62
27
27
USBDM
USBDP
MDIO_USB_IC
R63
6
5
STEWARD
HI1206N101R-00
JP31
Jumper
2
MDC_USB
JP32
Jumper
2
MDIO_USB
1
1
MDC_USB
(3)
MDIO_USB
(3)
0
STEWARD
HI1206N101R-00
A
A
FB12
1
2
USB Configuration
FBEAD
CONFIDENTIAL & PROPRIETARY
* Self Power
USB_CGND
* Multi-Protocol Synchronous Serial Engine (MPSSE) Mode
Title
KSZ9031MNX Evaluation-Socket Board
Size
Document Number
Rev
1.1
USB Port for MDC/MDIO Register Access
Date:
5
4
3
2
Friday, September 28, 2012
Sheet
1
7
of
8
1
2
3
4
5
AVDDL is the feedback for the KSZ9031MNX on-chip LDO controller.
Change FB2 from ferrite bead to 0 Ohm when PMOS (Q1) is populated.
1.2V Power option
Do not populate FB3 if KSZ9031MNX generates 1.2V with MOSFET
1.2V_EXT
STEWARD
HI1206N101R-00
1.2V_EXT
AVDDL
AVDDL
TP4
FB2
1
AVDDL
U1 - KSZ9031MNX
Decouple Pins 4, 5, 12, 13
Additional decoupling
for AVDDL plane
2
FBEAD
C15
C16
10uF/16V TANT A
0.1uF
C17
AVDDL
+
C18
C19
C20
C21
C22
+
C23
+
47uF/16V TANT C
10nF 0402
10nF 0402 10nF 0402
10nF 0402
10uF/16V TANT A
0.1uF 0402
D
D
+3.3V
STEWARD
HI1206N101R-00
U2
MIC49150WR / 5-Pin S-PAK
4
VIN
2
VBIAS
C25
+
5
ADJ
1
FB3
1
R40
STEWARD
HI1206N101R-00
2
AVDDL_PMOS
FBEAD
C27
AVDDL_PLL
C26
+
1.50K
R41
0.1uF
10uF/16V TANT A
3
0.1uF
10uF/16V TANT A
VOUT
GND
C24
R42
NC
0 1206
1
U1 - KSZ9031MNX
Decouple Pin 59
2
FBEAD
C28
AVDDL_PLL
TP5
FB4
C29
AVDDL_PLL
+
C30
C31
+
3.92K
47uF/16V TANT C
Connect TAB of
S-PAK to ground.
10uF/16V TANT A
0.1uF 0402
10nF 0402
VOUT = 0.9 X [ 1 + ( R40 / R42) ]
STEWARD
HI1206N101R-00
VDD I/O (DVDDH) Test Option
DVDDL
1
internal_test
U1 - KSZ9031MNX
Decouple Pins 20, 25, 36, 42, 54, 55
TP6
FB5
Provides test options for KSZ9031MNX VDD I/O power (DVDDH plane); Set by JP30.
DVDDL
2
C32
FBEAD
2.5V if only JP28 is ON
1.8V if only JP29 is ON
C33
DVDDL
+
C34
C35
C36
C37
C38
C39
C40
47uF/16V TANT C
10nF 0402
10nF 0402
10nF 0402
10nF 0402
10nF 0402
10nF 0402
+
10uF/16V TANT A
0.1uF
+3.3V
JP28
2.5V
U3
Jumper
2
GND
3
EN
C42
+
0.1uF
10uF/16V TANT A
VIN
VOUT
DVDDL
Jumper
Additional decoupling
for DVDDL plane
2
2
1
JP29
1.8V
MIC5207-2.5YM5
C41
1
C
1
C
5
R43
R44
2.43K
5.6K
C44
C43
+
BYP/ADJ
4
C45
C46
+
10uF/16V TANT A
0.1uF
10uF/16V TANT A
C47
R45
470pF
2.49K
STEWARD
HI1206N101R-00
internal_test
FB6
1
2
0.1uF 0402
Jumper setting:
1-2 -> To select internal test
2-3 -> To select 3.3V for normal operation
FBEAD
For Adjustable Voltage Regulator (MIC5207YM5)
option, use following formula to set VOUT.
JP30
1
VOUT = 1.24 X [ 1 + ( R45 / R43 or R44 ) ]
2
3
3X1
STEWARD
HI1206N101R-00
+3.3V
DVDDH
DVDDH
TP7
FB7
+(5V to 12V) DC Input
1
FBEAD
B
C48
C49
10uF/16V TANT A
0.1uF
DVDDH
+
DC_IN
U4
U1 - KSZ9031MNX
Decouple Pins 18, 30, 40, 46
2
C50
C51
C52
C53
C54
47uF/16V TANT C
10nF 0402
10nF 0402
10nF 0402
10nF 0402
B
+
+3.3V
3
2
1
+
POWER JACK
C55
C58
220uF Elect
0.1uF
1
EN
2
VIN
VOUT
4
ADJ
5
R46
C57
C56
+
2.49K
47uF/16V TANT C
3
DC_IN
GND
MIC29302WU / TO-263-5
J2
0.1uF
STEWARD
HI1206N101R-00
R47
+(5V to 12V)
DC INPUT
AVDDH
AVDDH
TP8
FB8
1.50K
1
FBEAD
VOUT = 1.24 X [ 1 + ( R46 / R47 ) ]
U1 - KSZ9031MNX
Decouple Pins 1, 16, 62
2
C59
C60
10uF/16V TANT A
0.1uF
AVDDH
C62
C63
C64
10nF 0402
10nF 0402
10nF 0402
C61
+
+
47uF/16V TANT C
+3.3V
R48
A
A
2
220
Place GND test points evenly across PCB.
D5
1
POWER_ON LED
Board
TP9
TP10
GND
GND
TP11
GND
CONFIDENTIAL & PROPRIETARY
TP12
GND
Title
KSZ9031MNX Evaluation-Socket Board
Size
Document Number
Rev
1.1
Power
Date:
1
2
3
4
Friday, September 28, 2012
5
Sheet
8
of
8