1 2 3 4 5 KSZ9031RNX Evaluation-Socket Board Revision 1.1 D REVISION HISTORY DATE DESCRIPTION REVISION 6/15/12 Initial Release 1.0 8/16/12 Added note to change FB2 from ferrite bead to 0 Ohm when PMOS (Q2) is populated. 1.1 Added LDO_O output drive range for PMOS gate input. Added note to place copper ground PCB heat sink for PMOS (Q2). Changed U1 (KSZ9031RNX) pin 13 from VSS_PS to NC and pin 47 from AVDDH to NC. 9/28/12 D Table of Contents PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE 01: 02: 03: 04: 05: 06: 07: 08: Revision History Board Block Diagram KSZ9031RNX Device LED Indicators & Mode RJ-45 / Pulse H5007NL Transformer TDK TLA-7T101LF Transformer (option) USB Port for MDC/MDIO Register Access Power 1.2 C C B B A A CONFIDENTIAL & PROPRIETARY Title KSZ9031RNX Evaluation-Socket Board Size Document Number Rev 1.2 Revision History Date: 1 2 3 4 Friday, September 28, 2012 Sheet 5 1 of 8 1 2 3 4 5 KSZ9031RNX EVALUATION-SOCKET BOARD - BLOCK DIAGRAM D D 5V LDO (for USB) 5V to 12V DC INPUT 25 MHz XTAL 1.2V core LDO 3.3V LDO PMOS (1.2V option) RESET 2.5V VDDIO LDO (test option) MODE[3:0] select USB Port (MDC/MDIO PHY Register Access) Voltage Translator C C 10Base-T / 100Base-TX / 1000Base-T RJ-45 Jack 4 TX / RX pairs Magnetics Pulse H5007NL RGMII Loopback (resistor network) MDC / MDIO 4 TX / RX pairs KSZ9031RNX 48-pin QFN RGMII Signals (TDK option) (Socket / Solder Mounting) Port Status LED Indicators & mode select B PHYAD[2:0] config B A A CONFIDENTIAL & PROPRIETARY Title KSZ9031RNX Evaluation-Socket Board Size Document Number Rev 1.2 Board Block Diagram Date: 1 2 3 4 Friday, September 28, 2012 Sheet 5 2 of 8 1 2 3 Q2 NC D D D D 4 6 5 2 1 AVDDL_PMOS Strapping Pins DVDDH SOT-223 FDT434P AVDDH TAB S PHY Hardware Reset AVDDL_PMOS Active Low D D S C97 PCB heat sink 1x1 inch copper ground C4 22pF XO (no longer use) C1 C2 0.1uF 10nF R1 D7 10K BAV16W-7 SOD-123 1 3 C3 1 2 3 2 4 3X1 + XI For AVDDH = 3.3V, range is 0.85V to 2.8V CLK125_NDO R12 TP4 DVDDH 12.1K INT_N DVDDL INT_N MDIO XI XO AVDDL_PLL LDO_O RESET_N INT_N DVDDH R13 1K Place this GND test point on Solder Side; Center and connect to Paddle Ground of U1. MDIO MDC P_GND Differential Pairs TXRXP_A TXRXM_A (5,6) (5,6) (5,6) (5,6) TXRXP_B TXRXM_B TXRXP_C TXRXM_C (5,6) (5,6) TXRXP_D TXRXM_D TXRXP_B TXRXM_B TXRXP_C TXRXM_C TXRXP_D TXRXM_D R8 1K D R9 1K AVDDH TXRXP_A TXRXM_A AVDDL TXRXP_B TXRXM_B TXRXP_C TXRXM_C AVDDL TXRXP_D TXRXM_D AVDDH U1 KSZ9031RNX MODE1 MODE0 Description MODE[3:0] Description (7) MDC (7) reserved 1000 reserved 0001 reserved 1001 reserved 0010 reserved 1010 reserved 0011 reserved 1011 reserved 0100 NAND Tree mode 1100 Advertise 1000BT full-duplex only (RGMII) 0101 reserved 1101 Advertise 1000BT full- and half-duplex only (RGMII) 0110 reserved 1110 Advertise all capabilites, except 1000BT half-duplex (RGMII) 0111 Chip Power Down 1111 Advertise all capabilites (RGMII) RGMII Clock Delay (test option) 48 47 46 45 44 43 42 41 40 39 38 37 MDIO 0000 Trace Delay is 180ps/1000mil for stripline layer (inside PCB layer) for FR-4 PCB. RGMII Loopback (Default: select KSZ9031RNX on-chip data-to-clock skew and no PCB skew) KSZ9031RNX 48-pin QFN Paddle Ground (bottom of chip) MDC RX_CLK DVDDH RX_DV RXD0 RXD1 DVDDL VSS RXD2 RXD3 DVDDL TX_EN 36 35 34 33 32 31 30 29 28 27 26 25 Place R144 on PCB Component Side next to R14. Place R145 on PCB Solder Side next to R18. MDC RX_CLK RX_DV RXD0 RXD1 Place on PCB Component Side RXD2 RXD3 RX_CLK R14 RX_CLK R144 NC 0402 GTX_CLK R145 NC 0402 RXCLK_TXCLK 49.9 0402 TP34 TP35 TP37 TP36 10000mils TX_EN RX_DV R16 49.9 0402 RXDV_TXEN RXD0 RXD1 RXD2 RXD3 R136 R137 R138 R139 49.9 49.9 49.9 49.9 RXD0_TXD0 RXD1_TXD1 RXD2_TXD2 RXD3_TXD3 TX_EN R17 0 0402 RXDV_TXEN GTX_CLK R18 0 0402 RXCLK_TXCLK TXD3 TXD2 TXD1 TXD0 R140 R141 R142 R143 0 0 0 0 RXD3_TXD3 RXD2_TXD2 RXD1_TXD1 RXD0_TXD0 2500mils 0402 0402 0402 0402 13 14 15 16 17 18 19 20 21 22 23 24 Modify Universal Footprint for Yamaichi/Johnstech Socket to support both socket and direct PCB mounting for U1. MODE2 C NC DVDDL LED2 DVDDH LED1 / PME_N1 DVDDL TXD0 TXD1 TXD2 TXD3 DVDDL GTX_CLK (5,6) (5,6) R7 1K RXD0 3X1 (Select PCB data-to-clock skew and program KSZ9031RNX for no on-chip skew) ISET NC XI XO AVDDL_PLL LDO_O RESET_N CLK125_NDO DVDDH DVDDL INT_N / PME_N2 MDIO 49 TP33 1 2 3 4 5 6 7 8 9 10 11 12 R6 1K 3X1 1 2 3 RXD1 R11 (4) 4.7K TXRXP_A TXRXM_A 3X1 1 2 3 RXD2 DVDDH MODE[3:0] CLK125_NDO GND 1 2 3 RXD3 MODE3 For AVDDH = 2.5V, range is 0.85V to 2.0V C JP4 LDO_O output drive range For KSZ9021RN footprint compatibility, KSZ9031RNX * Pin 13 (not bonded out) can be tied to PCB signal ground. * Pin 47 (not bonded out) can be tied to AVDDH power. AVDDL R5 10K JP3 10uF/16V TANT B 25MHz AVDDH DVDDH R4 10K JP2 S1 Y1 22pF DVDDH R3 10K JP1 SW PUSHBUTTON C5 DVDDH R2 10K RESET_N LDO_O 47uF/16V TANT C LDO_O D G 3 + DVDDH 2 G 5 1 Q1 AVDDH 4 GTX_CLK B B Layout Yamaichi IC507-048-004-xxx Socket Footprint for U1 Route these RGMII nets on layer 3. (4) LED[1:2] TXD3 TXD2 TXD1 TXD0 LED[1:2] LED2 LED1 0402 0402 0402 0402 Place on PCB Solder Side Test options (no longer use) Place U11 and U12 at the pins of T1 (Pulse H5007NL). Strapping Pins AVDDH A TXRXP_A TXRXM_A TXRXP_B TXRXM_B AVDDH 1 2 3 4 5 6 7 8 U11 U12 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 16 15 14 13 12 11 10 9 TXRXP_A TXRXM_A TXRXP_B TXRXM_B TXRXP_C TXRXM_C TXRXP_D TXRXM_D 1 2 3 4 5 6 7 8 NC NC NC NC NC NC NC NC DVDDH NC NC NC NC NC NC NC NC 16 15 14 13 12 11 10 9 TXRXP_C TXRXM_C R113 10K JP16 R152 NC NC 3X1 RX_DV R114 1K DVDDH R117 10K JP19 1 2 3 TXRXP_D TXRXM_D R151 DVDDH R24 10K JP9 1 2 3 3X1 RX_CLK R121 1K DVDDH R25 10K JP10 1 2 3 LED2 3X1 R33 1K A 1 2 3 3X1 LED1 R34 1K CONFIDENTIAL & PROPRIETARY Title CLK125_EN PHYAD2 PHYAD1 KSZ9031RNX Evaluation-Socket Board PHYAD0 Size Document Number Rev 1.2 KSZ9031RNX Device Date: 1 2 3 4 Friday, September 28, 2012 5 Sheet 3 of 8 5 4 3 2 1 Strapping Pin Single LED Mode Pin Description DVDDH LED2 D LED1 1 : Link off R118 10K 0 : Link on (any speed), solid color JP20 Blinking : Activity (RX, TX) 1 2 3 3X1 D Single LED Mode CLK125_NDO R122 1K CLK125_NDO (3) Tri-color Dual LED Mode +3.3V LED MODE LED D2 R146 220 LED2_SINGLE LED D1 R147 220 LED1_SINGLE C C JP26 LED2_SINGLE LED2_DUAL 1 2 3 LED[1:2] 3X1 LED2 Tri-color Dual LED Mode (3) JP27 Pins [LED2, LED1] LED1_SINGLE Description LED1_DUAL B LED[1:2] LED1 [0, 1] Solid Color : 1G Link [toggling, 1] Blinking : 1 2 3 3X1 Activity (RX, TX) [1, 0] Solid Color : 100M Link [1, toggling] Blinking : Activity (RX, TX) [0, 0] Solid Color : 10M Link [toggling, toggling] Blinking : [1, 1] Link off Activity (RX, TX) Green Red B Orange +3.3V R148 470 D10 A 1 2 3 4 Green LED2_DUAL A LED1_DUAL Red CONFIDENTIAL & PROPRIETARY Dialight 598-8610-207F / 1210 SMD Title KSZ9031RNX Evaluation-Socket Board Size Document Number Rev 1.2 LED Indicators & Mode Date: 5 4 3 2 Friday, September 28, 2012 Sheet 1 4 of 8 1 2 3 4 5 D D Differential Pair Differential Pair (3,6) TXRXP_A 12 TD4- MX4- 13 (3,6) TXRXM_A 11 TD4+ MX4+ 14 10 TCT4 MCT4 15 ENET_CGND 75 10 0.1uF 1 DA+ 2 DA- 3 DB+ 4 DB- 5 DC+ 6 DC- 7 DD+ 8 DD- Differential Pair TXRXP_B TD3- MX3- 16 C TXRXM_B TD3+ MX3+ 17 RJ45 Belfuse SS-6488S-A-FLS-50 75 C9 TCT3 Differential Pair C RJ1 7 TCT3 MCT3 18 MCT_CHASSIS R91 Differential Pair TXRXP_C 6 TD2- MX2- 19 (3,6) TXRXM_C 5 TD2+ MX2+ 20 9 (3,6) NC 0.1uF CGND (3,6) 8 11 (3,6) 9 NC MCT_CHASSIS R90 12 TCT4 CGND C7 Differential Pair ENET_CGND 75 C11 TCT2 Differential Pair B MCT_CHASSIS 4 TCT2 MCT2 21 R92 C96 MCT_CHASSIS 1000pF / 2kV 0.1uF C13 (3,6) TXRXP_D 3 TD1- MX1- 22 (3,6) TXRXM_D 2 TD1+ MX1+ 23 B 0.1uF 0805 Differential Pair C14 0.1uF 0805 C16 0.1uF 0805 FB14 1 75 C15 TCT1 1 TCT1 MCT1 24 R93 2 FBEAD MCT_CHASSIS 0.1uF ENET_CGND STEWARD HI1206N101R-00 T1 PULSE H5007NL Transformer Place FB14 ground bridge for ENET_CGND to GND (signal ground) return close to GND at input power to board. A A (6) TCT4 TCT4 (6) TCT3 TCT3 (6) TCT2 TCT2 (6) TCT1 TCT1 CONFIDENTIAL & PROPRIETARY Center tap connections to TDK Transformer option Title KSZ9031RNX Evaluation-Socket Board Size Document Number Rev 1.2 RJ-45 Connector / Pulse H5007NL Transformer Date: 1 2 3 4 Friday, September 28, 2012 Sheet 5 5 of 8 5 4 3 2 1 TDK TLA-7T101LF Transformer Option TDK Transformer has the same pinouts as the Pulse H5007NL (T1), but is narrower. Layout TDK Transformer as detailed on this page. D (3,5) TXRXP_A 12 TD4- MX4- 13 (3,5) TXRXM_A 11 TD4+ MX4+ 14 10 TCT4 MCT4 15 TCT4 (3,5) TXRXP_B 9 TD3- MX3- 16 (3,5) TXRXM_B 8 TD3+ MX3+ 17 7 TCT3 MCT3 18 D When populating TDK Transformer, add rework wires to connect the corresponding pads between TDK Transformer and Pulse Transformer on the RJ-45 Jack side. C C TCT3 KSZ9031RNX PHY Side RJ-45 Jack Side Overlay these pins with those of Pulse H5007NL Transformer (T1) Place PCB pads only for these pins (3,5) TXRXP_C 6 TD2- MX2- 19 (3,5) TXRXM_C 5 TD2+ MX2+ 20 4 TCT2 MCT2 21 TCT2 B B (3,5) TXRXP_D 3 TD1- MX1- 22 (3,5) TXRXM_D 2 TD1+ MX1+ 23 1 TCT1 MCT1 24 TCT1 T2 TDK TLA-7T101LF Transformer A A (5) TCT4 TCT4 (5) TCT3 TCT3 (5) TCT2 TCT2 (5) TCT1 TCT1 CONFIDENTIAL & PROPRIETARY Center tap connections to Pulse H5007NL Tranformer Title KSZ9031RNX Evaluation-Socket Board Size Document Number Rev 1.2 TDK TLA-7T101LF Transformer (option) Date: 5 4 3 2 Friday, September 28, 2012 Sheet 1 6 of 8 5 4 3 2 1 USB Port - MDC/MDIO Register Access DC_IN +(5V to 12V) DC INPUT STEWARD HI1206N101R-00 U9 MIC5207-5.0YM5 C115 C116 + 10uF/16V TANT B D 1 VIN 2 GND 3 0.1uF EN VOUT 5V_USB U8 - FTDI FT2232D Decouple Pins (3, 42) FB10 1 5 C118 2 FBEAD C119 + BYP/ADJ 4 C103 C104 C105 10uF/16V TANT B 0.1uF 0.1uF + 10uF/16V TANT B 0.1uF D C117 470pF STEWARD HI1206N101R-00 +3.3V C102 27pF 3.3V_USB U8 - FTDI FT2232D Decouple Pins (14, 31) FB11 XTIN 1 2 FBEAD Y2 MIC5207-5.0YM5 has very low dropout voltage (typically 165mV @ 150mA). 6MHz C106 27pF C108 C109 C110 10uF/16V TANT B 0.1uF 0.1uF + XTOUT FTDI FT2232D can operate down to +4.35V for its 5V input power (5V_USB). C107 5V_USB 3.3V_USB 0.1uF C USB_5V C R123 R124 470 1K R125 4.7K 48 47 46 45 44 43 42 41 40 39 38 37 R127 10K 10K C111 33nF B FTDI FT2232D 3.3V_USB EECS TEST AVCC AGND XTOUT XTIN VCC PWREN# NC NC NC NC R126 RESET#_USB RSTOUT# 3V3OUT USBDP USBDM MDC/MDIO Voltage Translator option U8 3.3V_USB 1 2 3 4 5 6 7 8 9 10 11 12 EESK EEDATA VCC RESET# RSTOUT# 3V3OUT USBDP USBDM GND NOT_USED GPIOH3 GPIOH2 DVDDH NC NC GND NC NC VCCIOB NC NC NC NC NOT_USED GND 36 35 34 33 32 31 30 29 28 27 26 25 3.3V_USB U13 R128 R153 R154 10K 4.7K 4.7K R129 3.3V_USB STEWARD HI1206N101R-00 2 R157 4.7K 4.7K 1 GND 2 VREF1 EN 8 VREF2 7 MDC 3 SCL1 SCL2 6 MDC_USB MDIO 4 SDA1 SDA2 5 MDIO_USB VSSOP-DCU B C126 0.1uF 13 14 15 16 17 18 19 20 21 22 23 24 10K R156 200K TI PCA9306 GPIOH1 VCCIOA GPIOH0 GPIOL3 GPIOL2 GND GPIOL1 GPIOL0 TMS/CS TDO/D1 TDI/D0 TCK/SK USB_5V R155 FB12 CN1 FBEAD 1 CN-USB 1 2 3 4 R131 R132 R133 27 0805 27 0805 1.5K RSTOUT# MDC_USB USBDM USBDP MDIO_USB Jumper 2 MDC JP22 Jumper 2 MDIO 1 MDC (3) MDIO (3) 0 6 5 R130 JP21 1 A TP24 STEWARD HI1206N101R-00 CONFIDENTIAL & PROPRIETARY GND FB13 1 A USB Configuration 2 * Self Power FBEAD USB_CGND Title * Multi-Protocol Synchronous Serial Engine (MPSSE) Mode KSZ9031RNX Evaluation-Socket Board Size Document Number Rev 1.2 USB Port for MDC/MDIO Register Access Date: 5 4 3 2 Friday, September 28, 2012 Sheet 1 7 of 8 1 2 3 4 1.2V Power option Do not populate this LDO circuit if KSZ9031RNX generates 1.2V with MOSFET 1.2V_EXT STEWARD HI1206N101R-00 1.2V_EXT AVDDL AVDDL U1 - KSZ9031RNX Decouple Pins 4, 9 TP12 FB2 1 2 FBEAD C53 C54 10uF/16V TANT B 0.1uF AVDDL + D +3.3V MIC49150WR / 5-Pin S-PAK VIN 2 VBIAS 5 ADJ 1 C55 C56 47uF/16V TANT C 10nF 0402 10nF 0402 D FB6 1 R95 2 FBEAD C86 STEWARD HI1206N101R-00 AVDDL_PMOS C89 + AVDDL_PLL 1.50K R78 NC/0 1206 1 AVDDL_PLL U1 - KSZ9031RNX Decouple Pin 44 TP15 FB4 0.1uF 10uF/16V TANT B 3 0.1uF 10uF/16V TANT B VOUT GND 4 C88 + C99 + STEWARD HI1206N101R-00 U5 C85 5 AVDDL is the feedback for the KSZ9031RNX on-chip LDO controller. Change FB2 from ferrite bead to 0 Ohm when PMOS (Q2) is populated. 2 R96 FBEAD C69 3.92K AVDDL_PLL + Connect TAB of S-PAK to ground. C70 C71 C72 10uF/16V TANT B 0.1uF 0402 10nF 0402 + 47uF/16V TANT C VOUT = 0.9 X [ 1 + ( R95 / R96) ] STEWARD HI1206N101R-00 2.5V Power (test option) DVDDL 1 U1 - KSZ9031RNX Decouple Pins 14, 18, 23, 26, 30, 39 TP14 FB3 Provides 2.5V option for KSZ9031RNX VDDIO power (DVDDH plane); Set by JP23. DVDDL 2 FBEAD C60 C61 10uF/16V TANT B 0.1uF DVDDL + C +3.3V C101 C62 C63 C64 C65 C66 C125 47uF/16V TANT C 10nF 0402 10nF 0402 10nF 0402 10nF 0402 10nF 0402 10nF 0402 + C +2.5V U10 MIC5207-2.5YM5 C120 1 VIN 2 GND 3 EN C121 + 0.1uF 10uF/16V TANT B VOUT 5 BYP/ADJ 4 R149 C123 C124 + NC / 1.00K C122 R150 470pF NC / 1.00K +2.5V 0.1uF 10uF/16V TANT B STEWARD HI1206N101R-00 FB15 1 2 FBEAD JP23 1 For Adjustable Voltage Regulator (MIC5207YM5) option, use following formula to set VOUT. VOUT = 1.24 X [ 1 + ( R150 / R149 ) ] 2 3 3X1 +3.3V STEWARD HI1206N101R-00 DVDDH 1 DVDDH TP16 FB5 U1 - KSZ9031RNX Decouple Pins 16, 34, 40 2 FBEAD C74 C75 10uF/16V TANT B 0.1uF DVDDH + +(5V to 12V) DC Input C98 C76 C77 C78 47uF/16V TANT C 10nF 0402 10nF 0402 10nF 0402 + B B DC_IN U7 +3.3V VIN + POWER JACK C93 1 EN 2 VIN C95 220uF Elect VOUT 4 ADJ 5 R88 0.1uF C92 C94 + STEWARD HI1206N101R-00 AVDDH 2.49K 47uF/16V TANT C 3 3 2 1 GND MIC29302WU / TO-263-5 J13 1 AVDDH TP7 FB1 0.1uF U1 - KSZ9031RNX Decouple Pins 1, 12, 47 2 R89 FBEAD +(5V to 12V) DC INPUT 1.50K C39 C40 10uF/16V TANT B 0.1uF AVDDH C41 C42 C43 10nF 0402 10nF 0402 10nF 0402 C100 + + 47uF/16V TANT C VOUT = 1.24 X [ 1 + ( R88 / R89 ) ] +3.3V R87 A A 2 220 Place GND test points evenly across PCB. D8 1 POWER_ON LED TP17 Board GND TP18 GND TP19 GND CONFIDENTIAL & PROPRIETARY TP20 GND Title KSZ9031RNX Evaluation-Socket Board Size Document Number Rev 1.2 Power Date: 1 2 3 4 Friday, September 28, 2012 5 Sheet 8 of 8