KSZ8061MNX Evaluation Board User's Guide

KSZ8061MNX
Evaluation Board
User’s Guide
 2016 Microchip Technology Inc.
DS50002449A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2016, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0359-3
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2016 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS50002449A-page 2
Object of Declaration: KSZ8061MNX Evaluation Board
 2016 Microchip Technology Inc.
DS50002449A-page 3
NOTES:
DS50002449A-page 4
 2016 Microchip Technology Inc.
KSZ8061MNX EVALUATION
BOARD USER’S GUIDE
Table of Contents
Preface ........................................................................................................................... 7
Introduction............................................................................................................ 7
Document Layout .................................................................................................. 7
Conventions Used in This Guide........................................................................... 8
Recommended Reading........................................................................................ 9
The Microchip Web Site ........................................................................................ 9
Customer Support ................................................................................................. 9
Revision History .................................................................................................... 9
Chapter 1. Product Overview
1.1 Introduction ................................................................................................... 11
Chapter 2. Configuration
2.1 Introduction ................................................................................................... 13
2.2 Configuration Options ................................................................................... 13
2.3 Configuration Instructions ............................................................................. 16
2.4 Power ........................................................................................................... 18
2.5 Clocking ........................................................................................................ 18
2.6 Line Interface Connector Options ................................................................. 19
2.7 MII Connector ............................................................................................... 20
2.8 MII Management Interface (MDIO/MDC) ..................................................... 20
2.9 10-Pin Header (J7) ....................................................................................... 20
2.10 Status Indicator LEDs ................................................................................. 20
2.11 Reset Buttons ............................................................................................. 21
2.12 Jumpers ...................................................................................................... 21
2.13 KSZ8061MNX Strapping Options ............................................................... 22
2.14 MDIO/MDC Software Utility and FTDI Cable ............................................. 22
Appendix A. Schematic and Layouts
A.1 Introduction .................................................................................................. 25
Appendix B. Bill of Materials (BOM)
Worldwide Sales and Service .................................................................................... 34
 2016 Microchip Technology Inc.
DS50002449A-page 5
KSZ8061MNX Evaluation Board User’s Guide
NOTES:
DS50002449A-page 6
 2016 Microchip Technology Inc.
KSZ8061MNX EVALUATION
BOARD USER’S GUIDE
Preface
NOTICE TO CUSTOMERS
All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our web site
(www.microchip.com) to obtain the latest documentation available.
Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXXXXA”, where “XXXXXXXX” is the document number and “A” is the revision level
of the document.
For the most up-to-date information on development tools, see the MPLAB® IDE online help.
Select the Help menu, and then Topics to open a list of available online help files.
INTRODUCTION
This chapter contains general information that will be useful to know before using the
KSZ8061MNX Evaluation Board. Items discussed in this chapter include:
•
•
•
•
•
•
Document Layout
Conventions Used in This Guide
Recommended Reading
The Microchip Web Site
Customer Support
Revision History
DOCUMENT LAYOUT
This document describes how to use the KSZ8061MNX Evaluation Board as a development tool. The document is organized as follows:
• Chapter 1. “Product Overview” – This chapter includes important information
about the KSZ8061MNX Evaluation Board.
• Chapter 2. “Configuration” – This chapter includes a detailed description of
each function of the evaluation board and instructions on how to begin using the
board.
• Appendix A. “Schematic and Layouts” – Refer to this appendix for board
schematics.
• Appendix B. “Bill of Materials (BOM)” – Refer to this appendix to view the bill of
materials.
 2016 Microchip Technology Inc.
DS50002449A-page 7
KSZ8061MNX Evaluation Board User’s Guide
CONVENTIONS USED IN THIS GUIDE
This manual uses the following documentation conventions:
DOCUMENTATION CONVENTIONS
Description
Arial font:
Italic characters
Initial caps
Quotes
Underlined, Italic text with
right angle bracket
Bold characters
N‘Rnnnn
Text in angle brackets < >
Courier New font:
Plain Courier New
Represents
Referenced books
Emphasized text
A window
A dialog
A menu selection
A field name in a window or
dialog
A menu path
MPLAB® IDE User’s Guide
...is the only compiler...
the Output window
the Settings dialog
select Enable Programmer
“Save project before build”
A dialog button
A tab
A number in verilog format,
where N is the total number of
digits, R is the radix and n is a
digit.
A key on the keyboard
Click OK
Click the Power tab
4‘b0010, 2‘hF1
Italic Courier New
Sample source code
Filenames
File paths
Keywords
Command-line options
Bit values
Constants
A variable argument
Square brackets [ ]
Optional arguments
Curly brackets and pipe
character: { | }
Ellipses...
Choice of mutually exclusive
arguments; an OR selection
Replaces repeated text
Represents code supplied by
user
DS50002449A-page 8
Examples
File>Save
Press <Enter>, <F1>
#define START
autoexec.bat
c:\mcc18\h
_asm, _endasm, static
-Opa+, -Opa0, 1
0xFF, ‘A’
file.o, where file can be
any valid filename
mcc18 [options] file
[options]
errorlevel {0|1}
var_name [,
var_name...]
void main (void)
{ ...
}
 2016 Microchip Technology Inc.
Preface
RECOMMENDED READING
This user's guide describes how to use KSZ8061MNX Evaluation Board. Other useful
documents are listed below. The following Microchip documents are available and
recommended as supplemental reference resources:
• KSZ8061MNX/KSZ8061MNG Data Sheet
This data sheet provides detailed information regarding the KSZ8061MNX device.
THE MICROCHIP WEB SITE
Microchip provides online support via our web site at www.microchip.com. This web
site is used as a means to make files and information easily available to customers.
Accessible by using your favorite Internet browser, the web site contains the following
information:
• Product Support – Data sheets and errata, application notes and sample
programs, design resources, user’s guides and hardware support documents,
latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical
support requests, online discussion groups, Microchip consultant program
member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip
press releases, listing of seminars and events, listings of Microchip sales offices,
distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer
(FAE) for support. Local sales offices are also available to help customers. A listing of
sales offices and locations is included in the back of this document.
Technical support is available through the web site at:
http://www.microchip.com/support.
REVISION HISTORY
Revision A (March 2016)
• Original Microchip release of this document. This document replaces Micrel document “KSZ8061MNX Evaluation Board User's Guide” version 1.1 (March 2015).
 2016 Microchip Technology Inc.
DS50002449A-page 9
KSZ8061MNX Evaluation Board User’s Guide
NOTES:
DS50002449A-page 10
 2016 Microchip Technology Inc.
KSZ8061MNX EVALUATION
BOARD USER’S GUIDE
Chapter 1. Product Overview
1.1
INTRODUCTION
The KSZ8061MNX Evaluation Board is designed to enable functional and performance
testing of the KSZ8061MNX PHY. In addition to the KSZ8061 PHY, there is a second
PHY–a KSZ8081. The KSZ8081 is a standard 10/100 Ethernet PHY. It is used here to
provide a second line interface for simple full-duplex traffic through the KSZ8061. This
board is not intended for evaluation of the KSZ8081. A block diagram of the board is
shown in Figure 1-1. Figure 1-2 highlights the board components.
FIGURE 1-1:
KSZ8061MNX EVALUATION BOARD BLOCK DIAGRAM
25 MHz
Clocking Options
Xtal
Tx
Rx
R1-6
R221-226
Rx
Second PHY
(KSZ8081)
Tx
Magnetics
MII
KSZ8061
MII
Magnetics
Line
Connector
(3 options)
R211-216
RXER Latch,
LED, Reset
RJ-45
Reset
Reset
R21-26
R11-16
Reset
Interrupt
10-Pin
Management
Header (J7)
Signal Detect
MII Connector
MDIO/MDC
En
KSZ8061 Low V Reg
Select
5V
KSZ8061 3.3V Reg
KSZ8081 3.3V Reg
DC Power
Connector
 2016 Microchip Technology Inc.
DS50002449A-page 11
KSZ8061MNX Evaluation Board User’s Guide
FIGURE 1-2:
DS50002449A-page 12
KSZ8061MNX EVALUATION BOARD COMPONENTS
 2016 Microchip Technology Inc.
KSZ8061MNX EVALUATION
BOARD USER’S GUIDE
Chapter 2. Configuration
2.1
INTRODUCTION
This chapter discusses the configuration of the KSZ8061MNX Evaluation Board.
Items discussed in this chapter include:
•
•
•
•
•
•
•
•
•
•
•
•
•
2.2
Configuration Options
Configuration Instructions
Power
Clocking
Line Interface Connector Options
MII Connector
MII Management Interface (MDIO/MDC)
10-Pin Header (J7)
Status Indicator LEDs
Reset Buttons
Jumpers
KSZ8061MNX Strapping Options
MDIO/MDC Software Utility and FTDI Cable
CONFIGURATION OPTIONS
The KSZ8061 line interface is designed to permit the installation of any one of three
different connectors. These are described further in a later section.
The KSZ8061 MII data path can be configured in three different ways. Below are
descriptions and photographs of the configuration options.
1. Two-PHY MII Back-to-Back
The evaluation board has two PHYs: a KSZ8061 (U1) and a KSZ8081 (U2). The
KSZ8081 is an ordinary 10/100 Ethernet PHY, and is on this board to support the
KSZ8061. Their MII buses can be connected together, which allows Ethernet
frames to be passed between the KSZ8061 line interface (J1, J2 or J3) and the
KSZ8081 line interface (J6). Unless otherwise indicated, this is the default board
configuration.
2. MII Loopback
In this configuration, the KSZ8061 receives Ethernet traffic from the line interface. At the MII interface, RX traffic is looped back the TX MII interface, and the
KSZ8061 transmits it back to the line interface. The KSZ8081 PHY is not used.
Do not reference Figure 2-2 for resistor settings.
3. MII Connector
The MII edge connector (J5) allows the KSZ8061MNX Evaluation Board to be
connected to the MAC port of a Microchip switch evaluation board, or to any
other device with an Ethernet MAC interface. Full duplex traffic can pass
between the MII connector and the KSZ8061 line interface (J1, J2 or J3). The
KSZ8081 PHY is not used.
 2016 Microchip Technology Inc.
DS50002449A-page 13
KSZ8061MNX Evaluation Board User’s Guide
FIGURE 2-1:
DS50002449A-page 14
KSZ8061MNX EVALUATION BOARD IN TWO-PHY MII BACK-TO-BACK MODE
 2016 Microchip Technology Inc.
Configuration
FIGURE 2-2:
KSZ8061MNX EVALUATION BOARD IN MII LOOPBACK MODE WITH
USB-TO-MDIO/MDC CABLE ON J7
FIGURE 2-3:
KSZ8061MNX EVALUATION BOARD IN MII CONNECTOR MODE, WITH
ETHERNET SWITCH
 2016 Microchip Technology Inc.
DS50002449A-page 15
KSZ8061MNX Evaluation Board User’s Guide
2.3
CONFIGURATION INSTRUCTIONS
These instructions detail how to change between configurations. Figure 2-4 and
Figure 2-5 show the location of the components referenced in the instructions.
1. Two-PHY MII Back-to-Back Configuration. This is the default configuration, so
these steps are only necessary if switching the board back from another
configuration.
a) Place the KSZ8061 in MII Back-to-Back mode: install R40 and R41. Remove
R39.
b) Connect the MII interfaces of the KSZ8061 and KSZ8081: install R212-R216
and R222-226. Note that the MII clocks should not be connected between
the two devices, so do not install R211 and R221.
c) Both PHYs must be clocked from U3. Do not use crystal Y1, by removing
either Y1 or R91 and R92.
d) Remove R1-R6.
e) Power the KSZ8081: install jumper JP1.
f) Optionally, for optimal signal integrity, remove R11-R16 and R21-R26.
2. MII Loopback Configuration
a) Place the KSZ8061 in MII Back-to-Back mode: install R40 and R41. Remove
R39.
b) Install R1-R6.
c) Remove the KSZ8081 from the MII bus. There are three possible ways to do
this:
- Remove jumper JP1 to remove power from the KSZ8081.
- Remove R211-R216 and R221-R226.
- Put the KSZ8081 in Isolate mode: install R70.
d) The KSZ061 may be clocked by either the external clock (U3) or the crystal
(Y1). When changing between clock sources, the KSZ8061 does not require
any setting changes.
e) Optionally, for optimal signal integrity, remove R11-R16 and R21-R26.
3. MII Connector Configuration
a) Place the KSZ8061 in Normal mode: remove R39 and R41. Install R40 if
Auto-MDI/MDI-X is desired. Otherwise, remove R40.
b) Install R11-R16 and R21-R26.
c) Remove R1-R6.
d) Remove the KSZ8081 from the MII bus. There are three possible ways to do
this:
- Remove jumper JP1 to remove power from the KSZ8081.
- Remove R211-R216 and R221-R226
- Put the KSZ8081 in Isolate mode: install R70.
e) The KSZ061 may be clocked by either the external clock (U3) or the crystal
(Y1). When changing between clock sources, the KSZ8061 does not require
any setting changes.
f) Connect the KSZ8061 evaluation board to a compatible connector on a
Microchip switch evaluation board, and ensure that the port on the switch
board is configured for MAC interface.
DS50002449A-page 16
 2016 Microchip Technology Inc.
Configuration
FIGURE 2-4:
TOP SIDE COMPONENTS FOR CONFIGURTION CHANGES
FIGURE 2-5:
BOTTOM SIDE COMPONENTS FOR CONFIGURATION
CHANGES
 2016 Microchip Technology Inc.
DS50002449A-page 17
KSZ8061MNX Evaluation Board User’s Guide
2.4
POWER
The evaluation board requires a DC supply at barrel connector J8. A jumper must be
installed on pins 2-3 of JP3. The voltage requirement is 4.5V to 14V. The current
requirement is 200 mA.
An alternate power connection is available at the 10-pin management header J7. This
is intended to allow the board to be powered from a USB cable such as the FTDI
C232HM-EDHSL-0. When supplying power via header J7, a jumper must be installed
on pins 1-2 of JP3 (labeled “5V_HDR”).
A noise filtering choke is provided on the J8 connector, but not on the J7 power pins.
Therefore, J8 is the preferred power connector when testing KSZ8061 performance.
2.5
CLOCKING
The KSZ8061 utilizes a 25 MHz reference clock. There are two options for supplying
this clock: crystal or external clock. If the second PHY (KSZ8081, U2) is used, then the
two PHYs must be synchronized and the only clocking option is to clock both PHYs
from the same external clock source.
1. External clock (default configuration). The external clock source is a Microchip
PL135-27 (U3), which drives the same 25 MHz clock to both PHYs. When using
this clock source, the KSZ8061 crystal (Y1) must not be connected from the
KSZ8061. This is done either by removing R91 and R92, or by removing Y1, refer
to Figure 2-6.
FIGURE 2-6:
EXTERNAL CLOCK OPTION
KSZ8081MNX (U2)
PL135-27 (U3)
CLK0
XI
CLK1
R62 / 0ȍ
R92 / DNI
Y1
KSZ8061MNX (U1)
XI
R91 / DNI
XO
2. Crystal. Crystal Y1 can be connected directly to the KSZ8061, which has an
on-chip oscillator. Install resistors R91 and R92, and remove resistor R62. To
fully turn off the external clock (U3), remove R63. This mode can be used only
when the KSZ8061 and KSZ8081 are not used in back-to-back configuration.
DS50002449A-page 18
 2016 Microchip Technology Inc.
Configuration
FIGURE 2-7:
CRYSTAL CLOCKING OPTION
3.3V
R62
DNI
KSZ8061MNX (U1)
R92 / 0ȍ
XI
R63 optional
PL135-27 (U3)
Y1
VDD
R91 / 0ȍ
XO
CAUTION
The silkscreen labels on the bottom of the board for R62, R91 and R92 are incorrect.
The middle resistor is R62. R91 is closer to C9, and R92 is closer to C10. The image
below shows the correct locations of R62, R91, and R92.
2.6
LINE INTERFACE CONNECTOR OPTIONS
The KSZ8081 has a conventional RJ-45 UTP Ethernet connector, but there are three
connector options for the KSZ8061:
1. J1: Ethernet RJ-45
2. J2: TE MQS-4, part number 1379165-1 (Mating receptacle is 1379029-1)
3. J3: Sumitomo TS series 16-pin, part number 6098-6793 (Mating receptacle is
6098-4008)
Table 2-1 lists the signal connections for each connector. Also refer to the schematic or
PCB layout file since connector pin numbering may not be standardized.
 2016 Microchip Technology Inc.
DS50002449A-page 19
KSZ8061MNX Evaluation Board User’s Guide
TABLE 2-1:
KSZ8061 CONNECTOR PIN ASSIGNMENTS
Connector Pin Assignment
KSZ8061 Signal
RJ-45
TXP
2.7
1
Sumitomo
6098-6793
TE 1379165-1
4
10
TXM
2
3
9
RXP
3
2
7
RXM
6
1
6
MII CONNECTOR
The MII edge connector J5 provides external access to the KSZ8061 MII bus and the
MII management interface (MDIO/MDC). This connector is typically used to connect
the KSZ8061 PHY to the MAC interface on a Microchip Ethernet switch evaluation
board. Test traffic can then be sent and received through another port on the switch.
This configuration is shown in Figure 2-3. Note that 5V power is not shared across this
connector, so each board must be powered separately.
To use this interface, it is necessary to have 0-ohm resistors R11-R16 and R21-R26
installed. The KSZ8081 also needs to be isolated from the MII bus. The simplest way
to do this is to remove power from the KSZ8081 by removing jumper JP1. Alternatively,
place the KSZ8081 into Isolate mode by installing R70, or remove resistors R211-R216
and R221-R226.
2.8
MII MANAGEMENT INTERFACE (MDIO/MDC)
The MII management interface (MDIO/MDC) can be accessed in two ways. The first is
via the MII connector J5, discussed above. This requires the installation of resistors
R31 and R33. Alternatively, these signals are accessible at the 10-pin header J7,
requiring the installation of resistors R27 and R28. These resistor options are provided
for signal integrity optimization. If signal integrity on this interface is not a problem, then
it is acceptable to leave all four resistors installed.
The default MII management addresses (a.k.a. PHY addresses) are b'001 for the
KSZ8061, and b'011 for the KSZ8081.
2.9
10-PIN HEADER (J7)
Header J7 is intended primarily for access to the MII management interface (MDIO and
MDC signals). The header pins are labeled with color codes for connection to the FTDI
C232HM-DDHSL-0 or C232HM-EDHSL-0 USB-to-MPSSE cable. The two pins labeled
“MDIO” are the same board signal. They are duplicated because the FTDI cable separates the serial data input and output signals.
As described in Section 2.4 “Power”, it is possible to power the board through header
J7 instead of the standard power connector J8. The C232HM-EDHSL-0 cable has 5V
available for this purpose. Note that the board cannot be powered from the
C232HM-DDHSL-0 cable which is 3.3V. See Section 2.4 “Power” for more details.
This header also provides access to the KSZ8061 reset input signal, and the interrupt
and signal detect output signals. The reset signal goes only to the KSZ8061, and not
to the KSZ8081 nor to the RXER latch and LED.
DS50002449A-page 20
 2016 Microchip Technology Inc.
Configuration
2.10
STATUS INDICATOR LEDS
The board includes the following LEDs:
• D2: KSZ8061 3.3V power indicator LED (red). Note that the KSZ8061 and
KSZ8081 have separate voltage regulators, and that there is no equivalent power
LED for the KSZ8081.
• D3: KSZ8061 SIGD (signal detect) LED (green). SIGD is also accessible at J7 pin 8.
• D4: KSZ8061 RXER (RX error) latch LED (red). RXER is an MII output signal from
the KSZ8061. If RXER ever goes high, that state is captured and held by latch
(U7). This latch is reset by the press button S3.
• D7: KSZ8081 link status LEDs (green). These are standard link/activity and speed
status LEDs. There are no equivalent link status LEDs for the KSZ8061.
FIGURE 2-8:
2.11
LOCATION OF LEDS AND RESET BUTTONS
RESET BUTTONS
The board has three push buttons, which are all used for reset purposes:
• S1: Chip reset for KSZ8061 (U1)
• S2: Chip reset for KSZ8081 (U2)
• S3: KSZ8061 RXER latch reset (U7, D4)
 2016 Microchip Technology Inc.
DS50002449A-page 21
KSZ8061MNX Evaluation Board User’s Guide
2.12
JUMPERS
The board has four jumpers:
• JP1: Install to enable the KSZ8081 (U2) 3.3V regulator. Remove to disconnect
power from the KSZ8081. Removing power from the KSZ8081 also isolates it
from the MII bus.
• JP2: When installed, the low voltage regulator (U6) that partially powers the
KSZ8061 is enabled/disabled by the KSZ8061 SIGD signal. When not installed,
the low voltage regulator is always enabled. When the KSZ8061 is properly configured, this feature can be used to achieve ultra-low power standby power.
• JP3: (3-pin) Selects the power source for the board. Normally, install a jumper on
pins 2-3 for power from connector J8. To power the board from header J7 instead,
install the jumper on pins 1-2.
• JP4: Install to enable the KSZ8061 (U1) voltage regulator. Remove to disconnect
power from the KSZ8061.
FIGURE 2-9:
2.13
LOCATION OF JUMPERS
KSZ8061MNX STRAPPING OPTIONS
Resistors R36-R44 are used to select optional strapping configurations to the
KSZ8061MNX. When a resistor is not installed, the internal resistor for each pin pulls
it to its default level during reset. Installing a resistor pulls the pin to the opposite logic
level. See the chip data sheet and/or board schematic for details.
DS50002449A-page 22
 2016 Microchip Technology Inc.
Configuration
TABLE 2-2:
Resistor
STRAPPING RESISTOR OPTIONS FOR PRODUCTION SILICON
Strapping Function
Resistor not Installed
Resistor Installed
[R38, R37, R36]
PHY Address
Address = b’001
Any other address
[R41, R40, R39]
Configuration
b’000 = Normal MII mode,
Auto-MDI/MDI-X disabled
b’010 = Normal mode,
Auto-MDI/MDI-X enabled
b’110 = Back-to-back,
Auto-MDI/MDI-X enabled
R42
Quiet-WIRE® Filtering
R43
NAND Tree
Disabled
Enabled
R44
Auto Negotiation
Disabled
Enabled
2.14
Enabled
Disabled
MDIO/MDC SOFTWARE UTILITY AND FTDI CABLE
ethutil.exe is a free Windows command line utility from Microchip for access to the
KSZ8061 MII management interface (MDIO/MDC) using the USB cables described in
Section 2.9 “10-Pin Header (J7)”. Contact your Microchip sales representative for
information on how to download this utility and the accompanying user guide. The user
guide provides instructions on installing and using this utility.
When the KSZ8061 and KSZ8081 are both powered and connected to the MII management interface (MDIO/MDC), the ethutil.exe utility will automatically configure itself
for the highest address PHY, which by default is the KSZ8081 at address 3. Use the
“address” command, as shown in Figure 2-10, to switch to the KSZ8061 PHY.
FIGURE 2-10:
ETHUTIL.EXE UTILITY - OPENING SCREEN AND ADDRESS COMMAND
If the KSZ8081 is removed, disabled or if power is disconnected, then the utility will
automatically configure itself for the KSZ8061 instead of the KSZ8081. This is shown
in Figure 2-11.
 2016 Microchip Technology Inc.
DS50002449A-page 23
KSZ8061MNX Evaluation Board User’s Guide
FIGURE 2-11:
ETHUTIL.EXE UTILITY WHEN KSZ8081 MDIO/MDC IS OFF
Commands for ethutil.exe can be saved in ordinary text files and run using the “run”
command. This is a simple form of scripting. It is suggested to have an “address 1"
command as the first line in all script files, to ensure that the commands to go the
KSZ8061 rather than the KSZ8081. Example 2-1 is an example of a file named
script.txt. Figure 2-12 shows how this script file is run.
EXAMPLE 2-1:
SCRIPT.TXT
address 1
r 0
r 1
FIGURE 2-12:
DS50002449A-page 24
RUNNING A SCRIPT
 2016 Microchip Technology Inc.
KSZ8061MNX EVALUATION
BOARD USER’S GUIDE
Appendix A. Schematic and Layouts
A.1
INTRODUCTION
This appendix contains the following schematics and layouts for the MCP9600
Thermocouple IC Evaluation Board:
•
•
•
•
Figure A-1: “Board Schematic 1 of 4”
Figure A-2: “Board Schematic 2 of 4”
Figure A-3: “Board Schematic 3 of 4”
Figure A-4: “Board Schematic 4 of 4”
 2016 Microchip Technology Inc.
DS50002449A-page 25
BOARD SCHEMATIC 1 OF 4
TP5
0.1uF
220
R77
D1
10K
BAV16W-7 SOD-123
C12
C31
25MHz
22pF
22pF
0.1uF
3.3V
S1
DVDDL
RST#_U1
AVDDL
0.1uF at U1 pins 9, 30
0.1uF at U1 pin 8
C3
1
3
U3
2
4
1
2
3
R123
10uF
SW PUSHBUTTON
XIN
CLK1
GND
220
6
5
4
XOUT
VDD
CLK0
33
R76
CLK_U2
Micrel PL135-27
C68
C73
0.1uF
0.1uF
0.1uF
2
C65
R90
D10
(5)
R62
RESET_IN
1
LED - GREEN SMD
VDDIO
BAV16W-7 SOD-123
R78
R91
1
2
R20
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
33
D6
DVDDL
MII_TXEN
J5
XI_PL
C11
LED - GREEN SMD
COL
opt
CRS_U1
COL
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_TXEN
MII_TXC
TXER_U1
RXER_U1
MII_RXC
MII_RXDV
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_MDC
MII_MDIO
3.3V
XO_PL
4.7k
R53
0
Y2
D3
R51
3.3V
R63
2
0.1uF
KSZ8061
Push
Button
Reset
1
C8
1) PL135-27 (default): Install R62. Remove R91, R92
or
2) Y1: Install R91, R92. Remove R62.
2
C76
SIG DET
R120
VDDIO
0.1uF at U1 pin 15
0.1uF at U1 pin 3
KSZ8061 Clock Options
SIGD
VDDIO
1
AVDDH
TXER_U1
R92
XO_D1
4.7K
SIGD
Male MII Connector
XI_U1
Male MII Connector: Connect to switch or SOC/CPU board.
Put KSZ8061 in normal mode.
Unpower KSZ8081 (remove JP1).
C10
25MHz
15pF
(6)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Opt/0
XI_D1
C9
SIGD
33
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
0
Y1
Opt/0
XO_U1
VCC
CRS
COL
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
TX_ER
RX_ER
RX_CLK
RX_DV
RXD0
RXD1
RXD2
RXD3
MDC
MDIO
VCC
15pF
INTRP_U1
AVDDL
25
1
XI
LED0/TXER
24
TXER_U1
XO_U1
2
XO
TXD1
23
TXD1_U1
3
AVDDH
TXD0
22
TXEN
21
RXP
(4)
RXM_U1
RXM_U1
7
8
KSZ8061MNX
20
TXC_P1
R81
0
TXC_U1
19
RXC_P1
R82
33
RXC_U1
RXM
RXD0
18
RXD0_P1
R83
33
RXD0_U1
AVDDL
RXD1
17
RXD1_P1
R84
33
RXD1_U1
RXD2
VDDIO
16
RXD3
RXDV
RXER
VDDIO
15
14
13
12
MDC
MDIO
10
9
11
VDDL
Notes:
1. KSZ8061 has a Paddle Ground on bottom side of chip.
Refer to datasheet for mechanical dimensions.
Place this GND test
point on bottom side;
Center and connect to
Paddle Ground of U1.
MII_TXD3
TXD3_U1
R216
0
PHY_TXD3 (5)
0
MII_TXD2
TXD2_U1
R215
0
PHY_TXD2 (5)
R14
0
MII_TXD1
TXD1_U1
R214
0
PHY_TXD1 (5)
R13
0
MII_TXD0
TXD0_U1
R213
0
PHY_TXD0 (5)
R12
0
MII_TXEN
TXEN_U1
R212
0
PHY_TXEN (5)
R11
0
MII_TXC
TXC_U1
R211
0
PHY_TXC
TXEN_U1
TXC
RXC
(32-QFN)
0
R15
RXD2_P1
R85
33
RXD2_U1
RXD3_P1
R86
33
RXD3_U1
RXDV_P1
R87
33
RXDV_U1
RXER_P1
R88
33
RXER_U1
(5)
Notes:
1. Place all MII bus resistors on the traces
to U1 to minimize stubs.
2. Place R11-R26 and R211-R226 on opposite
sides of the board - mirror image.
R6 Opt/0
TXM
6
R5 Opt/0
TXP
5
RXP_U1
R4 Opt/0
4
TXM_U1
R3 Opt/0
TXP_U1
TXM_U1
RXP_U1
R2 Opt/0
TXP_U1
(4)
R16
TXD0_U1
R1 Opt/0
TXD3
TXD2
26
27
28
29
INTRP
RESET#
CRS
30
31
VDDL
XI_U1
(4)
(4)
SIGDET
PAD_GND
AVDDH
TXD2_U1
REXT
U1
6.04K
Female MII Connector: Connect back-to-back with another PHY.
5V is supplied to the attached board.
Put KSZ8061 in Back-to-Back mode.
Unpower KSZ8081 (remove JP1).
TXD3_U1
32
R47
33
SIGD_P1
CRS_U1
R21
0
MII_RXC
RXC_U1
R221
0
PHY_RXC (5)
R22
0
MII_RXDV
RXDV_U1
R222
0
PHY_RXDV (5)
R23
0
MII_RXD0
RXD0_U1
R223
0
PHY_RXD0 (5)
R24
0
MII_RXD1
RXD1_U1
R224
0
PHY_RXD1 (5)
R25
0
MII_RXD2
RXD2_U1
R225
0
PHY_RXD2 (5)
R26
0
MII_RXD3
RXD3_U1
R226
0
PHY_RXD3 (5)
5.0V
J4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_TXEN
MII_TXC
MII_RXC
MII_RXDV
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
VCC
MDIO
MDC
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_CLK
RX_ER
TX_ER
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
COL
CRS
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Female MII Connector
TP6
5V_HDR
VDDIO
GND
R35
MDC
MDC
(5)
MDIO
MDIO
(5)
1K
 2016 Microchip Technology Inc.
Strapping Options (Refer to data sheet for descriptions)
MII Bus Connection
R1 - R6
KSZ8061 to KSZ8081
Remove
KSZ8061 to MII Connectors J4, J5 Remove
KSZ8061 MII loopback
Install
R11 - R26
R211 - R226
Optional
Install
Remove
Install
Optional
Remove
MDC
R31
33
MII_MDC
MDIO
R33
33
MII_MDIO
INTRP_U1
MDC
R27
33
MDC_H10
MDIO
R28
33
MDIO_H10
PHYAD0
RXD3_U1
R36
Opt/4.7K
PHYAD1
RXD2_U1
R37
Opt/4.7K
PHYAD2
RXD1_U1
R38
Opt/4.7K
CONFIG0
RXC_U1
R39
Opt/4.7K
RESET_IN
Mode (description)
000
MII normal mode; Auto-MDI/MDI-X disabled
010
MII normal mode; Auto-MDI/MDI-X enabled
1
CRS_U1
R40
4.7K
CONFIG2
RXDV_U1
R41
4.7K
BAV16W-7 SOD-123
VDDIO
D8
1
Q-WIRE_DISABLE
RXER_U1
R42
4.7K
NAND_Tree#
INTRP_U1
R43
Opt/1K
AUTO_NEG_DIS
RXD0_U1
R44
Opt/4.7K
110
R61
2
BAV16W-7 SOD-123
CLEAR RX_ER FFLOP
MII Back-to-Back; Auto-MDI/MDI-X enabled
R122
MII normal mode is used when interfacing
via the MII Connector.
RXER_U1
R60
0
1
2
3
CLK
GND
D
S3
10K
1
3
U7
MII Back-to-Back mode is required
for MII loopback, and when connecting
KSZ8061 to KSZ8081.
MDIO_H10
SIGD
RESET_IN
J7
MDC / ORANGE
MDIO / YELLOW
5V / RED
INTERRUPT#
GND / BLACK
2
0
CONFIG1
2
4
6
8
10
D9
RX_ER Flip Flop
CONFIG[2:0]
1
3
5
7
9
Labels for 5x2 Header:
Configuration options for KSZ8061MNX
VDDIO
Header 5x2
MDC_H10
MDIO_H10
CLR#
VCC
Q
74LVC1G175
6
5
4
2
4
SW PUSHBUTTON
R121
D4
220
2
1
C7
2.2uF
LED - RED SMD
1
3
5
7
9
2
4
6
8
10
GND / BLACK
MDIO / GREEN
5V / RED
SIG_DET
RESET#
KSZ8061MNX Evaluation Board User’s Guide
DS50002449A-page 26
FIGURE A-1:
BOARD SCHEMATIC 2 OF 4
Component placement for this schematic page
will allow for flow thru routing of TX and RX
differential pairs on top PCB layer.
These components are optional. They are suggested
only for applications requiring maximum noise immunity.
C91
opt
T1
J1
1
2
3
4
5
6
7
8
TX+_U1
TX-_U1
RX+_U1
R48
75
R50
75
R49
75
R52
75
1
16
2
15
TX-_U1
3
14
RX+_U1
6
11
7
10
8
9
CMT
RX-_U1
CT_TX1
TX_P_U1
1
4
TXP_U1
TXP_U1 (3)
TX_M_U1
2
3
TXM_U1
TXM_U1 (3)
TDK ACT45
CMR
C17
RX-_U1
1000pF / 2kV
U1_CHASSIS_GND
L3
CT_RX1
RX_P_U1
RX_M_U1
R58
TX+_U1
TX-_U1
RX+_U1
RX-_U1
opt
R96
opt
R59
0
R58 and R96:
Place one near J1/J2/J3
Place the other nearer L1
4
RXP_U1
RXP_U1 (3)
2
3
RXM_U1
RXM_U1 (3)
C94
C93
opt
opt
R32
opt
R34
opt
C92
opt
CT_TX1
MQS 4 Pos TE 1379165-1
1
TDK ACT45
TDK TLA-8T104WLF
J2
4
3
2
1
C90
opt
L2
TX+_U1
RJ-45 Jack
TH1
TH2
 2016 Microchip Technology Inc.
FIGURE A-2:
C18
1uF
J3
16
5
B
6
1
16
5
15
4
14
13
12
11
10
9
8
3
7
2
6
1
16
5
15
4
14
13
12
11
10
9
8
3
7
2
6
1
EXT_GND
CT_RX1
C16
1uF
TX+_U1
TX-_U1
RX+_U1
RX-_U1
Sumitomo 6098-6793
DS50002449A-page 27
Three connector options are provided.
Only one may be mounted at a time.
The footprints are closely spaced so as to minimize trace stubs.
Schematic and Layouts
U1_CHASSIS_GND
BOARD SCHEMATIC 3 OF 4
Notes:
1. KSZ8081 has a Paddle Ground on bottom side of chip.
Refer to datasheet for mechanical dimensions.
3.3V_U2
U2
Push
Button
Reset
3.3V_U2
LINK/ACT
LED1
SPEED
S2
1
2
3
4
SW PUSHBUTTON
D7
1
3
2
R79
220
LED0_U2
4
R80
220
LED1_U2
R75
D5
10K
BAV16W-7 SOD-123
C23
10uF
C22
1uF
C21
10uF
LED0_U2
3.3A_U2
LEDx2
1
FBEAD
C24
1uF
2
LED0
3.3V_U2
FB7
2
1
LEDs
3.3A_U2
CRS_U2
LED1_U2
GND
T2
J6
TDK TLA-8T104WLF
TX+_U2
TX-_U2
RX+_U2
RX-_U2
75
R55
RX-_U2
RJ-45 Jack
R56
75
R57
9
8
10
7
RX+_U2
11
6
TX-_U2
14
3
15
2
16
1
75
75
C29
1000pF / 2kV
TX+_U2
FB5
U2_CHASSIS_GND
1
R97
C63
1uF
C69
TXD0
TXEN
TXC
INTRP
RXER
RXC
RXDV
VDDIO
KSZ8081MNX
(32-QFN)
24
23
22
21
20
19
18
17
RXER_U2
RXC_P2
RXDV_P2
R29
R30
3.3V_U2
1uF
0.1uF
33
33
PHY_RXD3
PHY_RXD2
PHY_RXD1
PHY_RXD0
PHY_RXD3
PHY_RXD2
PHY_RXD1
PHY_RXD0
PHY_RXDV
PHY_RXC
PHY_RXDV (3)
PHY_RXC (3)
(3)
(3)
(3)
(3)
PHY_TXC
PHY_TXEN
PHY_TXC (3)
PHY_TXEN (3)
PHY_TXD0
PHY_TXD1
PHY_TXD2
PHY_TXD3
PHY_TXD0
PHY_TXD1
PHY_TXD2
PHY_TXD3
(3)
(3)
(3)
(3)
MDC
MDIO
(3)
(3)
U2
opt
Place this GND test
point on bottom side;
Center and connect to
Paddle Ground of U2.
U2_CHASSIS_GND
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
TXP
XO
C26
2
FBEAD
1
2
3
4
5
6
7
8
RX-_P2
RX+_P2
TX-_P2
TX+_P2
XI
REXT
MDIO
MDC
RXD3
RXD2
RXD1
RXD0
R54
9
10
11
12
13
14
15
16
TH1
TH2
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
RST#_U2
33
C20
0.1uF
C30
0.1uF
RST#
LED1
LED0
CRS
COL
TXD3
TXD2
TXD1
C71
2.2uF
EXT_GND
(3)
CLK_U2
R45
RXD0_P2
RXD1_P2
RXD2_P2
RXD3_P2
R67
R66
R65
R64
33
33
33
33
6.49K
TP7
MDC
MDIO
GND
Place R97 nearer to power connector J8.
FB5 should also be placed nearer to J8 than to J6.
Strapping Options (Refer to datasheet for descriptions)
3.3V_U2
 2016 Microchip Technology Inc.
PHYAD2
PHY_TXD1
R93
Opt/4.7K
PHYAD1
PHY_TXD2
R74
4.7K
CONFIG1
CRS_U2
R68
4.7K
CONFIG2
PHY_TXEN
R69
4.7K
000
MII normal mode
ISO
RXER_U2
R70
Opt/4.7K
110
MII Back-to-Back
NWAYEN
LED0_U2
R71
Opt/1K
SPEED
LED1_U2
R72
Opt/1K
MII Back-to-Back mode is required
when connecting KSZ8061 to KSZ8081.
DUPLEX
PHY_TXD0
R73
Opt/1K
On this board, the KSZ8081 is never used
in MII normal mode.
CONFIG[2:0]
Mode (description)
KSZ8061MNX Evaluation Board User’s Guide
DS50002449A-page 28
FIGURE A-3:
BOARD SCHEMATIC 4 OF 4
Power source options:
DC_IN_EXT (J26) must be used for EMC testing.
5V_HDR (J44) may be used in non-EMC environment.
DC_IN_EXT:
Nominal: 5V
Maximum: 13V or limited by attached MII board
3.3V Power for Second PHY (KSZ8081MNX)
5.0V
U4
DC_IN_EXT
DC_IN
5.0V
R94
opt
L1
1
4
2
3
VIN
VOUT
ADJ
TP1
GND
R117
5
2.49K
+ C84
22uF Tant
GND
1uF
TP33
+ C1
TP12
3.3V
220uF / 50V Elect
TP4
GND
C72
1.50K
3X1
TP3
GND
R118
2
3
TP2
4
2.2uF / 50V
1
1
R89
4.7K
C77
JP3
PWRJACK-TH
J8
5V_HDR
EN
GND
1
3
JUMPER
2
2.1mm Power
Jack
Place GND test points evenly across PCB.
3.3V_U2
MIC29302WU / TO-263-5
JP1
2
3
 2016 Microchip Technology Inc.
FIGURE A-4:
Jumper
Closed: Second PHY (KSZ8081) is powered
Open: Second PHY is unpowered
VOUT = 1.24 X [ 1 + ( R117 / R118 ) ]
3.3V
VDDL
VDDL
TDK ZJYS81
R95
opt
EXT_GND
When using terminal block (3.3V only),
1. Remove JP1 and JP4 to disable LDOs U4 and U5.
2. Install R98.
3.3V Power for KSZ8061MNX
C60
1
EN
2
VIN
R99
4.7K
2.2uF / 50V
VOUT
4
ADJ
5
VDDIO
1
R116
2
C54
FBEAD
R114
+ C19
220
+ C85
C58
2.49K
22uF Tant
3
opt
3.3V
FB1
2
JUMPER
3.3V_U2
R98
3.3V
3.3V
MIC29302WU / TO-263-5
GND
JP4
3.3V
U5
5.0V
1uF
10uF Tant
1uF
D2
R115
LED - RED SMD
1.50K
1
AVDDH
KSZ8061 Power
3.3V
FB2
J9
1
VOUT = 1.24 X [ 1 + ( R114 / R115 ) ]
Jumper
Closed: KSZ8061 is powered
Open: KSZ8061 is unpowered
1
2
2
C56
FBEAD
+ C14
1uF
10uF Tant
Term_Block_2
Open: Regulator enabled
Closed: Regulator controlled by SIGD pin of KSZ8061
VDDL
DVDDL
R46
VDDL_EN
3.3V
JP2
JUMPER
SIGD
(3)
VDDL
4.7K
FB3
1
2
FBEAD
U6
C5
2.2uF
VIN
GND
3
EN
VOUT
4
ADJ
5
BYP
6
10uF Tant
C81
10uF
1uF
R112
+ C28
C6
1.50K
10uF Tant
2
1
C27
+ C13
MIC5305_adj / MQF
AVDDL
1uF
C2
FB4
R113
1
0.1uF
26.7K
2
FBEAD
C25
C83
10uF
1uF
+ C15
DS50002449A-page 29
10uF Tant
VOUT = 1.25 X [ 1 + ( R112 / R113 ) ]
Schematic and Layouts
VDDL Power for KSZ8061MNX
KSZ8061MNX Evaluation Board User’s Guide
NOTES:
DS50002449A-page 30
 2016 Microchip Technology Inc.
KSZ8061MNX EVALUATION
BOARD USER’S GUIDE
Appendix B. Bill of Materials (BOM)
TABLE B-1:
BILL OF MATERIALS (BOM)
Item Quantity
Reference
Description
Footprint/Package
Manufacturer/Part Number
1
2
C9, C10
15 pF
0603
2
2
C11, C12
22 pF
0603
1000 pF/2 kV
Radial lead, thru hole Vishay S102K33Y5PP63K5R
3
2
C17, C29
4
10
C2, C8, C20, C26, 0.1 uF
C30, C31, C65,
C68, C73, C76
0402
5
11
C6, C22, C24,
C54, C56, C58,
C63, C69, C72,
C81, C83
1 uF
0603
6
2
C16, C18
1 uF
0805
7
3
C5, C7, C71
2.2 uF/10V, ceramic
0603
0603
TDK C1608X5R1A225K080AC
8
2
C60, C77
2.2 uF/50V, ceramic
1206
1206
Taiyo Yuden
UMK316BJ225KD-T
9
5
C3, C21, C23,
C25, C27
10 uF/10V, ceramic
0805
0805
TDK C2012X5R1A106K125AB
10
5
C13, C14, C15,
C19, C28
10 uF Tant
1210 (3528 metric)
11
2
C84, C85
22 uF Tant
1210 (3528 metric)
AVX TAJB226K016RNJ
12
1
C1
220 uF/50V Elect
Al Electrolytic
Panasonic ECA-1HM221
13
DNI 8
R32, R34, R53,
C90, C91, C92,
C93, C94
opt
0603
14
3
D1, D5, D6, D8,
D9
Diode
SOD-123
Diodes Inc BAV16W-7
Diodes Inc 1N4148W-7
Micro Commercial
1N4148W-TP
15
DNI 2
D8, D9
Diode
SOD-123
Diodes Inc BAV16W-7
Diodes Inc 1N4148W-7
Micro Commercial
1N4148W-TP
16
1
D2
LED - RED SMD
LED 0805
Lite-On LTST-C170CKT
Lumex SML-LXT0805IW-TR
17
DNI 1
D4
LED - RED SMD
LED 0805
Lite-On LTST-C170CKT
Lumex SML-LXT0805IW-TR
18
1
D3
LED - GREEN SMD
LED 0805
Lite-On LTST-C171GKT
Lumex SML-LX0805SGC-TR
19
DNI 1
D10
LED - GREEN SMD
LED 0805
Lite-On LTST-C171GKT
Lumex SML-LX0805SGC-TR
20
1
D7
LED, green, stacked
pair, right angle, thru
hole
Dual LED (thru hole)
Lumex SSF-LXH240GGD
Dialight 553-0122-300F
 2016 Microchip Technology Inc.
DS50002449A-page 31
MCP9600 Thermocouple IC Evaluation Board User’s Guide
TABLE B-1:
BILL OF MATERIALS (BOM) (CONTINUED)
Item Quantity
Reference
Description
Ferrite bead, 150
ohms at 600 MHz
Footprint/Package
3216 metric
Manufacturer/Part Number
21
7
FB1, FB2, FB3,
FB4, FB5, FB7,
R59
22
3
JP1, JP2, JP4
JUMPER
Header 2x1, standard 25 mil header pins, 100 mil pitch
23
1
JP3
3X1
Header 3x1, standard 25 mil header pins, 100 mil pitch
24
1
J6
RJ-45 Jack
RJ45-4P
TE 5558342-1
25
DNI 1
J1
RJ-45 Jack
RJ45-4P
TE 5558342-1
26
DNI 1
J2
MQS 4 Pos TE
1379165-1
1379165
TE 1379165-1
27
DNI 1
J3
Sumitomo 6098-6793 6098-6793
Sumitomo 6098-6793
28
DNI 1
J4
Female MII Connector, SCSI-2, 40-pin
Thru hole
TE 5787170-4
29
1
J5
Male MII Connector,
SCSI-2, 40-pin
PCB edge mount
Goal Ray Industry Co. Ltd
MDS-40MM-3-C2
30
1
J7
Header 5x2
HDR 5x2, standard
25mil header pins,
100mil pitch
FCI 67997-410HLF
31
1
J8
DC power connector,
barrel, 2.1 mm
Thru hole
CUI PJ-002A
Switchcraft RAPC722X
32
DNI 1
J9
Terminal block, 2 term Thru hole
33
1
L1
TDK ZJYS81
ZJYS81
TDK ZJYS81R5
34
2
L2, L3
Common mode
choke for signals
4532 metric 4ld
TDK ACT45B-101-2P
35
DNI 9
36
R1, R2, R3, R4,
Opt/0
R5, R6, R60, R91,
R92
0603
26
R11, R12, R13,
0
R14, R15, R16,
R21, R22, R23,
R24, R25, R26,
R62, R81, R211,
R212, R213,
R214, R215,
R216, R221,
R222, R223,
R224, R225, R226
0603
37
14
R20, R29, R30,
R64, R65, R66,
R67, R82, R83,
R84, R85, R86,
R87, R88
33
0402
38
1
R35
1K
0603
39
DNI 7
R36, R37, R38,
R39, R44, R70,
R93
Opt/4.7K
0603
40
11
R40, R41, R42,
R46, R51, R68,
R69, R74, R78,
R89, R99
4.7K
0603
41
DNI 4
R43, R71, R72,
R73
Opt/1K
0603
42
1
R45
6.49K
0603
DS50002449A-page 32
Steward/Laird
HI1206N101R-10
Phoenix 1984617
 2016 Microchip Technology Inc.
TABLE B-1:
BILL OF MATERIALS (BOM) (CONTINUED)
Item Quantity
Reference
Description
Footprint/Package
43
1
R47
12.1K
0603
44
8
R48, R49, R50,
R52, R54, R55,
R56, R57
75
0603
45
DNI 6
R58, R94, R95,
R96, R97, R98
Opt
1206
46
1
R63
0
1206
47
DNI 1
R61
0
1206
48
2
49
DNI 1
R75, R77
10K
0603
R122
10K
0603
50
6
R27, R28, R31,
R33, R76, R90
33
0603
51
4
R79, R80, R116,
R120
220
0603
52
DNI 2
R121, R123
220
0603
53
3
R112, R115, R118 1.50K, 1%
0603
54
1
R113
26.7K, 1%
0603
Manufacturer/Part Number
55
2
R114, R117
2.49K
0603
56
2
S1, S2
SW PUSHBUTTON
Switch (push button)
Panasonic EVQ-Q2Y03W
57
DNI 1
S3
SW PUSHBUTTON
Switch (push button)
Panasonic EVQ-Q2Y03W
58
DNI 7
TP1, TP2, TP3,
TP4, TP5, TP12,
TP33
TestPoint
Hole for standard 25
mil square header
pins
59
DNI 2
TP6, TP7
TestPoint
60 mil hole at U1 and
U2 center ground
pads
60
2
T1, T2
TDK TLA-8T104WLF SOIC16
TDK TLA-8T104WLF
Pulse H1102NL
61
1
U1
KSZ8061MNX
Microchip KSZ8061MNX
62
1
U2
KSZ8061MNX
32-QFN
Microchip KSZ8061MNX
63
1
U3
Microchip PL135-27
oscillator 1:2 fanout
buffer
DFN-6L
Microchip PL135-27
64
2
U4, U5
MIC29302WU adj. 3A TO-263-5
LDO
Microchip MIC29302WU
65
1
U6
MIC5305YML adj.
150 mA LDO
Micrel MIC5305YML
66
DNI 1
U7
74LVC1G175 single
SC70
flip flop w/ async clear
TI SN74LVC1G175DCK
67
1
Y1
25 MHz
5x3.2 mm, 2-ld
TXC 7A-25.000MAAE
NDK NX5032GA
CTS 445C23L25M00000
TXC AA-25.000MAGE
68
1
Y2
25 MHz
HC-49/SMD
ECS ECS-250-18-5PX-F
Abracon
ABLS-25.000MHZ-B4-F-T
TXC 9C-25.000MAAJ-T
ILSI
HC49USM-FB1F18-25.000
 2016 Microchip Technology Inc.
32-QFN
6-pin 2x2 mm MLF
DS50002449A-page 33
Worldwide Sales and Service
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DS50002449A-page 34
 2016 Microchip Technology Inc.