NCP1237: 32 W, 32 V Universal Input; Energy Star Adapter

AND8454/D
32 W, 32 V Universal Input
AC-DC Printer Adapter
using the NCP1237
Prepared by: Nicolas Cyr
http://onsemi.com
ON Semiconductor
APPLICATION NOTE
Introduction
Specification
This ac adapter demonstration board targets a printer
adapter application with a 32 V output, and a power
capability of up to 80 W transiently (for 150 ms) and 32 W
permanently. It exceeds the efficiency and standby power
requirements of the US ENERGY STAR® Specification for
External Power supplies (EPS) version 2.0.
It is built around the NCP1237, a fixed-frequency
controller featuring frequency foldback and Soft-Skipt to
maximize efficiency in light load conditions. Additional
functions include dual-level overcurrent protection for
transient peak power, line voltage sensing for Brown-out
protection, as well as overpower compensation to ensure a
constant overload protection independent of the input
voltage (for a detailed description of all these functions and
recommendations on how to use this controller, please refer
to the NCP1237 datasheet and other related documents at
www.onsemi.com.
The demonstration board must operate across universal
inputs, 85 Vac to 265 Vac (47 Hz to 63 Hz), and supply a
regulated 32 V output capable of delivering 1 A
continuously (32 W), and up to 2.5 A (80 W) for at least
120 ms, as defined in Figure 1. Its average efficiency as
defined by ENERGY STAR should be higher than 87%
(therefore exceeding the EPS 2.0 requirement of 84%), and
its no load input power must be lower than 150 mW. In
addition, the efficiency at an output of 1.0 W must be greater
than 70%. The specification is summarized in Table 1.
IOUT
120 ms
2.5 A
1.0 A
t
2s
Figure 1. Transient Output Current Specification
Table 1: Summary of Specifications
Requirement
Input Voltage
Min
Max
Unit
85
265
Vac
Line Frequency
47
63
Hz
Output Voltage
31.5
32.5
Vdc
Output Current
−
1.0
(2.5 transient peak for 120 ms)
Adc
Output Power
−
32
(80 transient peak for 120 ms)
W
Average Efficiency (as defined by ENERGY STAR)
87
−
%
Efficiency at an output power of 1.0 W
70
−
%
No Load Input Power
−
150
mW
Output Ripple Voltage
−
±200
mV
© Semiconductor Components Industries, LLC, 2010
April, 2010 − Rev. 1
1
Publication Order Number:
AND8454/D
AND8454/D
Design Procedure
The demonstration board schematic is based on the typical
application schematic for the NCP1237, provided in
Figure 2.
We will only highlight the design of the main components
of the power supply. For a more comprehensive step-by-step
design of a flyback converter, please refer to the
ON Semiconductor website (www.onsemi.com).
VIN
(dc)
VOUT
Rupper
OVP
LATCH
FB
CS
GND
HV
NCP1237
VCC
DRV
Ropc
Rbottom
Rs
Figure 2. Typical Application Schematic
There is not one single recipe to design a flyback
converter: one can initiate the design procedure with any of
the power components and walk his way through the
schematic. Each selection of a component restricts the
choice for the others in order to meet the specification.
For the design of this printer adapter, the specification the
most restrictive is the efficiency requirement: with such an
aggressive target, the design procedure must focus on
minimizing the losses. In a nutshell, we will strive to
combine low peak current, well balanced reflected voltages
on primary and secondary side, and low dissipation in
snubbers and clamps.
The maximum voltage that we allow across the rectifier is:
V MAX(rect) + V RRM @ K derating(rect)
(eq. 1)
Where Kderating(rect) is the derating applied on the
maximum reverse voltage across the rectifier, and VRRM the
maximum reverse voltage allowed for the rectifier.
Solving for a derating of 80 % and a reverse voltage of
150 V, VMAX(rect) must be less than 120 V. We have to keep
in mind that this not only includes the reflected voltage from
primary during on time, but also the voltage peak that
appears on the anode of the rectifier when the MOSFET
turns on. Let us now define Ksnub, the ratio between the
maximum negative voltage (VMAX(rect) – VOUT) and the
reflected voltage VReflect(sec): it represents the amount of
overshoot beyond the reflected voltage plateau. The larger
this ratio is, the lower the dissipation in the snubber that will
be placed across the secondary rectifier.
Output Rectifier
We’ll start the design from the secondary rectifier. The
reason is that ON Semiconductor offers a low VF Schottky
diode very well suited for a high efficiency adapter, the
MBR20H150, but its maximum reverse voltage is 150 V.
After deducing the output voltage, and applying a derating
on the maximum reverse voltage, there is not much voltage
left allowed across the secondary winding. Refer to Figure 3
for a graphical explanation of the following calculations.
V Reflect(sec) + (V MAX(rect) * V OUT) @ K snub
(eq. 2)
Solving for a snubber ratio of 1.4 and an output voltage of
32 V gives a reflected voltage of 62.5 V.
This imposes the turns ratio of the transformer, following
equation 3.
VA
V Reflect(sec) + V IN(dc) @
VOUT
NS
NP
(eq. 3)
Solving for the maximum VIN(dc)max of 375 V, it gives a
turns ratio NP / NS = N = 6
t
Primary MOSFET
Knowing the output voltage and the turns ratio, we can
calculate the reflected voltage from secondary side to
primary side of the transformer during off time:
VMAX(rect)
VReflect(sec)
V Reflect(prim) + V OUT @ N
(eq. 4)
Solving for the values calculated above gives a reflected
voltage across the primary winding of 192 V.
Figure 3. Typical Voltage VA on the Anode of the
Rectifier
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duration corresponds exactly to the demagnetization time of
the transformer. In other words, the secondary current
reaches 0 exactly when the MOSFET is turned back on, as
shown on Figure 5.
VD
VBVDSS
IL
VReflect(prim)
VIN
IP(BCM)
t
1 / FSW
Figure 5. Transformer Current at the DCM-CCM
Transition
As shown on Figure 4, we can now calculate the minimum
breakdown voltage of the MOSFET VBVDSS using equation
5. Kderating(switch) is the derating applied on the breakdown
voltage of the transistor and Kclamp the ratio between the
maximum voltage that appears on the drain of the transistor
and the reflected voltage to the primary.
V IN(dc)max ) V Reflect(prim) @ K clamp
K derating(switch)
t
t Off
t ON
Figure 4. Typical Voltage VD on the Drain of the
MOSFET
V BVDSS +
N.(VOUT+VP)
LP
VIN
LP
As a result, we can write:
t ON ) t OFF +
L p @ I P(BCM)
V IN
)
L p @ I P(BCM)
N @ (V OUT ) V F)
+ 1 (eq. 6)
F SW
In addition, the output power can be defined as the power
transferred from primary to secondary multiplied by the
overall efficiency η of the conversion; the transferred power
being the energy stored in the primary inductor during one
cycle multiplied by the switching frequency. In the BCM
case the output power is then equal to:
(eq. 5)
Solving for a clamped-to-reflected voltage ratio of 1.4 and
a derating of 80%, we find that VBVDSS should be at least
805 V.
We will choose an 800 V MOSFET and adjust the clamp
voltage.
Note that if no derating is applied on the MOSFET and/or
the rectifier, and/or we use the avalanche capability of the
these components to clamp the voltage overshoots, the same
converter could be designed with a 650 V or even a 600 V
MOSFET (and a lower turns ratio, of 5 for example).
However we will stick to the safe design calculated above,
as our purpose is primarily to demonstrate the capabilities
of the NCP1237 controller.
P OUT(BCM) + 1 @ L p @ I P(BCM) @ F SW @ h
2
2
(eq. 7)
From which we can extract IP:
I P(BCM) +
Ǹ
2 @ P OUT(BCM)
L p @ F SW @ h
(eq. 8)
Replacing IP in equation 6 using equation 8, we obtain a
way of calculating the primary inductance LP, dependent on
the output power Pout(BCM) at which the application
transitions from DCM to CCM:
Transformer
2
Lp +
We will design the transformer in such a way that the
converter runs in discontinuous conduction mode (DCM) in
normal conditions, and enter continuous conduction mode
(CCM) during peak power transients. Since the duration of
these transients is safely clamped by the NCP1237’s
transient timer, the transformer doesn’t need to be designed
thermally for the 80 W peak power, but only for 32 W. It
must however be able to deliver the peak output current of
2.5 A without saturating.
At the transition from DCM to CCM, the converter runs
in Borderline Conduction Mode (BCM), and the off time
h @ V IN(dc) @ N 2 @ (V OUT ) V F) 2
2 @ F SW @ P OUT(BCM) @ (V IN(dc) ) N @ (V OUT ) V F)) 2
(eq. 9)
Solving for an efficiency of 87 %, a transition output
power of 32 W and an input voltage of 100 V, we obtain LP
= 916 mH.
We will choose 1 mH, as it will further reduce the peak
current, and give us a nice round number to ease up the rest
of the calculations. With 1 mH and 100 V, the adapter will
transition from DCM to CCM at 29.3 W at 100 V.
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AND8454/D
Let us now calculate IP(max), for an output power of 80 W.
The converter is now running in CCM, and the current in the
inductor doesn’t go to 0 at the end of each cycle, as shown
in Figure 6.
This time the power equation is different, since only the
energy corresponding to the current variation is transferred
to the secondary.
IL
IP(max)
N.(VOUT+VP)
LP
VIN(min)
LP
DIP(max)
IP(max) − DIP(max)
t
t Off
t ON
1 / FSW
Figure 6. Inductor Current in CCM
ǒ
Ǔ
2
P OUT(max) + 1 @ L p @ I P(max) * 1 @ L p @ (I P(max) * DI P(max)) 2 @ F SW @ h
2
2
(eq. 10)
From it we can calculate IP:
I P(max) +
P OUT(max)
DI P(max) @ L p @ F SW @ h
)
DI P(max)
2
(eq. 11)
From Figure 6, we can also define ΔIP as:
DI P(max) +
With
L p@DI P(max)
V
t ON(max)
IN(min)
D MAX +
+ L @DI
L p@DI P(max)
t ON(max) ) t OFF(max)
p
P(max)
) N@(V @V )
V
IN(min)
OUT
V IN(dc) D MAX
@
LP
F SW
, that simplifies into
(eq. 12)
D MAX +
N @ (V OUT ) V F)
(eq. 13)
V IN(min) ) N @ (V OUT ) V F)
F
Using equations 12 and 13 we can rewrite equation 11 as follows:
I P(max) +
P OUT(max) @ (V IN(min) ) N @ (V OUT ) V F))
N @ V IN(min) @ (V OUT ) V F) @ h
Solving for the maximum power of 80 W at the minimum
voltage of 100 V, we find that the maximum peak current is
IP(max) = 1.90 A, with ΔIP(max) = 1.02 A and DMAX = 66 %.
)
N @ V IN(min) @ (V OUT ) V F)
2 @ L p @ F SW @ (V IN(min) ) N @ (V OUT ) V F))
RS +
V ILIM(min)
I P(max)
(eq. 14)
(eq. 15)
Solving with VILIM(min) = 0.665 V and IP(max) = 1.9 A, it
gives RS = 0.35 W. Knowing that the previously calculated
value for IP(max) didn’t take into account any tolerances, we
will choose 0.33 W for the sense resistor.
In the final schematic, the designator for the sense resistor
is R7.
Sense Resistor
The sense resistor RS is easily calculated from the IP(max)
value, knowing the threshold of the current sense
comparator.
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Overpower Compensation Resistor
This means that even if the peak currents are the same at low
and high line, the minimum current aren’t: there is a
difference δIV, as shown on Figure 7. Therefore the
maximum powers aren’t the same in both cases, according
to Equation 10.
We will need an extra offset to compensate for this effect.
It can be calculated, but it involves a complicated equation,
since we want to compensate for the difference in the valleys
of the primary currents by offsetting the peak. This is not
easy, so we will rather increase the value for the
compensation resistor, and we will adjust it if needed after
testing the board.
We choose to increase ROPC by 50%, i.e. ROPC = 1.2 kW.
In the final schematic, the designator for the overpower
compensation resistor is R4.
There is a propagation delay from when the current
reaches the maximum programmed value to when the
MOSFET actually turns off: it is the sum of the internal
propagation delay of the controller (speed of the CS
comparator, the internal logic and the output driver), and the
external propagation delay (any resistor between the DRV
pin and the MOSFET’s gate, and the turn-off time of the
MOSFET). This delay is fairly constant, but the slope of the
current is proportional to the input voltage, as shown on
Figure 7. As a result the actual maximum power that the
application can deliver increases with the input voltage.
t prop
IL
δI P
VILIM
RS
Low line
Slope Compensation
Because the application runs in CCM at a duty ratio higher
than 50% at low input voltage, slope compensation is needed
to prevent sub-harmonic oscillations. Thankfully the
NCP1237 already includes internal slope compensation, so
there is nothing to adjust.
High line
δI V
Overvoltage Protection
Building an Overvoltage Protection (OVP) using the latch
pin of the NCP1237 is very simple. All is needed is to
connect a Zener diode between the voltage to be sensed and
the pin. No additional resistor is required, as the current is
internally limited.
In our application, we choose to connect a 17 V zener
diode between the supply voltage VCC and the Latch pin: as
soon as the output voltage increases, the supply voltage
increases as well, and the Latch pin follows. When the Latch
pin voltage reaches 2.5 V, corresponding to 19.5 V on the
VCC capacitor, the OVP is triggered, and the controller gets
latched off.
In the final schematic, the designator for the OVP zener
diode is ZD1.
t
Figure 7. Delay from Max Peak Current to Turn-off
From Figure 7, we can calculate the peak current increase
between two different input voltages:
dI P +
(V IN2 * V IN1) @ t Prop
LP
(eq. 16)
In our case we are interested in δIP(max), the peak current
increase from the lowest to the highest input voltage.
However, this equation requires the total propagation delay,
which we can’t know at this moment. We will thus use an
estimated value of 1 ms, keeping in mind that we may have
to optimize this value later if the propagation delay turns out
to be significantly different than the assumed value. Solving
for VIN(min) = 100 V and VIN(max) = 375 V, we obtain a
δIP(max) of 275 mA.
To compensate for that, the maximum peak current
threshold must be reduced when the input voltage increases.
This is achieved in the NCP1237 by sourcing a current
proportional to VIN out of the CS pin: inserting a
compensation resistor ROPC between the CS pin and the
sense resistor RS adds an offset to the current sense signal,
which is equivalent to reducing the peak current.
Since the compensation current is 0 at low line, we just
need to estimate what offset is needed at high line to be able
to calculate ROPC.
R S @ dI P(max)
R OPC +
I OPC
Output Regulation and Feedback Loop
The feedback loop is classically built around a TL431,
which provides reliable regulation with few components
and at a low cost. We want to minimize the bias current in the
resistor divider that senses the output voltage, as the losses
associated with this bias current can be significant in no-load
condition.
Let us choose a 20 kW bottom resistor Rbottom, which
limits the bias current to 125 mA since the reference voltage
of the TL431 Vref is 2.495 V.
The upper resistor can be calculated from equation 18:
R upper + R bottom @
(eq. 17)
V OUT * V REF
V REF
(eq. 18)
Solving for VOUT = 32 V, we obtain a value of 236.5 kW.
We will choose a normalized value of Rupper = 237 kW.
In the final schematic, the designator for the upper resistor
is R31, and R32 for the bottom resistor.
That leads to a compensation resistor of 800 W.
However, when the primary current is close to the
maximum, the converter is running in CCM, not in DCM.
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Final Schematic
R17
D13
T1
R18
D2
R1
JP3
C6
R2
C10
R14
R41
R5
D6
R11
ZD1
C2
U3B
C4
R8
R4
C5
D5
C3
C16
C8
Q5
C15
ZD4
R7
C9
Figure 8. Final Schematic of the Printer Evaluation Board
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C19
U4
R37
C21
R31
U3A
R6
U1
R24
C7
R13
NCP1237
R23
D1
R15
R3
32 V
D7
J1
VIN
L1
T2
C1
F1
C14
R32
0V
AND8454/D
Bill of Materials
Table 2: Bill of Materials of the Printer Evaluation Board
Reference
Value
Manufacturer
Description
Part number
C1
330 nF / 250 Vac
Kemet / Evox-Rifa
X2 film capacitor − 8.5x18 mm
PHE840MX6330MB11
C2, C4
1 nF / 25 V
Vishay
0805 ceramic
C3
100 nF / 50 V
Vishay
0805 ceramic
C5, C21
open
−
−
C6
100 mF / 400 V
United Chemicon
Electrolytic capacitor − 18x32 mm
EKXG401ELL101MMN3S
C7
47 mF / 50 V
United Chemicon
Electrolytic capacitor
ECA-1HM470
C8
100 nF / 50 V
Vishay
0805 ceramic
C9
2.2 nF / 250 Vac
Kemet / Evox-Rifa
Y2 film capacitor
PHE850EA4220MA01R17
C10
6.8 nF / 630 V
TDK
mid-voltage ceramic through-hole
FK20COG2J682J
C14
1.0 nF / 250V
TDK
mid-voltage ceramic through-hole
FK24C0G2E102J
C15
470 mF / 50 V
United Chemicon
Electrolytic capacitor
ECA-1HM471
C16
220 mF / 50 V
United Chemicon
Electrolytic capacitor
ECA-1HM221
C19
10 nF / 50 V
Vishay
1206 ceramic
D1
MUR1100
ON Semiconductor
1 A / 1 kV through-hole rectifier
MUR1100EG
D2
W06G
Vishay
600 V through-hole bridge rectifier
W06G-E4/51
D5, D6
MMSD4148
ON Semiconductor
SOD123 commutation diode
MMSD4148T1G
D7
MBRF20H150
ON Semiconductor
TO220 fullpack 20 A / 150 V Schottky
MBRF20H150CTG
D13
1N4007
ON Semiconductor
1 A / 1000 V through-hole rectifier
1N4007G
F1
2.0 A
Littelfuse
392 series radial fuse
3921200
HS1, HS2
Heatsink
custom
Heatsink - 30x20x1.5 mm
J1
770W-X2/10
Qualtek
AC connector
JP3
open
−
Jumper
L1
4.7 mH / 4.2 A
Coilcraft
Power inductor
RFB0807-4R7L
Q5
4N80 fullpack
Infineon
4 A / 800 V MOSFET - TO220 fullpack
SPA04N80C3
R1, R2
1.5 MW / 200 V
Vishay
1206
R3
14 kW
Vishay
0805
R4
1.2 kW
Vishay
0805
R5, R41
1 kW / 200 V
Vishay
1206
R6
10 W
Vishay
1206
R7
0.33 W
2512
R8
47 W / 0.5 W
Axial through-hole
R11
10 W
Vishay
1206
R13
0W
Vishay
1206
R14
200 kW / 0.5 W
R15
2.2 mH
Vishay
inductor 1206
R17, R18
200 W / 200 V
Vishay
1206
R23
10 kW
Vishay
1206
R24
3.3 kW
Vishay
1206
R31
237 kW / 1%
Vishay
0805
R32
20 kW / 1%
Vishay
0805
R37
10 kW
Vishay
0805
T1
2 x 10 mH
Epcos
Vertical common-mode choke
B82732R2142B030
T2
TO09161
Ice Components
Custom
TO09161
U1
NCP1237A 65kHz
ON Semiconductor
Fixed-frequency CM controller
NCP1237AD65DR2G
U3
PS2561
CEL-NEC
Optocoupler
PS2561-1-L-A
U4
TL431B
ON Semiconductor
Adj. Voltage Reference - TO-92
TL431B
ZD1
17 V
ON Semiconductor
SOD123 Zener diode
MMSZ5247BT1G
ZD4
open
−
−
770W-X2/10
Axial through-hole
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Board Layout
During the layout process care was taken to minimize high
current loops area and keep sensitive nodes away from noisy
nodes.
Figures 9, 10 and 11 show the top and bottom layers of the
PC board.
The demonstration board is built using a single sided FR4
board. Through hole components are placed on the top layer
and surface mount components on the bottom layer. The
board is constructed using 2 oz copper.
Figure 9. Top Layer Silkscreen
Figure 10. Bottom Layer Silkscreen
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Figure 11. Bottom Layer Copper
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Board Performance
Efficiency
period of 6 minutes per measurement. All output
measurements were performed at the end of a 0.6 m long
cable.
All input power measurements were performed using a
WT210 power meter from Yokogawa, in Wh mode over a
Energy Star Measurements:
115 Vac
230 Vac
EPS 2.0 Compliance
32 W (100 %)
88.9 %
89.7 %
PASS
24 W (75 %)
88.7 %
88.9 %
16 W (50 %)
88.1 %
88.1 %
8 W (25 %)
86.7 %
86.3 %
Average
88.1 %
88.3 %
PASS
No load input power
92 mW
133 mW
PASS
Additional Efficiency Measurements:
115 Vac
230 Vac
3.2 W
82.1 %
79.7 %
1.89 W
78.0 %
76.0 %
0.93 W
72.6 %
69.9 %
0.48 W
65.4 %
62.1 %
Oscilloscope Shots
Figures 12 to 29 show typical waveforms and demonstrate the compliance to the specification.
Figures 12 and 13: the adapter operates in DCM below 32 W at low and high line
Figures 14 and 15: the frequency is reduced in light load condition
Figures 16 to 19: the controller enters skip mode in no load condition
Figures 20 to 23: the ripple on the output is less than 200 mV in all conditions
Figures 24 and 25: the adapter can deliver 2.5 A during 120 ms
Figures 26 and 27: the output stays within ±500 mV during no load to full load load steps
Figure 28 and 29: no overshoot appears on the output during start-up
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Figure 12. Drain Voltage in Full Load Condition
(1 A at 115 Vac)
Figure 13. Drain Voltage in Full Load Condition
(1 A at 230 Vac)
Figure 14. Drain Voltage in Light Load Condition
(150 mA at 115 Vac)
Figure 15. Drain Voltage in Light Load Condition
(150 mA at 230 Vac)
Figure 16. Skip Mode Observed on the Drain
Signal in No Load Condition at 115 Vac
Figure 17. Skip Mode Observed on the Drain
Signal in No Load Condition at 230 Vac
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Figure 18. Zoom on the Drain Voltage in No
Load Condition at 115 Vac
Figure 19. Zoom on the Drain Voltage in No
Load Condition at 230 Vac
Figure 20. Output Voltage Ripple in No Load
Condition at 115 Vac
Figure 21. Output Voltage Ripple in No Load
Condition at 230 Vac
Figure 22. Output Voltage Ripple in Full Load
Condition (1 A at 115 Vac)
Figure 23. Output Voltage Ripple in Full Load
Condition (1 A at 230 Vac)
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Figure 24. Output Voltage during Peak Power
(1 A to 2.5 A to 1 A at 115 Vac)
Figure 25. Output Voltage during Peak Power
(1 A to 2.5 A to 1 A at 230 Vac)
Figure 26. Output Voltage during a Load Step
(1 A to 0 A to 1 A at 115 Vac)
Figure 27. Output Voltage during a Load Step
(1 A to 0 A to 1 A at 230 Vac)
Figure 28. Output Voltage during Start-up
(1 A at 115 Vac)
Figure 29. Output Voltage during Start-up
(1 A at 230 Vac)
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Disclaimer: This demonstration board is designed to demonstrate the features and flexibility of the NCP1237. This design
is a guideline only and does not guarantee performance for any manufacturing or production purposes.
Soft−Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC). ENERGY STAR and the ENERGY
STAR mark are registered U.S. marks.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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