KSZ8462-8441_eval_bd_v1.1_schematic

5
4
3
2
1
KSZ8462HLL_LQFP Demo Board Revision 1.1
REVISION HISTORY
Table of Contents
D
D
DATE:
DESCRIPTION
REVISION
12/17/2010
Initial release
1.0
11/16/2011
2.5V/1.8V regulator schematic is corrected
1.1
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
01:
02:
03:
04:
05:
06:
07:
Revision History
KSZ8462HLL Device and CPU Port
Device Configuration and LEDs
Ethernet Interface
Fiber Interface1
Fiber interface2
Power
C
C
B
B
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8462HLL DEMO BOARD
Size
Document Number
Rev
1.1
Revision History
Date:
5
4
3
2
Wednesday, November 16, 2011
Sheet
1
1
of
7
4
3
2
VDD_IO
Serial EEPROM
MAC Address / User Data
JP409
D
R218
1K
8
7
6
5
VCC
NC
ORG
GND
2X1
MBR0520L
D16
U2
CS
SK
DI
DO
RSTN
R241
PME_EESEL R235
C117
R15
R16
R17
R22
R26
4.7K
4.7K
4.7K
4.7K
CPU_RSTN
CPU_PME
33
33
INTRN
R215
33
SD0
SD1
SD2
SD3
SD4
SD5
SD6
R240
R239
R238
R237
R236
R234
R233
33
33
33
33
33
33
33
+1.2V
33
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPIO1
GPIO2
GPIO3_EESK
GPIO4_EEDIO
GPIO5_EECS
R226
33
R217
R225
R227
R224
33
33
33
33
R228
33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
C
GPIO6
Sht.3
Sht.3
Sht.3
Sht.3
P1LED1
P1LED0
P2LED1
P2LED0
Sht.5
FXSD1
P1LED1
P1LED0
P2LED1
P2LED0
RST_SWN
KSZ_FXSD1
J12
1
3
2
4
GPIO1
DGND
VDD_1.2
GPIO2
GPIO3/EESK
GPIO4/EED_IO
GPIO5/EECS
VDD_IO
DGND
GPIO6
P1LED1
P1LED0/H816
P2LED1
P2LED0/LEBE
RSTN
FXSD1
CON4A
SD7
SD8
VDD_IO
DGND
SD9
SD10
SD11
SD12
SD13
SD14
SD15
VDD_IO
DGND
X2
X1
PWRDN
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
+3.3A
VDD_IO
Note: place series resistors
near pins of KSZ8462HLL
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
CPU_D1
CPU_D3
CPU_D5
CPU_D7
CPU_D9
CPU_D11
CPU_D13
CPU_D15
SD7
SD8
R232
R231
33
33
CPU_D7
CPU_D8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
R230
R229
R223
R222
R221
R220
R219
33
33
33
33
33
33
33
CPU_D9
CPU_D10
CPU_D11
CPU_D12
CPU_D13
CPU_D14
CPU_D15
X1
Power_ON
Reset
+
2
4
2X1
R6
STEWARD
2X1
HI1206N101R-00
+5V
FB24
1
2
FBEAD
R8
4.7K
CON4A
FX Detect
FX Mode
FXSD2
TX Mode
SW PUSHBUTTON
+
C4
R4
6.49K
10UF
Do not populate
cap if pull down
is used
TP10
C116
0.1UF
2
4
1-2 for Fiber,
3-4 for RJ45
TP9
C5
10UF
R9
1K
1
2
3
JP77
B
3X1
+3.3A
FXSD2
DIFFERENTIAL_PAIR = DP2
DIFFERENTIAL_PAIR = DP2
R10
4.7K
Do not populate
cap if pull down
is used
TX Mode
+
C6
R11
1K
DIFFERENTIAL_PAIR = DP4
DIFFERENTIAL_PAIR = DP4
FX Detect
FX Mode
FXSD1
C
C2
18PF
Y1
25MHz
Chip Power Down
(active low)
1K
1
3
TXM2
TXP2
RXM2
RXP2
TXM1
TXP1
S2
1
3
B
RXM1
RXP1
10K
CPU_D0
CPU_D2
CPU_D4
CPU_D6
CPU_D8
CPU_D10
CPU_D12
CPU_D14
JP3
C1
18PF
KSZ_FXSD2
Push Button
Reset
Note: CPU_D[15:8] must be tied
to GND in 8-bit bus mode.
90131-0780
J13
R5
Note: VDD_IO must be compatible
with master plugged into parallel port.
CPU_D[15:0]
+3.3A
D2
MBR0520L
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
X2
JP2
VDD_CO1.2
+1.2A
J16
X2
X1
PWRDN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1-2 for Fiber,
3-4 for RJ45
KSZ8462HLL
RXM1
RXP1
AGND
TXM1
TXP1
VDD_A1.2
ISET
AGND
VDD_A3.3
RXM2
RXP2
AGND
TXM2
TXP2
FXSD2
VDD_CO1.2
GPIO
Header
CPU_D0
CPU_D1
CPU_D2
CPU_D3
CPU_D4
CPU_D5
CPU_D6
Note: KSZ8462HLL is parallel port slave device
VDD_IO
Sht.3
D
U11
GPIO0
CSN
PME/EESEL
WRN
RDN
INTRN
CMD
SD0
VDD_1.2
DGND
SD1
SD2
SD3
SD4
SD5
SD6
VDD_IO
CPU_PME
CPU_CSN
CPU_WRN
CPU_RDN
CPU_INTRN
CPU_CMD
0.1UF
Note: ORG = "1" for x16 organization
R216
VDD_IO VDD_IO
4.7K
CAT93C66LI-G
GPIO0
VDD_IO VDD_IO
NOTE: install jumper for bi-directional RSTN
VDD_IO
1
2
3
4
1
CPU_+5V
5
1
2
3
DIFFERENTIAL_PAIR = DP1
DIFFERENTIAL_PAIR = DP1
JP78
DIFFERENTIAL_PAIR = DP3
DIFFERENTIAL_PAIR = DP3
3X1
10UF
Sht.6
TXP2
TXM2
Sht.6
Sht.6
RXP2
RXM2
Sht.6
Sht.6
TXP1
TXM1
Sht.5
Sht.5
RXP1
RXM1
Sht.5
Sht.5
GPIO HEADER
A
A
J15
GPIO6
GPIO5_EECS
GPIO4_EEDIO
GPIO3_EESK
GPIO2
GPIO1
GPIO0
13
11
9
7
5
3
1
14
12
10
8
6
4
2
CONFIDENTIAL & PROPRIETARY
Title
KSZ8462HLL DEMO BOARD
2x7
Size
Document Number
Rev
1.1
KSZ8462 Device and CPU Port
Date:
5
4
3
2
Wednesday, November 16, 2011
Sheet
1
2
of
7
5
4
3
+3.3V_EXT
D
Sht.2
P1LED1
R31
220
SPEED
D14
6
2
1
FDY3000NZ
Q1-2
SC89
Sht.2
1
+3.3V_EXT
R60
220
FDY3000NZ
Q1-1
2
P1_LED1
1
P1_LED0
3
2
D
4
LEDX2
LINK / ACT
3
5
P1LED0
4
SC89
+3.3V_EXT
+3.3V_EXT
R188
220
FDY3000NZ
Q2-1
Sht.2
P2LED1
R34
220
SPEED
D15
6
2
1
FDY3000NZ
Q2-2
SC89
P2_LED1
1
P2_LED0
3
2
4
LEDX2
3
LINK / ACT
C
C
Sht.2
5
P2LED0
4
SC89
VDD_IO
R128
4.7K
1
2
3
R127
1K
JP301
3X1
Strapping / Configuration Options
B
VDD_IO
JP301
Parallel Bus Width Select
1 = 16-bit Bus Width (default)
B
0 = 8-bit Bus Width
R124
4.7K
Parallel Bus Endian Mode Select
1
2
3
R123
1K
JP302
JP302
1 = Little Endian (default)
0 = Big Endian
3X1
JP303
EEPROM Select
1 = EEPROM Present
0 = EEPROM Not Present (default)
VDD_IO
R130
4.7K
1
2
3
Sht.2 CPU_PME
A
R129
1K
JP303
A
3X1
CONFIDENTIAL & PROPRIETARY
Title
KSZ8462HLL DEMO BOARD
Size
Document Number
Rev
1.1
Device Configuration and LEDs
Date:
5
4
3
2
Wednesday, November 16, 2011
Sheet
1
3
of
7
5
4
3
2
1
Compatible Isolation Transformers
C87
1000pf/2KV
Pulse H1102
R242
Transpower HB726
DNI
Bel Fuse S558-5999-U7
10.0M 5%
.5W
1
2
3
4
5
6
7
8
DELTA LF8505
CHASSIS GND
RX1P
RX1M
TX1P
1
2
3
4
5
6
7
8
LanKom LF-H41S
D
T1
R183
R184
51
51
R171
51
R172
75
CMT1
TX1M
R185
R186
51
51
R174
51
C66
TX1P
CMT1
TX1M
1000PF/2KV
RX1P
10 SHLD
9 SHLD
D
RJ45 CAT5 SHLD
J1
RX1M
16
15
14
13
12
11
10
9
TX+
TCM
TXNC
NC
RX+
RCM
RX-
1
2
3
4
5
6
7
8
TD+
TC
TDNC
NC
RD+
RC
RD-
TXP_1
DIFFERENTIAL_PAIR = DP7
TXM_1
DIFFERENTIAL_PAIR = DP7
RXP_1
DIFFERENTIAL_PAIR = DP9
RXM_1
DIFFERENTIAL_PAIR = DP9
H1102
C67
Sht.5
TXM_1
Sht.5
RXP_1
Sht.5
RXM_1
Sht.5
C68
0.1uF
Line Side Protection (test option)
TXP_1
0.1uF
Chip Side Protection (test option)
Place near RJ-45 connector
D6
4
5
TXP_1
1
8
7
2
7
6
3
6
4
5
RXP_1
RX1M
3
C
RX1P
PLC03-3.3
PLC03-3.3
PROTEK
DEVICES
PROTEK
DEVICES
RX1P
1
TX1P
D7
2
TX1P
TXM_1
C
4
3
RX1M
D8
SR3.3
SR3.3
PROTEK
DEVICES
PROTEK
DEVICES
1
2
TX1M
3
8
2
1
4
D5
TX1M
RXM_1
Compatible Isolation Transformers
C88
1000pf/2KV
Pulse H1102
R243
Transpower HB726
DNI
10.0M 5%
.5W
LanKom LF-H41S
RJ45 CAT5 SHLD
J2
1
2
3
4
5
6
7
8
RX2P
RX2M
TX2P
1
2
3
4
5
6
7
8
DELTA LF8505
CHASSIS GND
B
T2
R18
R21
51
51
R19
51
R20
R23
R25
51
51
R24
51
C9
75
CMT2
TX2M
TX2P
CMT2
TX2M
1000PF/2KV
RX2P
10 SHLD
9 SHLD
B
Bel Fuse S558-5999-U7
RX2M
16
15
14
13
12
11
10
9
TX+
TCM
TXNC
NC
RX+
RCM
RX-
1
2
3
4
5
6
7
8
TD+
TC
TDNC
NC
RD+
RC
RD-
TXP_2
DIFFERENTIAL_PAIR = DP11
TXM_2
DIFFERENTIAL_PAIR = DP11
RXP_2
DIFFERENTIAL_PAIR = DP13
RXM_2
DIFFERENTIAL_PAIR = DP13
H1102
C10
Sht.6
TXM_2
Sht.6
RXP_2
Sht.6
RXM_2
Sht.6
C11
0.1uF
Line Side Protection (test option)
TXP_2
0.1uF
Chip Side Protection (test option)
Place near RJ-45 connector
D10
TXP_2
7
2
7
6
3
6
RXP_2
RX2M
TX2P
4
5
TX2P
RX2P
4
RX2P
5
PLC03-3.3
PLC03-3.3
PROTEK
DEVICES
PROTEK
DEVICES
2
A
TXM_2
4
8
D11
D12
SR3.3
SR3.3
PROTEK
DEVICES
PROTEK
DEVICES
RXM_2
1
1
3
3
RX2M
2
2
TX2M
4
8
3
1
1
D9
TX2M
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8462HLL DEMO BOARD
Size
Document Number
Rev
1.1
Ethernet Interface
Date:
5
4
3
2
Wednesday, November 16, 2011
Sheet
1
4
of
7
5
4
3
2
1
JP10
3X1
1
2
3
+3.3V_EXT
+5V
STEWARD HI1206N101R-00
Place components
in dotted box
close to fiber
transceiver
FB4
D
1
2
FBEAD
C13
VCC_FT1
Route TX pairs on
component side
FB5
0.1UF
1
C15
C14
+
0.1UF
C16
47UF / 16V
These components are DNI
regardless the Fiber
Transceiver is used or not
Refer to fiber
transceiver's
reference design
for the actual
values of these
resistors
2
FBEAD
0.1UF
D
Route RX pairs on
solder side
VCC_FT1
Route TX & RX
differential pairs
close together,
8mil/8mil parallel
spacing, and keep
other signals 20 mil
(minimum) away
+3.3A
C17
VCCRX1
VCCTX1
DIFFERENTIAL_PAIR = DP1
0.1UF
C18
R64
R65
R66
TX
N/C
RX
1x9/SC/SIP
N/C
TX_GND
TD+
TDVCCTX
VCCRX
SD
RDRD+
RX_GND
9
8
7
6
5
4
3
2
1
82
82
130
FT_TDP1
FT_TDM1
DIFFERENTIAL_PAIR = DP18
DIFFERENTIAL_PAIR = DP18
FT_SD1
FT_RDM1
FT_RDP1
DIFFERENTIAL_PAIR = DP14
DIFFERENTIAL_PAIR = DP14
R63
49.9
49.9
DIFFERENTIAL_PAIR = DP1
C
0.1UF
R62
R67
TXP1
Sht.2
TXM1
Sht.2
TXP_1
Sht.4
TXM_1
Sht.4
RXM_1
Sht.4
RXP_1
Sht.4
RXM1
Sht.2
RXP1
Sht.2
C
130
C19
0.1UF
FT_TXP1
DIFFERENTIAL_PAIR = DP20
R195
R
R199
0
DIFFERENTIAL_PAIR = DP7
C20
0.1UF
FT_TXM1
DIFFERENTIAL_PAIR = DP20
R196
R
R200
0
DIFFERENTIAL_PAIR = DP7
C21
0.1UF
FT_RXM1
DIFFERENTIAL_PAIR = DP16
R197
R
R201
0
DIFFERENTIAL_PAIR = DP9
R198
R
R202
0
DIFFERENTIAL_PAIR = DP9
FIBER TX
FIBER RX
C22
R68
R69
R70
R71
82
82
130
130
0.1UF
FT_RXP1
DIFFERENTIAL_PAIR = DP16
TOP VIEW
U6
FIBER TRANSCEIVER
R72
R73
R74
R75
DIFFERENTIAL_PAIR = DP3
49.9
49.9
NC
NC
DIFFERENTIAL_PAIR = DP3
HFBR-5803Z (+3.3V)
C23
Layout will support direct and
1x9 SIP Socket mounting for U6
0.1UF
C24
VCC_FT1
+3.3A
R195/196/197/198=NC,
R199/200/201/202=0 ohm
when port 1 is copper.
0.1UF
B
R76
0
Compatible Fiber Transceivers
Agilent HFBR-5803
(+3.3V)
Agilent HFBR-5205
(+5V)
Agilent HFBR-5103
(+5V)
DELTA OPT-155A1H1
(+5V)
LUMINENT B-13/15-155-T3-SSC3
LUMINENT B-13/15-155-T-SSC3
FXSD1
Sht.2
B
R195/196/197/198=0 ohm,
R199/200/201/202=NC
when port 1 is fiber.
R77
Nominal termination and DC biasing for
LVPECL and PECL Fiber Transceivers
(+3.3V)
130
VCC_FT
R64, R65
R68, R69
R66, R67
R70, R71
R76
+3.3V
82 Ohms
130 Ohms
130 Ohms
0 Ohm
130 Ohms
+5V
68 Ohms
191 Ohms
270 Ohms
4.75K 1%
5.62K 1%
(+5V)
R77
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8462HLL DEMO BOARD
Size
Document Number
Rev
1.1
Fiber Interface 1
Date:
5
4
3
2
Wednesday, November 16, 2011
Sheet
1
5
of
7
5
4
3
2
1
JP11
3X1
1
2
3
+3.3V_EXT
+5V
STEWARD HI1206N101R-00
Place components
in dotted box
close to fiber
transceiver
FB7
1
2
D
FBEAD
C26
VCC_FT2
0.1UF
D
FB6
1
FBEAD
C25
C32
+
0.1UF
C33
47UF / 16V
These components are DNI
regardless the Fiber
Transceiver is used or not
Refer to fiber
transceiver's
reference design
for the actual
values of these
resistors
2
0.1UF
VCC_FT2
+3.3A
C38
VCCRX2
VCCTX2
DIFFERENTIAL_PAIR = DP2
0.1UF
C31
R93
0.1UF
C
TX
N/C
RX
1x9/SC/SIP
N/C
TX_GND
TD+
TDVCCTX
VCCRX
SD
RDRD+
RX_GND
9
8
7
6
5
4
3
2
1
R80
82
R89
82
130
FT_TDP2
FT_TDM2
DIFFERENTIAL_PAIR = DP19
DIFFERENTIAL_PAIR = DP19
FT_SD2
FT_RDM2
FT_RDP2
DIFFERENTIAL_PAIR = DP15
DIFFERENTIAL_PAIR = DP15
R84
R90
49.9
49.9
DIFFERENTIAL_PAIR = DP2
R92
TXP2
Sht.2
TXM2
Sht.2
TXP_2
Sht.4
TXM_2
Sht.4
RXM_2
Sht.4
RXP_2
Sht.4
RXM2
Sht.2
RXP2
Sht.2
130
C
C36
0.1UF
FT_TXP2
DIFFERENTIAL_PAIR = DP21
R212
R
R211
0
DIFFERENTIAL_PAIR = DP11
C34
0.1UF
FT_TXM2
DIFFERENTIAL_PAIR = DP21
R206
R
R205
0
DIFFERENTIAL_PAIR = DP11
C30
0.1UF
FT_RXM2
DIFFERENTIAL_PAIR = DP17
R207
R
R208
0
DIFFERENTIAL_PAIR = DP13
R209
R
R210
0
DIFFERENTIAL_PAIR = DP13
FIBER TX
FIBER RX
C37
R79
R81
R82
0.1UF
FT_RXP2
DIFFERENTIAL_PAIR = DP17
R87
TOP VIEW
82
82
U10
130
130
FIBER TRANSCEIVER
R85
R78
R91
R83
DIFFERENTIAL_PAIR = DP4
49.9
49.9
NC
NC
DIFFERENTIAL_PAIR = DP4
HFBR-5803Z (+3.3V)
C35
Layout will support direct and
1x9 SIP Socket mounting for U6
0.1UF
C39
VCC_FT2
+3.3A
R209/207/206/212=NC,
R205/208/210/211=0 ohm
when port 2 is copper.
0.1UF
B
B
R86
0
Compatible Fiber Transceivers
Agilent HFBR-5803
(+3.3V)
Agilent HFBR-5205
(+5V)
Agilent HFBR-5103
(+5V)
DELTA OPT-155A1H1
(+5V)
LUMINENT B-13/15-155-T3-SSC3
LUMINENT B-13/15-155-T-SSC3
FXSD2
Sht.2
R205/208/210/211=NC,
R209/207/206/212=0 ohm,
when port 2 is fiber.
R88
Nominal termination and DC biasing for
LVPECL and PECL Fiber Transceivers
(+3.3V)
130
VCC_FT
R93, R80
R79, R81
R89, R92
R82, R87
R86
+3.3V
82 Ohms
130 Ohms
130 Ohms
0 Ohm
130 Ohms
+5V
68 Ohms
191 Ohms
270 Ohms
4.75K 1%
5.62K 1%
(+5V)
R88
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8462HLL DEMO BOARD
Size
Document Number
Rev
1.1
Fiber Interface 2
Date:
5
4
3
2
Wednesday, November 16, 2011
Sheet
1
6
of
7
5
4
3
2
1
+1.2A
STEWARD HI1206N101R-00
JP405
2X1
1
2
FBEAD
+1.2A Current
Probe
C93
U11 - KSZ8462HLL
Decouple VDD_CO1.2 Pin 16
+
C129
STEWARD HI1206N101R-00
FB19
FB20
JP403
2
FBEAD
OPEN
2.5V
CLOSED
1.8V
2
1
IN
EN
5
6
GND
GND
OUT
3
JP404
VDD_IO
1-2
1.8V / 2.5V
1
ADJ
GND
GND
4
8
7
JP406
C120
R194
10.7K
4
VREG_3.3V
ADJ
5
R179
GND
VOUT
+3.3A
U11 - KSZ8462HLL
Decouple +3.3A (VDD_A3.3) Pin 9
C130
+
C106
100UF / 16V
+
0.1UF
C131
C107
22UF / 20V
0.1UF
C
C137
+
0.1UF
22UF / 20V
2X1
R204
8.45K
VDD_IO
STEWARD HI1206N101R-00
1
2
3
VDD_IO
U11 - KSZ8462HLL
Decouple VDD_IO Pins 21, 30, 56
FB21
1
2
FBEAD
+
C133
C110
100UF / 16V
+
0.1UF
C134
C111
C112
C103
22UF / 20V
0.1UF
0.1UF
0.1UF
+
C132
C109
2.49K
100UF / 16V
3
VIN
+3.3A
VDD_IO
Current
Probe
U4
MIC29302BT
VIN
0.1UF
2
3X1
2
C101
0.1UF
C119
R203
10.5K
Install JP406 for 1.8V
470pF
3.3V
1
C102
FBEAD
JP404
+5V DC
C128
1.8_2.5V
MIC5209YM
2-3
U11 - KSZ8462HLL
Decouple VDD_1.2 Pins 40, 51
U21
1.8_2.5V
JP406
2X1
+3.3A
Current
Probe
VOUT = 1.242 X [ 1 + (R194/ (R203 || R204)) ]
D
22UF / 20V
+
0.1UF
STEWARD HI1206N101R-00
1
C
+1.2V
0.1UF
2X1
C100
22UF / 20V
C94
22UF / 20V
+1.2V Current
Probe
JP408
C124
+
0.1UF
D
VDD_CO1.2
U11 - KSZ8462HLL
Decouple VDD_A1.2 Pin 6
FB16
0.1UF
R180
+3.3V_EXT
STEWARD HI1206N101R-00
1.50K
+3.3V_EXT
FB23
1
2
R178
VOUT = 1.24 X [ 1 + ( R179 / R180 ) ]
FBEAD
+
C136
C118
100UF / 16V
5VDC
1
FB22
+5VDCIN
1
1
D13
POWER LED
+5V
STEWARD HI1206N101R-00
J11
B
220
0.1UF
2
B
2
2
3
FBEAD
+
C144
470UF / 16V
C114
TP21
100UF / 16V
TP22
GND
C135
+
0.1UF
TP24
GND
C115
0.1UF
TP23
GND
GND
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8462HLL DEMO BOARD
Size
Document Number
Rev
1.1
Power
Date:
5
4
3
2
Monday, November 21, 2011
Sheet
1
7
of
7