5
4
3
2
1
KSZ8463MLL/RLL_LQFP Demo Board Revision 1.3
REVISION HISTORY
Table of Contents
D
D
DATE:
DESCRIPTION
10/02/2010
REVISION
Initial release
1.0
3/21/2011
Add 4.7K pull-up on J5-2 (spi rdy) and 2.2K pull-down at TP6 (TXEN)
1.1
4/29/2011
Change R46-R50, R52, R54, R55 to 0 ohm
1.2
11/14/2011
2.5V/1.8V regulator schematic is corrected.
1.3
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
01:
02:
03:
04:
05:
06:
07:
08:
09:
Revision History
KSZ8463MLL/RLL_LQFP Device
USB Interface Bridge
Device Configuration and LEDs
Ethernet Interface
Fiber interface1
Fiber Interface2
MII / RMII Interface
Power
C
C
B
B
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8463MLL/RLL DEMO BOARD
Size
Document Number
Rev
1.3
Revision History
Date:
5
4
3
2
Monday, November 14, 2011
Sheet
1
1
of
9
5
4
3
Place R12 and R13 termination
resistors near U11 pin 44.
R12
294
R13
1
VDD_IO
VDD_IO
Note: R12 and R13 installed only when
external SPI interface is connected to J5
2
TP8
221
R15
4.7K
Sht.3
Sht.3
Place R235 termination
resistor near U11 pin 41.
SCL_MDC
SDA_MDIO
SCL_MDC
SDA_MDIO
D
R215
33
R235
33
INTRP
SPI_CSN
SPI_DO
R164
GPIO Header
COL
CRS
GPIO8
GPIO0
GPIO11
GPIO8
Sht.4
RXD0
RXD1
RXD2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
+1.2V
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GPIO2
GPIO3
GPIO4
GPIO5
GPIO Header
GPIO6
P1LED1
P1LED0
P2LED1
P2LED0
Sht.4
Sht.4
Sht.4
Sht.4
P1LED1
P1LED0
P2LED1
P2LED0
Sht.6
FXSD1
J12
1
3
RSTN
KSZ_FXSD1
2
4
GPIO1
DGND
VDD_1.2
GPIO2
GPIO3
GPIO4
GPIO5
KSZ8463MLL/RLL
VDD_IO
DGND
GPIO6
P1LED1/GPIO7_MLL
P1LED0
P2LED1/GPIO9_MLL
P2LED0/GPIO10_MLL
RSTN
FXSD1
RXD3/REFCLK_O
RX_DV
VDD_IO
DGND
TX_ER/MII_BP
TX_CLK/REFCLK_I
TXD0
TXD1
TXD2/NC
TXD3/EN_REFCLKO
TX_EN
VDD_IO
DGND
X2
X1
PWRDN
RXM1
RXP1
AGND
TXM1
TXP1
VDD_A1.2
ISET
AGND
VDD_A3.3
RXM2
RXP2
AGND
TXM2
TXP2
FXSD2
VDD_CO1.2
GPIO1
CON4A
+3.3A
VDD_IO
RXD3
RX_DV
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
R213
X2
X2
X1
PWRDN
X1
C1
18PF
2X1
+1.2A
R6
+1.2V
TX_ER
TX_CLK
TXD0
TXD1
TXD2
TXD3
TX_EN
0
JP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1-2 for Fiber,
3-4 for RJ45
SPI_CSN
SPI_DO
Sht.3
Sht.3,4
RX_CLK
Sht.8
COL
CRS
Sht.8
Sht.8
RXD[3:0]
Sht.4,8
D
R164, R213 clock termination resistors should
be placed close to KS8463 device pins. In
PHY MII mode these clocks are outputs from
VDD_IO the KS8463 and it is recommended to change
the resistor values to 33 ohms.
U11
GPIO0
GPIO11
GPIO8
SPI_DI/SDA_MDIO
SPI_SCLK/SCL_MDC
INTRN
SPI_CSN
SPI_DO
VDD_1.2
DGND
RX_CLK/GPIO7_RLL
COL/GPIO10_RLL
CRS/GPIO9_RLL
RXD0
RXD1
RXD2
VDD_IO
C
RX_CLK
0
Y1
25/50MHz
RX_DV
Sht.4,8
TX_ER
TX_CLK
Sht.8
Sht.8
TXD[3:0]
Sht.8
TX_EN
Sht.8
FXSD2
Sht.7
C
C2
18PF
Chip Power Down
(active low)
1K
1
3
Power_ON
Reset
+
B
2
4
1
3
2
4
+3.3A
TXM2
TXP2
2
S2
RXM2
RXP2
10K
RXM1
RXP1
D2
1N4148
TXM1
TXP1
1
J13
KSZ_FXSD2
Push Button
Reset
R5
CON4A
1-2 for Fiber,
3-4 for RJ45
TP9
R8
SW PUSHBUTTON
4.7K
C4
R4
6.49K
10UF
Do not populate
cap if pull down
is used
TP10
+3.3A
FX Detect
FX Mode
1
2
3
FXSD2
TX Mode
+
R9
C5
10UF
1K
B
JP77
3X1
R10
Do not populate
cap if pull down
is used
FXSD1
TX Mode
+
C6
R11
10UF
DIFFERENTIAL_PAIR = DP2
DIFFERENTIAL_PAIR = DP2
FX Detect
FX Mode
4.7K
1
2
3
DIFFERENTIAL_PAIR = DP4
DIFFERENTIAL_PAIR = DP4
JP78
DIFFERENTIAL_PAIR = DP1
DIFFERENTIAL_PAIR = DP1
3X1
1K
DIFFERENTIAL_PAIR = DP3
DIFFERENTIAL_PAIR = DP3
JP38
1
2
3
3X1
R232 33
33
R234
J15
COL
P2LED0
GPIO10
GPIO8
GPIO6
GPIO4
GPIO2
GPIO0
R229
R228
R227
R217
R216
33
33
33
33
33
11
9
7
5
3
1
J16
12
10
8
6
4
2
HEADER 6X2
12
10
8
6
4
2
R214
11
9
7
5
3
1
R224
R225
R226
33
33
33
33
GPIO11
GPIO9
GPIO7
GPIO5
GPIO3
GPIO1
CRS
R230
33
P2LED1
R231
33
RX_CLK
P1LED1
R233
33
HEADER 6X2
Note: place all series resistors near pin of KSZ8463
1
2
3
Sht.7
Sht.7
TXP1
TXM1
Sht.6
Sht.6
RXP1
RXM1
Sht.6
Sht.6
A
1
2
3
JP36
3X1
CONFIDENTIAL & PROPRIETARY
Title
KSZ8463MLL/RLL DEMO BOARD
Size
3
2
Document Number
Rev
1.3
KSZ8463 Device
GPIO7 SELECT
Date:
4
RXP2
RXM2
JP37
3X1
Note: place header to minimize
RX_CLK stub length.
5
Sht.7
Sht.7
GPIO9 SELECT
GPIO HEADERS
GPIO10 SELECT
A
TXP2
TXM2
Monday, November 14, 2011
Sheet
1
2
of
9
5
4
3
2
1
Bus Selection
Jumper Setting
SMI / MIIM (SW)
open JP32 and JP33.
close JP34 and JP35.
place Jumper between pin3 and pin4 of J5
D
These components are DNI
KSZ8463
I2C Master Mode
KSZ8463
SMI, SPI / I2C Slave Mode
JP3
CLOSE
OPEN
JP9
CLOSE
OPEN
I2C Master /
I2C Slave /
SPI Slave
open JP32 and JP33
MIIM (PHY only)
close JP32 and JP33
D
close JP34 and JP35.
open JP34 and JP35.
place Jumper between pin3 and pin4 of J5
VDD_IO
Serial EEPROM
U2
1
2
3
4
A0
A1
A2
GND
VCC
WP
SCL
SDA
8
7
6
5
R7
R1
10K
10K
JP9
SR_EEPRM_SCL
SR_EEPRM_SDA
SCL
SDA
JP32
2X1
MDC_PHY
JP33
2X1
MDIO_PHY
SCL
JP34
2X1
SCL_MDC
SDA
JP35
2X1
SDA_MDIO
MDC_PHY
JP3
Sht.8
MDIO_PHY
Sht.8
SCL_MDC
Sht.2
SDA_MDIO
Sht.2
AT24C02
USB5V
C
C
FB12
1
USB5V
2
FBEAD
C96
R165
470R
C97
C98
0.1uF
0.01uF
+3.3V_EXT
2-3 Close for default
VDD_IO
10uF
FT2232_VCCIO
C117
C116
C113
0.1uF
0.01uF
J14
1-2 USB 3.3V from LDO
1
2
3
2-3
USB 5.0V from
USB Port
SPI Signals
R169
4.7K
0.1uF
CN1
CN-USB
R175
4.7K
68001-206HLF
R222
4.7K
2
DIFFERENTIAL_PAIR = DP5
DIFFERENTIAL_PAIR = DP5
SPI_CSN
SPI_RDY
SPI_DO
SDA
SCL
R221 R219
4.7K 4.7K
R220
4.7K
R218
200K
R223
200K
R236
0
1
2
3
4
5
6
R189
1.5K
RSTOUT#
XTIN
3V3OUT
8
USBDM
7
USBDP
5
RSTOUT#
43
XTOUT
4
RESET#
+3.3V_EXT
48
EECS
1
EESK
R190
10k
2
EEDATA
TEST
45
AGND
47
15
13
12
11
SI/WUA
10
TXDB
RXDB
RTSB#
CTSB#
DTRB#
DRSB#
DCDB#
RIB#
40
39
38
37
36
35
33
32
TXDENB#
SLEEPB#
RXLEDB#
TXLEDB#
30
29
28
27
SI/WUB
26
PWREN#
41
U18
GND
GND
GND
GND
C105
47pF
44
9
18
25
34
C104
47pF
TXDENA
SLEEPA#
RXLED#
TXLED#
FT_SCK
FT_MOSI
FT_MISO
FT_CSN
8
EN
6
5
SCL2
SDA2
C145
2
GND
1
SCL1
SDA1
3
4
+3.3V_EXT
U20
7
VREF2
8
EN
6
5
SCL2
SDA2
C146
JP79
1
3
5
7
PCA9306DCU
0.1uF
R192
10K
To SoC Board
VREF1
2
GND
1
SCL1
SDA1
3
4
SCL
SDA
3
42
USB5V
XTOUT
24
23
22
21
20
19
17
16
XTIN
6MHz CRYSTAL
Y3
TXDA
RXDA
RTSA#
CTSA#
DTRA#
DSRA#
DCDA#
RIA#
VREF1
PCA9306_VDD
Note: place 27 ohm resistors
R182, R166 close to FT2232D
device pins.
6
VREF2
14
31
46
33nF
VCCIOA
VCCIOB
R166
27
VCC
VCC
C108
R182
27
7
SPI
Port
J5
U19
AVCC
1
USBM
USBP
6
5
R170
4.7K
FB13
1
2
3
4
B
R167
4.7K
VDD_IO
FT2232_VCCIO
USB5V
USB Port
R168
4.7K
2
4
6
8
SPI_DO
SPI_CSN
SPI_DO
SPI_CSN
Sht.2,4
Sht.2
HEADER 4X2
Install jumpers to connect
FT2232D to SPI Bus:
1 - 2
3 - 4
5 - 6
7 - 8
B
PCA9306DCU
0.1uF
+3.3V_EXT
R193
10K
R191
1K
FT2232D ( SPI PINOUT )
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8463MLL/RLL DEMO BOARD
Size
Document Number
Rev
1.3
USB Interface Bridge
Date:
5
4
3
2
Monday, November 14, 2011
Sheet
1
3
of
9
5
4
3
VDD_IO
D14
D
LEDX2
D15
LEDX2
1
SPEED
0
LED_VDD
R173
2
R60
220
P1LED1
R31
220
P1LED0
R188
220
P2LED1
R34
220
P2LED0
P1LED1
Sht.2
P1LED0
Sht.2
P2LED1
Sht.2
P2LED0
Sht.2
LINK / ACT
SPEED
D
LINK / ACT
Strapping / Configuration Options
Note: for 8462 only supports VDD_IO=3.3V or 2.5V
due to strap in requirements
VDD_IO
VDD_IO
VDD_IO
R128
4.7K
R130
4.7K
R132
4.7K
C
C
JP301
1
2
3
RX_DV
R127
1K
3X1
JP303
Sht.2,8
1
2
3
JP302
RXD2
3X1
Sht.2,8
JP306
R129
1K
1
2
3
3X1
GPIO8
VDD_IO
VDD_IO
VDD_IO
R124
4.7K
R126
4.7K
R122
4.7K
1
2
3
RXD1
Sht.2,8
R123
1K
3X1
JP304
1
2
3
3X1
RXD0
Sht.2,8
R125
1K
JP305
1
2
3
3X1
Sht.2
R131
1K
SPI_DO
Sht.2,3
R121
1K
B
B
JP301
PHY / MAC mode select
1 = PHY MII mode (default)
0 = MAC MII mode
JP302
Hi/Low Speed SPI mode select
1 = High Speed (default)
0 = Low Speed
{JP303,
JP304}
Serial Bus mode select
{0, 0} - I2C Master (EEPROM) mode
{0, 1} - I2C Slave mode
{1, 0} - SPI Slave mode (default)
{1, 1} - SMI / MIIM mode
A
JP305
XCLK Frequency
1 = 25MHz from X1/X2 (default)
0 = 50MHz from REFCLK_I
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8463MLL/RLL DEMO BOARD
Size
Document Number
Rev
1.3
Device Configuration and LEDs
Date:
5
4
3
2
Monday, November 14, 2011
Sheet
1
4
of
9
5
4
3
2
1
1000pf/2KV
Compatible Isolation Transformers
C87
Pulse H1102
Transpower HB726
1000pf/2KV
Bel Fuse S558-5999-U7
YCL PT163020
CHASSIS GND
DELTA LF8505
J1
D
D
RX1P
RX1M
TX1P
1
2
3
4
5
6
7
8
T1
R183
R184
51
51
R171
51
R172
75
CMT1
TX1M
R185
R186
51
51
R174
51
C66
TX1P
CMT1
TX1M
1000PF / 2KV
RX1P
RJ-45
RX1M
16
15
14
13
12
11
10
9
TX+
TCM
TXNC
NC
RX+
RCM
RX-
1
2
3
4
5
6
7
8
TD+
TC
TDNC
NC
RD+
RC
RD-
TXP_1
DIFFERENTIAL_PAIR = DP7
TXM_1
DIFFERENTIAL_PAIR = DP7
RXP_1
DIFFERENTIAL_PAIR = DP9
RXM_1
DIFFERENTIAL_PAIR = DP9
H1102
C67
Sht.6
TXM_1
Sht.6
RXP_1
Sht.6
RXM_1
Sht.6
C68
0.1uF
Line Side Protection (test option)
TXP_1
0.1uF
Chip Side Protection (test option)
Place near RJ-45 connector
D6
4
5
TXP_1
1
8
7
2
7
6
3
6
4
5
RXP_1
RX1M
3
C
RX1P
PLC03-3.3
PLC03-3.3
PROTEK
DEVICES
PROTEK
DEVICES
RX1P
1
TX1P
D7
2
TX1P
TXM_1
C
4
3
RX1M
D8
SR3.3
SR3.3
PROTEK
DEVICES
PROTEK
DEVICES
1
2
TX1M
3
8
2
1
4
D5
TX1M
RXM_1
Compatible Isolation Transformers
1000pf/2KV
C88
Pulse H1102
Transpower HB726
1000pf/2KV
Bel Fuse S558-5999-U7
YCL PT163020
J2
B
RX2P
RX2M
TX2P
1
2
3
4
5
6
7
8
DELTA LF8505
CHASSIS GND
B
T2
R18
R21
51
51
R19
51
R20
R23
R25
51
51
R24
51
C9
75
CMT2
TX2M
TX2P
CMT2
TX2M
1000PF / 2KV
RX2P
RJ-45
RX2M
16
15
14
13
12
11
10
9
TX+
TCM
TXNC
NC
RX+
RCM
RX-
1
2
3
4
5
6
7
8
TD+
TC
TDNC
NC
RD+
RC
RD-
TXP_2
DIFFERENTIAL_PAIR = DP11
TXM_2
DIFFERENTIAL_PAIR = DP11
RXP_2
DIFFERENTIAL_PAIR = DP13
RXM_2
DIFFERENTIAL_PAIR = DP13
H1102
C10
Sht.7
TXM_2
Sht.7
RXP_2
Sht.7
RXM_2
Sht.7
C11
0.1uF
Line Side Protection (test option)
TXP_2
0.1uF
Chip Side Protection (test option)
Place near RJ-45 connector
D10
TXP_2
7
2
7
6
3
6
RXP_2
RX2M
TX2P
4
5
TX2P
RX2P
4
RX2P
5
PLC03-3.3
PLC03-3.3
PROTEK
DEVICES
PROTEK
DEVICES
2
A
TXM_2
4
8
D11
D12
SR3.3
SR3.3
PROTEK
DEVICES
PROTEK
DEVICES
RXM_2
1
1
3
3
RX2M
2
2
TX2M
4
8
3
1
1
D9
TX2M
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8463MLL/RLL DEMO BOARD
Size
Document Number
Rev
1.3
Ethernet Interface
Date:
5
4
3
2
Monday, November 14, 2011
Sheet
1
5
of
9
5
4
3
2
1
JP10
3X1
1
2
3
+3.3V_EXT
+5V
STEWARD HI1206N101R-00
Place components
in dotted box
close to fiber
transceiver
FB4
D
1
2
FBEAD
C13
VCC_FT1
Route TX pairs on
component side
D
Route RX pairs on
solder side
FB5
0.1UF
1
Refer to fiber
transceiver's
reference design
for the actual
values of these
resistors
2
FBEAD
C15
C14
+
0.1UF
C16
47UF / 16V
0.1UF
These components are DNI
regardless the Fiber
interface is used or not.
VCC_FT1
Route TX & RX
differential pairs
close together,
8mil/8mil parallel
spacing, and keep
other signals 20 mil
(minimum) away
+3.3A
C17
VCCRX1
VCCTX1
DIFFERENTIAL_PAIR = DP1
0.1UF
C18
R64
R65
R66
N/C
TX
TX_GND
TD+
TDVCCTX
VCCRX
SD
RDRD+
RX_GND
RX
1x9/SC/SIP
N/C
9
8
7
6
5
4
3
2
1
82
82
130
FT_TDP1
FT_TDM1
DIFFERENTIAL_PAIR = DP18
DIFFERENTIAL_PAIR = DP18
FT_SD1
FT_RDM1
FT_RDP1
DIFFERENTIAL_PAIR = DP14
DIFFERENTIAL_PAIR = DP14
R63
49.9
49.9
DIFFERENTIAL_PAIR = DP1
C
0.1UF
R62
R67
TXP1
Sht.2
TXM1
Sht.2
TXP_1
Sht.5
TXM_1
Sht.5
RXM_1
Sht.5
RXP_1
Sht.5
RXM1
Sht.2
RXP1
Sht.2
C
130
C19
0.1UF
FT_TXP1
DIFFERENTIAL_PAIR = DP20
R195
R
R199
0
DIFFERENTIAL_PAIR = DP7
C20
0.1UF
FT_TXM1
DIFFERENTIAL_PAIR = DP20
R196
R
R200
0
DIFFERENTIAL_PAIR = DP7
C21
0.1UF
FT_RXM1
DIFFERENTIAL_PAIR = DP16
R197
R
R201
0
DIFFERENTIAL_PAIR = DP9
R198
R
R202
0
DIFFERENTIAL_PAIR = DP9
FIBER TX
FIBER RX
C22
R68
R69
R70
R71
82
82
130
130
0.1UF
FT_RXP1
DIFFERENTIAL_PAIR = DP16
TOP VIEW
U6
FIBER TRANSCEIVER
R72
R73
R74
R75
DIFFERENTIAL_PAIR = DP3
49.9
49.9
NC
NC
DIFFERENTIAL_PAIR = DP3
HFBR-5803Z (+3.3V)
C23
Layout will support direct and
1x9 SIP Socket mounting for U6
0.1UF
C24
VCC_FT1
+3.3A
R195/196/197/198=NC,
R199/200/201/202=0 ohm
when port 1 is copper.
0.1UF
B
R76
O
Compatible Fiber Transceivers
Agilent HFBR-5803
(+3.3V)
Agilent HFBR-5205
(+5V)
Agilent HFBR-5103
(+5V)
DELTA OPT-155A1H1
(+5V)
LUMINENT B-13/15-155-T3-SSC3
LUMINENT B-13/15-155-T-SSC3
FXSD1
Sht.2
B
R195/196/197/198=0 ohm,
R199/200/201/202=NC
when port 1 is fiber.
R77
Nominal termination and DC biasing for
LVPECL and PECL Fiber Transceivers
(+3.3V)
130
VCC_FT
R64, R65
R68, R69
R66, R67
R70, R71
R76
+3.3V
82 Ohms
130 Ohms
130 Ohms
O Ohm
130 Ohms
+5V
68 Ohms
191 Ohms
270 Ohms
4.75K 1%
5.62K 1%
(+5V)
R77
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8463MLL/RLL DEMO BOARD
Size
Document Number
Rev
1.3
Fiber Interface
Date:
5
4
3
2
Monday, November 14, 2011
Sheet
1
6
of
9
5
4
3
2
1
JP11
3X1
1
2
3
+3.3V_EXT
+5V
STEWARD HI1206N101R-00
Place components
in dotted box
close to fiber
transceiver
FB7
1
2
D
FBEAD
C26
VCC_FT2
0.1UF
D
FB6
1
Refer to fiber
transceiver's
reference design
for the actual
values of these
resistors
2
FBEAD
C25
C32
+
0.1UF
C33
47UF / 16V
0.1UF
These components are DNI
regardless the Fiber
interface is used or not.
VCC_FT2
+3.3A
C38
VCCRX2
VCCTX2
DIFFERENTIAL_PAIR = DP2
0.1UF
C31
R93
0.1UF
C
TX
N/C
RX
1x9/SC/SIP
N/C
TX_GND
TD+
TDVCCTX
VCCRX
SD
RDRD+
RX_GND
9
8
7
6
5
4
3
2
1
R80
82
R89
82
130
FT_TDP2
FT_TDM2
DIFFERENTIAL_PAIR = DP19
DIFFERENTIAL_PAIR = DP19
FT_SD2
FT_RDM2
FT_RDP2
DIFFERENTIAL_PAIR = DP15
DIFFERENTIAL_PAIR = DP15
R84
R90
49.9
49.9
DIFFERENTIAL_PAIR = DP2
R92
TXP2
Sht.2
TXM2
Sht.2
TXP_2
Sht.5
TXM_2
Sht.5
RXM_2
Sht.5
RXP_2
Sht.5
RXM2
Sht.2
RXP2
Sht.2
130
C
C36
0.1UF
FT_TXP2
DIFFERENTIAL_PAIR = DP21
R212
R
R211
0
DIFFERENTIAL_PAIR = DP11
C34
0.1UF
FT_TXM2
DIFFERENTIAL_PAIR = DP21
R206
R
R205
0
DIFFERENTIAL_PAIR = DP11
C30
0.1UF
FT_RXM2
DIFFERENTIAL_PAIR = DP17
R207
R
R208
0
DIFFERENTIAL_PAIR = DP13
R209
R
R210
0
DIFFERENTIAL_PAIR = DP13
FIBER TX
FIBER RX
C37
R79
R81
R82
0.1UF
FT_RXP2
DIFFERENTIAL_PAIR = DP17
R87
TOP VIEW
82
82
U10
130
130
FIBER TRANSCEIVER
R85
R78
R91
R83
DIFFERENTIAL_PAIR = DP4
49.9
49.9
NC
NC
DIFFERENTIAL_PAIR = DP4
HFBR-5803Z (+3.3V)
C35
Layout will support direct and
1x9 SIP Socket mounting for U6
0.1UF
C39
VCC_FT2
+3.3A
R209/207/206/212=NC,
R205/208/210/211=0 ohm
when port 2 is copper.
0.1UF
B
R86
O
Compatible Fiber Transceivers
Agilent HFBR-5803
(+3.3V)
Agilent HFBR-5205
(+5V)
Agilent HFBR-5103
(+5V)
DELTA OPT-155A1H1
(+5V)
LUMINENT B-13/15-155-T3-SSC3
LUMINENT B-13/15-155-T-SSC3
FXSD2
Sht.2
B
R205/208/210/211=NC,
R209/207/206/212=0 ohm,
when port 2 is fiber.
R88
Nominal termination and DC biasing for
LVPECL and PECL Fiber Transceivers
(+3.3V)
130
VCC_FT
R93, R80
R79, R81
R89, R92
R82, R87
R86
+3.3V
82 Ohms
130 Ohms
130 Ohms
O Ohm
130 Ohms
+5V
68 Ohms
191 Ohms
270 Ohms
4.75K 1%
5.62K 1%
(+5V)
R88
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8463MLL/RLL DEMO BOARD
Size
Document Number
Rev
1.3
Fiber Interface
Date:
5
4
3
2
Monday, November 14, 2011
Sheet
1
7
of
9
5
4
3
2
RMII option
The KSZ8463RLL can provide the 50MHz reference clock
by jumpering JP28 1-2 to enable REFCLKO. Remove R 51 and R53.
VDD_IO
R103
4.7K
1
2
3
R133
1K
JP27
TX_ER / MII_BP
(Pin 28)
3X1
Signal
Type
Signal
Pin #
REF_CLK
Input
TX_CLK
27
Input
CRS_DV
Output
TX_EN
22
Input
RXD[1]
Output
TXD1
25
Input
RXD[0]
Output
TXD0
26
Input
TX_EN
Input
RX_DV
31
Output
TXD[1]
Input
RXD1
34
Output
TXD[0]
Input
RXD0
35
Output
RX_ER
Output
TX_ER
28
Input
In MII PHY Mode
1
Disable MII PHY mode link, enable bypass mode
0
MII PHY mode normal operation
R104
4.7K
TXD3 / EN_REFCLKO
(PIN 23)
C
1
2
3
R112
1K
If 50MHz comes from Internal KSZ8463RLL.
NC R57
Layout will support
SMD and HALF CAN
packages for Y2
VDD_IO
Sht.2 TXD3
3X1
Enable REFCLKO Output
+
Disable REFCLKO Output
0
C70
10uF
RMII option
Y2
VDD_IO
RMII Mode Reference Clock
Selection - Port 3
1
JP28
Type
D
The KSZ8463RLL can use internal or external reference clock which is
selected by register CFGR bit 3. For external, it is set to 1, vice reverse.
Sht.2 TX_ER
(with respect to MAC)
(with respect to PHY)
For this board, the KS8463RLL provides RMII signals with respect to MAC side only.
The RMII signal connections between KS8463RLL and external PHY are shown in
the table to the right.
D
KSZ8463RLL RMII
External PHY RMII
KS8463RLL provides RMII signals with respect to both PHY and MAC sides.
1
50.000 MHz +/-50ppm
4
VCC
OUT
3
1
NC
GND
2
R57
R181
49.9 TX_CLK
R187
49.9 TXC_PHY3
0
Populated if RMII Mode used
C
C71
0.01uF
ECS-3953C-500-B
(SMD package)
(R58NC, For Test only)
R58
Sht.2 RXD3
0
(Note: alternate function is REFCLK_O)
TX_CLK
TXC_PHY3
+5V
STEWARD HI1206N101R-00
FB3
Do Not Install R51,
R53 in RMII mode
2
J4
Sht.3 MDIO_PHY
B
Sht.3
MDC_PHY
Sht.2
TXD[3:0]
Sht.2
Sht.2
Sht.2
TX_EN
TX_CLK
TX_ER
MDIO_PHY
MDC_PHY
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK
TX_ER
RX_CLK
RX_DV
RXD0
RXD1
RXD2
RXD3
COL
CRS
Sht.2
RX_CLK
Sht.2,4 RX_DV
Sht.2,4 RXD[3:0]
Sht.2
COL
Sht.2
CRS
COL
RX_DV
RX_CLK
RXD0
RXD1
RXD2
RXD3
R46
R47
R48
R49
R50
R51
R52
0
0
0
0
0
49.9
0
R53
49.9
R56
R54
R55
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TP1
VCC
MDIO
MDC
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_CLK
RX_ER
TX_ER
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
COL
CRS
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
1
FBEAD
AMP 787170-4
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
B
Female MII Connector
TP2
TP3
MAC Mode MII
TP4
TP11
(foward)
TP12
TP13
TP14
TXER
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
Sht.3 MDIO_PHY
Sht.3
MDIO_PHY
MDC_PHY
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_CLK
Sht.2,4 RXD[3:0]
Sht.2,4 RX_DV
Sht.2
RX_CLK
A
TX_ER
TX_CLK
TX_EN
Sht.2
TXD[3:0]
Sht.2
Sht.2
COL
CRS
TP6
TP7
TP16
TP17
TP18
J3
TP19
MDC_PHY
Sht.2
Sht.2
Sht.2
TP15
TP5
Note: Label Testpoints with signal
name on Silkscreen.
TX_ER
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
COL
CRS
R59
R37
R38
R39
R40
R41
R42
49.9
49.9
49.9
49.9
49.9
49.9
R43
49.9
R44
R45
49.9
49.9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VCC
MDIO
MDC
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_CLK
RX_ER
TX_ER
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
COL
CRS
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A
CONFIDENTIAL & PROPRIETARY
Male MII Connector
2.2K
Title
KSZ8463MLL/RLL DEMO BOARD
PHY Mode MII
Place R59 so as not to add any stub or length to TX_EN
Size
(reverse)
4
3
Rev
1.3
MII / RMII Interface
Date:
5
Document Number
2
Monday, November 14, 2011
Sheet
1
8
of
9
5
4
3
2
1
+1.2A
STEWARD HI1206N101R-00
+1.2A
U11 - KS8463
Decouple VDD_A1.2 Pin 6
FB16
1
2
FBEAD
C123
+
C93
C124
+
C94
DNI
100UF / 16V
D
0.1UF
22UF / 20V
0.1UF
D
JP405
+1.2A Current Probe
2X1
+1.2V
C127
+
U11 - KS8463
Decouple VDD_CO1.2 Pin 16
and VDD_1.2 Pins 40, 51
+1.2V
C100
C128
C102
C95
C101
22UF / 20V
0.1UF
0.1UF
0.1UF
+
DNI
100UF / 16V
STEWARD HI1206N101R-00
STEWARD HI1206N101R-00
FB19
FB20
1
JP403
2
FBEAD
OPEN
2.5V
CLOSED
1.8V
2
1
IN
EN
5
6
GND
GND
OUT
3
JP404
VDD_IO
1-2
1.8V / 2.5V
ADJ
GND
GND
4
8
7
2
JP406
C120
R194
10.7K
4
VREG_3.3V
ADJ
5
R179
GND
VOUT
C131
C107
22UF / 20V
0.1UF
C
C137
+
0.1UF
22UF / 20V
2X1
R204
8.45K
VDD_IO
STEWARD HI1206N101R-00
1
2
3
VDD_IO
U11 - KS8463
Decouple VDD_IO Pins 21, 30, 56
FB21
1
2
FBEAD
+
C133
C110
100UF / 16V
+
0.1UF
C134
C111
C112
C103
22UF / 20V
0.1UF
0.1UF
0.1UF
+
C132
C109
2.49K
100UF / 16V
3
VIN
+
0.1UF
VDD_IO
Current
Probe
U4
MIC29302BT
VIN
C106
100UF / 16V
3X1
2
C130
+
C119
R203
10.5K
Install JP406 for 1.8V
470pF
3.3V
1
U11 - KS8463
Decouple +3.3A (VDD_A3.3) Pin 9
FBEAD
JP404
+5V DC
+3.3A
1.8_2.5V
MIC5209YM
2-3
+3.3A
U21
1.8_2.5V
JP406
1
+3.3A
Current
Probe
VOUT = 1.242 X [ 1 + (R194/ (R203 || R204)) ]
C
2X1
0.1UF
0.1UF
R180
USB5V
+3.3V_EXT
STEWARD HI1206N101R-00
1.50K
+3.3V_EXT
FB23
1
JP400
FBEAD
1
2
3
2-3
+
5V from USB
C136
C118
100UF / 16V
1
D13
POWER LED
1
FB22
+5VDCIN
1
B
220
0.1UF
+5V
STEWARD HI1206N101R-00
J11
5VDC
2
R178
VOUT = 1.24 X [ 1 + ( R179 / R180 ) ]
2
1-2 5V from Jack
B
2
2
3
FBEAD
+
C144
470UF / 16V
C114
TP21
100UF / 16V
TP22
GND
C135
+
0.1UF
TP24
GND
C115
0.1UF
TP23
GND
GND
A
A
CONFIDENTIAL & PROPRIETARY
Title
KSZ8463MLL/RLL DEMO BOARD
Size
Document Number
Rev
1.3
Power
Date:
5
4
3
2
Monday, November 21, 2011
Sheet
1
9
of
9