Programmable True power on sensor Data Sheet Version 1.1 TLE4983C-HTN E6747 Features • TPO True Power On functionality • Increased BTPO range • Mono-cell chopped Hall system • TIM Twisted Independent Mounting • Dynamic self-calibrating algorithm • End-of-line programmable switching points • TC of back-bias magnet programmable • High sensitivity and high stability of the magnetic switching points PG-SSO-3-91 • High resistance to mechanical stress • Digital output signal (voltage interface) • Short-circuit protection • Module style package with two 4.7/47 nF integrated capacitors • Package: PG-SSO-3-91 with nickel plating Type Marking Ordering Code Package TLE4983C-HTN E6747 83ACS3 SP0003-74272 PG-SSO-3-91 General information: The TLE4983C is an active Hall sensor ideally suited for camshaft applications. Its basic function is to map either a tooth or a notch into a unique electrical output state. It has an electrical trimming option for post-fabrication trimming in order to achieve true power on capability even in the case of production spreads such as different magnetic configurations or misalignment. An additional self-calibration module has been implemented to achieve optimum accuracy during normal running operation. It comes in a three-pin package for the supply voltage and an open drain output. Page 1 of 29 Pin configuration PG-SSO-3-91 Pin definition and Function Pin No. 1 Symbol VS Function Supply Voltage 2 3 GND Q Ground Open Drain Output Functional description: The basic operation of the TLE4983C is to map a „high positive“ magnetic field (tooth) into a “low” electrical output signal and to map a „low positive“ magnetic field (notch) into a “high” electrical output. Optionally the other output polarity can be chosen by programming the PROM. A magnetic field is considered as positive if the North Pole of a magnet shows towards the rear side of the IC housing. Since it seems that also backbias-reduced magnetic configurations still show significant flux densities in one distinct direction the circuit will be optimised for one flux direction in order to provide an optimal signal to noise behaviour. For understanding the operation of the TLE4983C three different modes have to be considered: Initial operation after power up: This mode will be referred to as „initial mode“. Operation following the initialisation before having full information about the target wheel: This mode will be referred to as “precalibrated mode”. Normal operation with running target wheel: This mode will be referred to as „calibrated mode“. Page 2 of 29 Initial mode: The magnetic information is derived from a chopped Hall amplifier. The threshold information comes from a PROM-register that may be programmed at any time, but only once (no EEPROM). The magnetic information is compared against the threshold and the output state is set correspondingly. Some hysteresis is introduced in order to avoid false switching due to noise. In case that there is no PROM-value available (PROM has not been programmed before) the chip starts an auto-search for the actual magnetic value (SAR-mode). The initial threshold value is set to this magnetic value. This feature can be used to find a TPO-value for providing correct programming information to the chip simply by setting the chip in front of a well-defined static target. In this case a moving target wheel is not necessary. In case there is a PROM value available, the open drain output will be turned on or off by comparing the magnetic field against the pre-programmed value. During rotation of the target wheel a self-calibration procedure is started in the background. The IC memorises magnetic field values for adjusting the threshold to an optimum value. The exact way of threshold adjustment is described in more detail in the precalibrated mode. Precalibrated mode: In the precalibrated mode the IC permanently monitors the magnetic signal. To say it in more detail, it searches for minimum (caused by a notch) and maximum (caused by a tooth) values in the signal. Once the IC has found a pair of min / max values it calculates the optimum threshold level and adjusts the system offset in such a way, that the switching occurs on this level. The internal offset update algorithm checks also the magnetical edge in that point in time when an offset update is to be released. Positive updates of the offset are released only at magnetic rising edges, negative offset updates only on magnetic falling edges. Otherwise an update on the wrong magnetic edge may cause additional switching. The threshold adjustment is limited to increments of approx. 15mT per calibration in order to avoid totally wrong information caused by large signal disturbances (EMC-events or similar). The optimum threshold level may differ depending on the target wheel. For example, for regular gearwheels the magnetic signal is close to a sinusoid and the optimum threshold value can be considered as 50% value, which is the mean value between minimum and maximum signal. For camshaft wheels an optimum threshold may be at a different percent-value in order to have minimum phase error over airgap variations. See fig.4 for definition of this dynamic switching level. In case that the initial PROM-value does not lead to a switching of the IC because it is slightly out of the signal range the IC nevertheless does its switch value correction in the background. After having corrected for a sufficient amount the IC will start its output switching. The output switching includes some hysteresis in order to avoid false switching. During 16 switching events updates (number of updates depend on the magnetic signal) with 15mT are allowed. Page 3 of 29 Every valid1 minimum or maximum will be considered. After the next 16 switching events a single update of max. 15mT (in both directions) is allowed. For this single update the highest maximum and lowest minimum is taken into consideration. If the IC has not been programmed yet, it uses the default 50% value between the minimum and the maximum as switching level. 1 Valid means signal detection with DNC Page 4 of 29 Calibrated mode: After a certain number of switching events (32) the accuracy is considered to be quite high. At this time the chip is switched into an averaging mode (= calibrated mode) where only minor threshold corrections are allowed. In this mode a period of 32 switching events is taken to find the absolute minimum and maximum within this period. Threshold calculation is done with these minimum and maximum. A filter algorithm is implemented, which ensures that the threshold will only be updated, if the adjustment value calculated shows in the same direction over the last four consecutive periods. Every new calculated adjustment value that shows in the same direction causes an immediate update of the threshold value. If the direction of the calculated adjustment value changes, there must be again four consecutive adjustment values in the same direction for another update of the threshold value. Additionally there is an activation level implemented, allowing the threshold to be adjusted only if a certain amount (normally bigger than 1LSB) of adjustment is calculated. The threshold correction per cycle is limited to 1 LSB. The purpose of this strategy is to avoid larger offset deviations due to singular events. Also irregularities of the target wheel are cancelled out, since the minimum and maximum values are derived over at least one full revolution of the wheel. The output switching is done at the threshold level without visible hysteresis in order to achieve maximum accuracy. Nevertheless the chip has some internal protection mechanisms in order to avoid multiple switching due to noise. Changing the mode: Every time after power up the chip is reset into the initial mode. Subsequent modes (precalibrated, calibrated) are entered consequently as described before. In addition, two plausibility checks are implemented in order to enable some self-recovery strategy in case of unexpected events. First, there is a watchdog, which checks for switching of the sensor at a certain lower speed limit. If for 12 seconds there is no switching at the output, the chip is reset into the initial mode. Second, the IC checks if there is signal activity seen by the digital logic and if there is no outputswitching at the same time. If the digital circuitry expects that there should have been 4 switching events and actually no switching has occurred at the output, the IC is reset into the initial mode. Reset: There are several conditions, which can lead to a reset condition. For the IC behaviour we have to distinguish between a “output hold mode”, a “long reset”, a “short reset” and a “software reset”. Output hold mode: This operating mode means that the output is held in the actual state and there is no reset on the digital part performed. This state will be released after the IC reaches his normal operation condition again and goes back into the operating mode he was before. The following conditions lead to the output hold mode: • A drop in the supply voltage to a value less than 2.4V but higher than 2.0V for a time not longer than 1µs .. 2µs. Page 5 of 29 Long reset: This reset means a total reset of the analogue as well as for the digital part of the IC. The output is forced to its default state (“high”). This condition remains for less than 1ms. After this time the IC is assumed to run in a stable condition and enters the initial mode where the output represents the state of the target wheel (PROM value). The following conditions lead to a long reset: • Power-on condition. • Low supply voltage: drop of the supply voltage to values less than 2.4V for a time longer than 1µs .. 2µs or drop of the supply voltage to values less than 2.0V. Short reset: This reset means a reset of the digital circuitry. The output memorizes the state he had before the reset. This condition remains for approx. 1µs. After that time the chip is brought into the initial mode (output stays “high” for approx. 200µs for an untrimmed IC). Then the output is released again and represents the state of the target wheel (PROM value). The following conditions lead to a short reset: • Watchdog overflow: If there is no switching at the output for more than 12 seconds. • If there are four min- or max-events found without a switching event at the output Software reset: This reset can be performed in the testmode through the serial-interface. The IC output is then used as data output for the serial interface. The following condition lead to a software reset: • There is a reset applied through the serial Interface Table 1 shows an overview over the behaviour of the output under certain conditions. output hold mode long reset short reset initial mode precalibrated mode calibrated mode Unprogrammed Noninverted inverted Qn-1 High High high (self calibration) Normal Normal - Programmed Noninverted Inverted Qn-1 Qn-1 High High normal TPO inverted TPO normal TPO inverted TPO Normal Normal … state of output before a reset occurs Qn-1 normal TPO … “low” if B>BTPO ; “high” if B<BTPO inverted TPO … “high” if B>BTPO ; “low” if B<BTPO normal … “low” if B>BThreshold ; “high” if B<BThreshold inverted … “high” if B>BThreshold ; “low” if B<BThreshold Table1: Output behaviour under certain conditions Page 6 of 29 Inverted Inverted Hysteresis concept: There are two different hysteresis concepts implemented in the IC. The first one is called visible hysteresis, meaning that the output switching levels are changed between two distinct values (depending on the direction of the magnetic field during a switching event), whenever a certain amount of the magnetic field has been passing through after the last switching event. The visible hysteresis is used in the precalibrated mode of unprogrammed sensors. See fig.1 for more details. The second form of hysteresis is called hidden hysteresis. This means, that one cannot observe a hysteresis from outside. If the value of the switching level does not change, the output always switches at the same level. But inside the IC there are two distinct levels close above and below the switching level, which are used to arm the output. In other words if the value of the magnetic field crosses the lower of this hysteresis levels, then the output will be able to switch if the field crosses the switching level. After this switching event the output will be disabled until the value of the magnetic field crosses one of the two hysteresis levels. If it crosses the upper hysteresis level, then the output will be armed again and can switch if the magnetic field crosses the switching level. On the other hand, if the magnetic field does not reach the upper hysteresis level, but the lower hysteresis level will be crossed again after a switching event, then the output is allowed to switch, so that no tooth will be lost. But please notice that this causes an additional phase error. The hidden hysteresis is used for programmed sensors in precalibrated and calibrated mode. For more details see fig.2 Page 7 of 29 B Bon Bhys BTPO Boff B t Q t Fig. 1: Visible hysteresis valid for unprogrammed IC during precalibrated mode Page 8 of 29 B Bon B Bhys/2 Bcal Boff t Q t Fig. 2 Hidden hysteresis valid for programmed IC Page 9 of 29 Block diagram: The block diagram is shown in fig.3. The IC consists of a spinning Hall probe (monocell in the centre of the chip) with a chopped preamplifier. Next there is a summing node for threshold level adjustment. The threshold switching is actually done in the main comparator at a signal level of „0“. This means, that the whole signal is shifted by this summing node in that way, that the desired switching level occurs at zero. This adjusted signal is fed into an A/D-converter. The converter feeds a digital calibration logic. This logic monitors the digitised signal by looking for minimum and maximum values and also calculates correction values for threshold adjustment. The static switching level is simply done by fetching a digital value out of a PROM. The dynamic switching level is done by calculating a weighted average of min and max value. For example, a factor of approximately 71% can be achieved by doubling the weight of the max value. Generally speaking, a threshold level of Bcal = Bmin + (Bmax – Bmin) * k0 can be achieved by multiplying max with the switching level k0 and min with (1-k0). Serial interface: The serial interface is used to program the chip. At the same time it can be used to provide special settings and to read out several internal registers status bits. The interface description consists of a physical layer and a logical layer. The physical layer describes format, timing and voltage information, whereas the logical layer describes the available commands and the meaning of bits, words and addresses. Physical interface layer: The data transmission is done over the VS-pin, which generates input information and clock timing, and the out-pin Q, which delivers the output data. Generally the interface function is disabled; this means, that in normal operation including normal supply distortion the interface is not active and therefore the chip operates in its normal way. A special initialisation sequence must be performed to enter the interface mode that is also referred to as “testmode”. There are two possible ways to achieve the testmode. They are called OpenPowerOn and OpenSyncVDD. For already programmed devices this initialisation procedures to testmode are not possible. The IC is still in test mode after programming the IC. It is possible to read out the programmed values as long as you do not leave the test mode. OpenPowerOn: For a short time after power on or reset the chip monitors the output signal. The internal logic brings the output into a high impedance state, which will be a logical “high” caused by the external pull-up resistor. If now the chip sees a logical “low” (for at least 1ms), which is an output voltage lower than 0.3V, the chip enters the testmode. Data transmission: Serial transmission is done in words (LSB first). A logical „1“ is represented by a long (2/3 of one period) „high“ voltage level (higher than 5V) on the supply followed by a short (1/3 of one period) „low“ voltage level (lower than 5V), whereas a logical „0“ is represented by a short „high“ level on the supply followed by a long „low“ level. At the same time this high/low voltage combination, which forms in fact a bit, acts as a serial interface clock which clocks out logical high / low values on the output. Due to the increased capacity a clocking period of 200µs is recommended (standard value for 4.7nF capacitor: 100µs). Page 10 of 29 See fig.5 for a more detailed timing diagram. End of word is indicated by a long (we recommend longer than 200µs, first 30µs should be higher than 5V and the rest lower than 5V) „low” supply. Please note, that for communicating 13 bits of data 14 VS-pulses are necessary. If more than 14 input bits are transmitted the output bits are irrelevant (transmission buffer empty) whereas the input bits remain valid and start overwriting the previously transmitted bits. In any case the last 14 transmitted bits are interpreted as transmitted data word (13 bits) + 1 stop bit. End of communication is signalled by a long „high“ voltage level. A new communication has to be set up by a new initialisation sequence. Programming the PROM: One possibility for programming the static threshold value is to run the IC on a testbench (or in the car), to wait until the IC has reached the calibrated mode and then simply to issue the copy commands, which transfers the calibrated threshold value into the PROM. Use the following procedure for this type of programming: 1) Apply an oscillating magnetic field with a suitable offset (Notice that for unfused devices this offset lies in the middle of the maximum and minimum value of the magnetic field). 2) Enter the testmode with the second procedure described in the chapter “Physical interface layer”. 3) Wait until the IC has reached the calibration mode. 4) Choose a k-factor and supply a programming current to the output. For details see document: “How to program TLE498x”. 5) Write the two following bit-combinations via the serial interface: 101XXXXXk2k1k0I1 1011111111111 Here ki indicate the 3bits of the k-factor (k2 … MSB and k0 … LSB) in dual-code. This means: XXXX111 is equal to k0=0.7734 and XXXX011 is equal to k0=0.5234. The bit I is the so called Inverting bit, which determines either the output switches inverse to the applied magnetic field (I=”0”) or not (I=”1”). 6) Leave the testmode by writing a long “high” voltage level. Page 11 of 29 A second form of programming the static threshold value is to bring the IC in front of a target, which delivers a static magnetic field with a suitable strength and perform a power on by forcing the output to a low state for at least 1ms. This brings the chip in the testmode and he starts immediately a successive approximation and adjusts the value of the offset-DAC to the switching level that corresponds to the field strength. Use the following procedure for this type of programming: 1) Apply a static magnetic field with a suitable strength. 2) Enter the testmode with the first procedure described in the chapter “Physical interface layer”. 3) Wait until the IC has made the successive approximation and reached the right level for the offset-DAC (at least 10 periods of the internal clock frequency after releasing the output). 4) Choose a k-factor and supply a programming current to the output. For details see document: “How to program TLE498x”. 5) Write the two following bit-combinations via the serial interface: 101XXXXXk2k1k0I1 1011111111111 Here ki indicate the 3bits of the k-factor (k2 … MSB and k0 … LSB) in dual-code. This means: XXXX111 is equal to k0=0.7734 and XXXX011 is equal to k0=0.5234. The bit I is the so called Inverting bit, which determines either the output switches inverse to the applied magnetic field (I=”0”) or not (I=”1”). 6) Leave the testmode by writing a long “high” voltage level. It has to be noted that the chip has increased power dissipation during programming the PROM/fuses. The additional power is taken out of the output. Due to the PROM can not be tested during the sensor production please be aware that there is natural programming yield loss. Furthermore there may be an influence from the programming equipment. Please contact your local technical support for more details or see document: “How to program TLE498x”. Overvoltage protection: The process used for production has a breakthrough voltage of approximately 27.5V. The chip can be brought into breakthrough without damage if the breakthrough power (current) is limited to a certain value. Usually destruction is caused by overheating the device. Therefore for short pulses the breakthrough power can be higher than for long duration stress. For example for load dump conditions an external protection resistor of 200 Ω is recommended in 12V-systems and 50 Ω in 5V-systems. Page 12 of 29 OUT clamping & reverse voltage protection Vs overtemperature & short-circuit protection hyst comp clamping supply regulator digital supply analog supply Hall supply main comp enable n-channel open drain interface spinning Hall probe chopper + & filter - digital Tracking ADC min max algorithm offset DAC actual switching level bias for temperature & technology compensation oscillator GND Fig.3: Blockdiagram of TLE4983 Page 13 of 29 reset PROM K-factor inv. bit BTPO Fig. 4: Dynamic threshold value Fig. 5: Serial protocol Page 14 of 29 Absolute maximum ratings: Symbol Name VS VQ min typ max -18 18 supply voltage output OFF voltage Unit V -24 24 V 1h with RSeries>=200Ω2 -26 26 V 5min with RSeries>=200Ω1 -28 28 V 1min with RSeries ≥ 200Ω1 -0.3 18 V -18 24 V 1h with RLoad>=500Ω -18 26 V 5min with RLoad>=500Ω V 1h without RLoad 16 V current internal limited by short circuit protection (72h@TA<40°C) 18 V current internal limited by short circuit protection (1h@TA<40°C) 24 V current internal limited by short circuit protection (1min@TA<40°C) 50 mA -1.0 VQ output ON voltage IQ continuous output current -50 Tj junction temperature -40 RthJA thermal resistance junction-air TS storage temperature B magnetic field induction Note: Note -50 °C 155 °C 5000h (not additive) 165 °C 2500h (not additive) 175 °C 500h (not additive) 195 °C 10x1h (additive to the other life times) 190 K/W 150 °C mT no limit Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD Protection 2 Parameter Symbol max Unit Remarks ESD – protection VESD ±4 kV According to standard EIA/JESD22A114-B, Human Body Model (HBM). Accumulated life time Page 15 of 29 Operating range: Symbol VS Name min max Unit 3.3 18 24 V V 26 V 155 °C °C 5000h (not additive) 165 °C 2500h (not additive) 175 °C operating supply voltage -40 Continuous 1h with RSeries>=200Ω; extended limits for parameters in characteristics 5min with RSeries>=200Ω; extended limits for parameters in characteristics Tj operating junction temperature Tcal trimming temperature 15 35 °C 500h (not additive) reduced signal quality permittable (e.g. jitter) VS=5/12V IQ continuous output ON current continuous output OFF voltage 0 20 mA VQmax=0.5V -0.3 18 V Continuous -0.3 24 V 1h with RLoad>=500Ω 0 5 kHz VQ fB tedge B BTPO BAC_TPO BAC_cal Bover k0 3 Note magnetic signal switching frequency rise time of magnetic edge magnetic switching level range true power on range magnetic signal swing for TPO-function magnetic signal swing for calibrated mode magnetic overshoot adjustment range of switching level 85 µs -13 91 mT -13 91 mT 6 80 mTpp 3 80 mTpp 10 % of BACcal 77.34 % of BAC_cal 33.59 Encapsulated devices with BTPO=44mT and BHYS=0.5mT show minimum value of 5mTpp Page 16 of 29 Measured between two rising edges of the magnetic signal Magnetic signal edge is not allowed to rise faster (otherwise tracking ADC is not able to follow) Allowed programmable TPOvalues; Hysteresis not included (typ. BHys=1mT) BTPO=33mT BHYS = 0.75mT3 Switching point in calibrated mode is determined by: Bcal = Bmin + (Bmax – Bmin) * k0 k0 step size = 6.25% Symbol TCBTPO ∆TCBTPO Name Programmable temperature coefficient of BTPO Deviation to programmed temperature coefficient of BTPO min max Unit Note -1200 0 ppm/K Range to compensate TCmagnet , typical -825ppm/K -300 300 ppm/K -3.75 3.75 % Linear TC deviation -40°C to 150°C 1 At -40°C and 150°C See figure 6 1 ±450ppm/K @ -40°C guaranteed by design refered to second order TCBTPO compensation. Furthermore this compensation comprises the adjustment to second order effect of magnet Note: In the operating range the functions given in the functional description are fullfiled Figure 6: Deviation to programmed temperature coefficient of BTPO Page 17 of 29 AC/DC characteristics: Symbol Name min typ max Unit Note VQsat output saturation voltage 0.25 0.5 V IQ = 20mA IQleak output leakage current 0.1 10 µA VQ = 18V IQshort currentlimit for shortcircuit protection 30 50 80 mA Tprot junction temperature limit for output 195 protection output rise time 4 210 230 °C 11 17 µs VLoad = 4,5..24V RLoad = 1kΩ, CLoad = 4,7nF included in package 2.4 4 3.4 5.6 µs µs VLoad = 5V; VLoad = 12V; RLoad = 1kΩ, CLoad = 4,7nF included in package trise4 tfall5 output fall time ISVmin supply current @ 3.2V 6 7 mA VS = 3.2V; extended limits for parameters in characteristics ISV supply current @ 3.3V 6 7 mA VS = 3.3V; IS supply current 5.6 7.5 mA Ismax supply current @ 24V 8.0 mA VSclamp Clamping voltage VS-Pin 24 27.5 V 1mA through clamping device VQclamp Clamping voltage Q-Pin 24 27.5 V 1mA through clamping device VSreset Analog reset voltage ton 1.4 2.4 2.35 6 power on time 0.56 2.9 V 1 ms 8 0.75 td 9 delay time of output to magnetic edge 8 -3.6 nwatch temperature drift of delay time of output to magnetic edge watchdog edges twatch watchdog time ∆td 15 ms 22 µs 3.6 µs 4 - 12 s 4 RSeries>=200Ω Time to achieve specified accuracy. During this time the output is locked7 Higher magnetic slopes and overshoots reduce td, because the signal is filtered internal.10 not additional to td If nwatch min or max-events have been found and there was no change at the output a reset is performed. If there is no output change during twatch a reset is performed. value of capacitor: 4.7nF±10%;(excluded drift due to temperature and over lifetime); ceramic: X8R; maximum voltage: 50V value of capacitor: 4.7nF±10%;(excluded drift due to temperature and over lifetime); ceramic: X8R; maximum voltage: 50V 6 trimmed IC. 7 output is in high-state. 8 untrimmed IC. 9 measured at Tj = 25°C; represents the influence of the production spread (corresponds to the 3σ-value). 10 measured with a sinusoidal-field magnetic-field with 10mTpp and a frequency of 1kHz. 5 Page 18 of 29 Symbol Name min fclk fchopper ∆k0 BOffset clock frequency for digital part typ max 1.76 kHz mT Typ. value corresponds 1σ 130 162.5 mT Typ. BODAC_0 = -16.3mT Typ. BODAC_1023 = 113.8mT Tj=25°C full scale range of the offset-DAC FSRODACtyp full scale range of the offset-DAC 112.7 130 152.8 mT BTPO_res resolution of programmable threshold in TPO mode drift of BTPO-point 0.13 mT ∆BAC_cal accuracy of threshold in calibration mode Bneff effective noise value of the magnetic switching points output jitter is not affected by the chopper frequency % FSRODAC ∆BTPO Note MHz clock frequency used by the chopper 220 preamplifier resolution of switching level 6.25 adjustment internal offset -2.2 ±0.35 2.2 104 Unit -2 +3.4 mT BTPO=33mT11 -2 2 % percentage of BAC; BAC=10mTpp sinusoidal signal12; systematic deviation due to hysteresis in the filter algorithm of 1.5% at BAC=10mTpp not included; Tj = 25°C; The magnetic noise is normal distributed, nearly independent to frequency and without sampling noise or digital noise effects. The typical value represents the rms-value here and corresponds therefore to 1σ probability of normal distribution. Consequently a 3σ value corresponds to 0.3% probability of appearance. The typical value corresponds to the rms-value at Tj = 175°C. The max value corresponds to the rms-values in the full temperature range and includes technological spreads. 33 55 µT 120 µT Note: The listed AC/DC and magnetic characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not other specified, typical characteristics apply at Tj = 25 °C and VS = 12 V. 11 This value shows the deviation from the programmed BTPO value and its temperature coefficient. Included are the package-effect, the deviation from the adjusted temperature coefficient of the BTPO point (resolution of the temperature coefficient and spread of the technologie) and the drift of the offset (over temperature and lifetime). Not included is the hysteresis in the initial mode. Included are the package-effect, the deviation from the adjusted temperature coefficient of the BTPO point (resolution of the temperature coefficient and spread of the technologie) and the drift of the offset (over temperature and lifetime). Not included is the hysteresis in the initial mode. 12 bigger amplitudes of signal lead to smaller values of ∆BAC_cal. Page 19 of 29 Application circuit 1 3 2 for example: RL=1,2kΩ RS=120Ω 1 3 2 for example: RP≥200Ω @ Vs=12V RP≥50Ω @ Vs=5V RL=1,2kΩ Figure 7 Application Circuits TLE4983C Page 20 of 29 Electro Magnetic Compatibility - (values depend on RSeries) Additional Information: Characterisation of Electro Magnetic Compatibility are carried out on sample base of one qualification lot. Not all specification parameters have been monitored during EMC exposure. Only key parameters e.g. switching current and duty cycle have been monitored. Ref. ISO 7637-1; see test circuit of figure 8; ∆BPP = 10mT (ideal sinusoidal signal); VS=13.5V ± 0.5V, fB= 1000Hz; T= 25°C; RSeries ≥ 200Ω; Parameter Symbol Level/typ Status Testpulse 1 VEMC IV / -100V C Testpulse 2 IV / 100V A13 Testpulse 3a IV / -150V A Testpulse 3b IV / 100V A Testpulse 4 IV / -7V A Ref. ISO 7637-2; 2nd edition 06/2004 see test circuit of figure 8; ∆BPP = 2mT (amplitude sinus signal); VS=13.5V ± 0.5V, fB= 1000Hz; T= 25°C; RSeries ≥ 200Ω; Parameter Symbol Level/typ Status Testpulse 2a VEMC IV / 40V A Testpulse 5a IV / 86.5V C Testpulse 5b IV / 86.5V A14 Note: Test criteria for status A: No missing pulse no additional pulse on the IC output signal plus duty cycle and jitter are in the specification limits. Test criteria for status B: No missing pulse no additional pulse on the IC output signal. (Output signal “OFF” means switching to the voltage of the pull-up resistor). Test criteria for status C: One or more parameter can be out of specification during the exposure but returns automatically to normal operation after exposure is removed. Test criteria for status E: destroyed. 13 14 Valid during Vs is applied afterwards Status C, current consumption may be out of spec during testpulse Suppressed Us*=35V Page 21 of 29 Ref. ISO 7637-3; TP 1 and TP 2 ref. DIN 40839-3; see test circuit of figure 8; ∆BPP = 10mT (ideal sinusoidal signal); VS=13.5V ± 0.5V, fB= 1000Hz; T= 25°C; RSeries ≥ 200Ω; Parameter Symbol Level/typ Status Testpulse 1 VEMC IV / -30V A Testpulse 2 IV / 30V A Testpulse 3a IV / -60V A Testpulse 3b IV / 40V A Ref. ISO 11452-3; see test circuit of figure 8; measured in TEM-cell; ∆BPP = 4mT (ideal sinusoidal signal); VS=13.5V ± 0,5V, fB= 200Hz; T= 25°C; RSeries ≥ 200Ω; Parameter Symbol Level/max EMC field strength ETEM-Cell IV / 200V/m Remarks AM=80%, f=1kHz; Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Test condition for the trigger window: fB-field=200Hz, Bpp=4mT, vertical limits are ±200mV and horizontal limits are ±200µs. 5V RSeries 200Ω VEMC CInt-package RLoad 47 nF VS GND 1kΩ Q CInt-package Figure 8: Testcircuit for EMC-tests Page 22 of 29 4.7 nF CLoad 50pF Package Dimensions PG-SSO 3-91 (Plastic Green Single Small Outline) Page 23 of 29 Position of the Hall Element Page 24 of 29 Appendix: Calculation of mechanical errors: Magnetic Signal Output Signal ϕ ∆ϕ ∆ϕ Figure 9: Systematic Error ϕ and Stochastic Error ∆ϕ Systematic Phase Error ϕ The systematic error comes in because of the delay-time between the threshold point and the time when the output is switching. It can be calculated as follows: ϕ= 360° • n • td 60 ϕ ... systematic phase error in ° n ... speed of the camshaft-wheel in min-1 td ... delay time (see specification) in sec Page 25 of 29 Stochastic Phase Error ∆ϕ The stochastic phase error includes the error due to the variation of the delay time with temperature and the error caused by the resolution of the threshold. It can be calculated in the following way: ∆ϕd ∆ϕcal n ∂ϕ ... ... ... ... ∂B ∆td ... ∆BAC_cal ... ∆ϕd = 360° • n • ∆td 60 ∆ϕcal = ∂ϕ • ∆BAC _ cal ∂B stochastic phase error due to the variation of the delay time over temperature in ° stochastic phase error due to the resolution of the threshold value in ° speed of the camshaft wheel in min-1 inverse of the magnetic slope of the edge in °/T variation of delay time over temperature in sec accuracy of the threshold in T Jitter (Repeatability) The phase jitter is normally caused by the analogue system noise. If there is an update of 1bit of the offset-DAC due to the algorithm, what could happen after a period of 16 teeth, then an additional step in the phase occurs (see description of the algorithm). This is not included in the following calculations. The noise is transformed through the slope of the magnetic edge into a phase error. The phase jitter is determined by the two formulas: B ∂B ∂ϕ Bn_max Bneff_typ 1σ 3σ Noise ϕ Jitter _ typ = ϕ Phase-Jitter ∂ϕ • (Bneff _ typ ) ∂B ϕ Jitter _ max = Figure 10: Phase-Jitter Page 26 of 29 ∂ϕ • (Bn _ max ) ∂B ϕJitter_typ ϕJitter_max ∂ϕ ∂B Bneff_typ Bn_max ... ... ... typical phase jitter at Tj=25°C in ° (1Sigma) maximum phase jitter at Tj=175°C in ° (3Sigma) inverse of the magnetic slope of the edge in °/T ... ... typical value of Bneff in T maximum value of Bn in T (1σ-value at Tj=25°C) (3σ-value at Tj=175°C) Example: Assumption: n = 3000 min-1 td = 14 µs ∆td = ±3 µs ∂B = 1 mT/° ∂ϕ ∆BAC_cal = ±0.2 mT (=2% of 10mT swing) Bneff_typ = ±33 µT (1σ-value at T=25°C) Bn_max = ±360 µT (3σ-value at T=170°C) Calculation: ϕ = 0.252° ∆ϕd = ±0.054° ∆ϕcal = ±0.2° ϕJitter_typ = ±0.033° ϕJitter_max = ±0.21° ... ... ... ... ... systematic phase error stochastic phase error due to delay time variation stochastic phase error due to accuracy of the threshold typical phase jitter (1σ-value at Tj=25°C) maximum phase jitter (3σ-value at Tj=175°C) Page 27 of 29 Appendix A: Marking & data matrix code information: Product is RoHS (restriction of hadzardous substances) compliant when marked with letter “G” in front or after the date code marking. As mentioned in information note N° 136/03 a data matrix code with 8x18 fields according to the ECC200 standard may be used for TLE4983C. Furthermore the marking technique on the front side of the device may be changed from a mask to a writing laser equipment. The information content (date code and device type) will hereby not be changed. Please refer to you Key account team or regional sales responsible if you need further information Example for data matrix code (rear side of sensor): Comparison between mask writing vs. new laser writing (TLE 4941): Mask Lasering Writing Lasering Page 28 of 29 Revision History: Version 1.1 Previous Version: 1.1 23 25 Change: new package outline figure Old package outline figure erased Infineon Technologies AG © Infineon Technologies AI SC All Rights Reserved. http://www.infineon.com/products/sensors We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? 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