PRELIMINARY Differential Hall Sensor TLE4925/TLE4925C Features • Advanced performance by dynamic self calibration principle • High sensitivity • Single chip solution • Symmetrical thresholds • High resistance to Piezo effects • South and north pole pre-induction possible • low cut-off frequency • Digital output signal • Two-wire and three-wire configuration possible • Wide operating temperature range • Fast start-up time • Large operating air-gaps • Reverse voltage protection at Vs- PIN • Short- circuit and over temperature protection of output • No external filter capacitor required (TLE4925C) • Digital output signal (voltage interface) • Module style package with two 4.7nF integrated capacitors (TLE4925C) Page 1 of 25 PRELIMINARY P-SSO-3-6 1 2 3 P-SSO-3-9 1 2 3 Figure 1: Pin configuration in P-SSO-3-6 and P-SSO-3-9 Pin No. 1 2 3 Symbol VS GND Q Function Supply Voltage Ground Open Drain Output General Information The TLE4925/TLE4925C is an active Hall sensor suited to detects the motion and position of ferromagnetic and permanent magnet structures. An additional selfcalibration module has been implemented to achieve optimum accuracy during normal running operation. It comes in a three-pin package for the supply voltage and an open drain output. Functional Description The differential Hall sensor IC detects the motion and position of ferromagnetic and permanent magnet structures by measuring the differential flux density of the magnetic field. To detect ferromagnetic objects the magnetic field must be provided by a back biasing permanent magnet (south or north pole of the magnet attached to the rear unmarked side of the IC package). Page 2 of 25 PRELIMINARY Offset cancellation is achieved by advanced digital signal processing. Immediately after power-on motion is detected (start-up mode). After a few transitions the sensor has finished self-calibration and switches to a high-accuracy mode (running mode). In running mode switching occurs at signal zero-crossing of the arithmetic mean of max and min value of magnetic differential signal. ∆B is defined as difference between hall plate 1 and hall plate 2. Q clamping & reverse voltage protection VS overtemperature & short-circuit protection hyst comp power supply regulator analog supply main comp digital supply clamping n-channel open drain enable interface Hall probes ++ + amplifier -- Tracking ADC filter digital min max algorithm Offset DAC actual switching level bias for temperature & technology compensation oscillator GND reset Figure 2: Block Diagram of TLE4925/TLE4925C Circuit Description The TLE4925/TLE4925C is comprised of a supply voltage regulator, a pair of hall probes, spaced at 2.5mm, differential amplifier, noise-shaping filter, comparator, advanced digital signal processor (DSP), A/D and D/A converter and an open drain output. Startup mode: The differential signal is digitized in the A/D converter and fed into the dsp part of the circuit. There a rising or falling transition is detected and the output stage is triggered accordingly. As the signal is not offset compensated at this time, the output does not neccessarily switch at zero-crossing of the magnetic signal. Signal peaks are also detected in the digital circuit and their arithmetic mean value can be calculated. The offset of this mean value is determined and fed into the offset cancellation DAC. This procedure can be repeated with increasing accuracy. After few increments the IC is switched into the high accuracy running mode. Page 3 of 25 PRELIMINARY Running mode: In running mode the output is triggered by the comparator. An offset cancellation feedback loop is formed by the A/D converter, dsp and offset cancellation D/A converter. In running mode switching always occurs at zero-crossing. It is only affected by the (small) remaining offset of the comparator and by the remaining propagation delay time of the signal path, mainly determined by the noise-shaping filter. Nevertheless signals below a defined threshold are not detected to avoid unwanted parasitic switching. peak detection offset= (max + min) / 2 offset correction offset running-mode startup-mode Figure 3: Startup of the device At transition from startup-mode to running mode switching timing is moving from low-accuracy to high accuracy zero-crossing. Page 4 of 25 PRELIMINARY 1.1 Absolute Maximum Ratings No. Parameter Symbol min 1.1.1 Supply voltage VS Typ max Unit Remarks -18 18 V - -24 24 V 1h with RSeries ≥ 200Ω1 -26 26 V 5min with RSeries ≥ 200Ω1 -28 28 V 1min with RSeries ≥ 200Ω1 1.1.2 Supply current IS -10 25 mA - 1.1.3 Output OFF voltage VQ -0.3 18 V - -0.3 24 V 1h with RLoad ≥ 500Ω -0.3 26 V 5min with RLoad ≥ 500Ω -1.0 - V 1h (protected by internal series resistor) 1.1.4 Output ON voltage VQ - 16 V Current internal limited by short circuit protection (72h @ TA < 40°C). - 18 V Current internal limited by short circuit protection (1h @ TA < 40°C). - 24 V Current internal limited by short circuit protection (1min @ TA < 40°C). 1.1.5 Continuous output IQ -50 Tj -40 50 mA - °C - 155 °C 2000h (not additive) 165 °C 1000h (not additive) 175 °C 168 h (not additive) 195 °C 3 x1 h (additive to the current 1.1.6 Junction temperature other life times). 1.1.7 Storage temperature TS 1.1.8 Thermal resistance Rth JA -40 junction-air for 150 °C 190 K/W Lower values are possible with overmoulded devices. P-SSO-3-6 P-SSO-3-9 Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Accumulated life time. Page 5 of 25 PRELIMINARY 1.2 Electro Magnetic Compatibility - (values depend on R Series!) Ref. ISO 7637-1; see test circuit of figure 4 and 5; ∆BPP = 10mT (ideal sinusoidal signal); VS=13.5V ± 0.5V, fB= 1000Hz; T= 25°C; RSeries ≥ 200Ω; No. Parameter Symbol Level/typ Status 1.2.1 Testpulse 1 VEMC IV / -100V C2 Testpulse 2 IV / 100V C2 Testpulse 3a IV / -150V A Testpulse 3b IV / 100V A Testpulse 4 IV / -7V A Testpulse 5 IV / 86.5V C Note: Test criteria for status A: No missing pulse no additional pulse on the IC output signal plus duty cycle and jitter are in the specification limits. Test criteria for status B: No missing pulse no additional pulse on the IC output signal. (Output signal “OFF” means switching to the voltage of the pull-up resistor). Test criteria for status C: One or more parameter can be out of specification during the exposure but returns automatically to normal operation after exposure is removed. Test criteria for status E: IC destroyed. Ref. ISO 7637-3; TP 1 and TP 2 ref. DIN 40839-3; see test circuit of figure 4 and 5; ∆BPP = 10mT (ideal sinusoidal signal); VS=13.5V ± 0.5V, fB= 1000Hz; T= 25°C; RSeries ≥ 200Ω; No. Parameter Symbol Level/typ Status 1.2.2 Testpulse 1 VEMC IV / -30V A Testpulse 2 IV / 30V A Testpulse 3a IV / -60V A Testpulse 3b IV / 40V A Ref. ISO 11452-3; see test circuit of figure 4 and 5; measured in TEM-cell; ∆BPP = 4mT (ideal sinusoidal signal); VS=13.5V ± 0,5V, fB= 200Hz; T= 25°C; RSeries ≥ 200Ω; No. Parameter Symbol Level/max 1.2.3 EMC field strength ETEM-Cell IV / 200V/m Remarks AM=80%, f=1kHz; Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Test condition for the trigger window: fB-field=200Hz, Bpp=4mT, vertical limits are ±200mV and horizontal limits are ±200µs. 2 According to 7637-1 the supply switched „OFF“ for t=200ms. For battery „ON“ is valid status „A“. Page 6 of 25 PRELIMINARY 1.3 ESD Protection No. Parameter 1.3.1 ESD – protection P-SSO-3-9 Symbol max Unit Remarks According to standard VESD P-SSO-3-6 ±8 kV EIA/JESD22-A114-B ±6 kV Human Body Model (HBM). 5V RSeries 200Ω RLoad CInt-package VEMC 4.7 nF VS 1.2 kΩ Q 4.7 nF CLoad GND 50 pF CInt-package Figure 4: Test Circuit for EMC tests (TLE4925C) – P-SSO-3-9 Package 5V RSeries 200Ω RLoad 4.7nF VEMC CExt1 VS GND 1.2kΩ Q CLoad 50pF CExt2 Figure 5: Test Circuit for EMC tests (TLE4925) – P-SSO-3-6 Package Page 7 of 25 4.7nF PRELIMINARY 2.1 Operating Range No. Parameter Symbol min 2.1.1 Supply voltage VS 3.3 typ max Unit Remarks 18 V Continuous 24 V 1h with RSeries ≥ 200Ω 26 V 5min with RSeries ≥ 200Ω. Extended limits for parameters in characteristics. 3 2.1.2 Supply voltage ripple VSAC 2.1.3 Continuous output OFF VQ voltage 2.1.4 Continuous output ON IQ V During test pulse 4. 6 Vpp VS=13V; 0 < f < 50kHz -0.3 18 V Continuous -18 24 V 1h with RLoad ≥ 500Ω 0 20 mA VQmax=0.6V 1 ms Time to achieve specified accuracy current 2.1.5 Power on time ton After power on the output of the IC is always in high-state. After internal resets output is locked3. 2.1.6 Operating junction temperature Tj -40 °C - 155 °C 2000 h (not additive) 165 °C 1000 h (not additive) 175 °C 168 h (not additive) reduced signal quality permittable (e.g. jitter) Note: Unless otherwise noted, all temperatures refer to junction temperature. For the supply voltage lower than 28V (RSeries ≥ 200Ω) and junction temperature lower than 195°C the magnetic and AC/DC characteristics can exceed the specification limits. 3 Output of the IC is locked in present state (high-state or low-state) after an internal reset is launched. This reset happens typically every 780ms when there is no significant signal change. See also 2.2.14. A voltage reset causes a release of the output and output is in high state after power on again. Page 8 of 25 PRELIMINARY 2.2 AC/DC Characteristics Over operating range, unless otherwise specified. Typical values correspond to VS=12V and TA=25°C No. Parameter Symbol min typ max Unit Remarks 2.2.1 Supply current IS 3 6.8 9 mA - 2.2.2 Supply current @ 3.3V ISVmin 3 6.7 8 mA VS=3.3V 2.2.3 Supply current @ 24V ISmax 3 7 9.5 mA VS=24V RSeries ≥ 200Ω 2.2.4 Output saturation VQsat 0.25 0.6 V IQ= 20mA 0.1 10 µA VQ= 18V voltage 2.2.5 Output leakage current IQleak 2.2.6 Current limit for short- IQshort 30 60 80 mA - Tprot 195 210 230 °C - 4 12 20 µs VLoad = 4.5 to 24V Circuit protection 2.2.7 Junction temperature limit for output protection 2.2.8 Output rise time tr4 TLE4925C (P-SSO-3-9) RLoad = 1.2kΩ; CLoad = 4.7nF included in package. TLE4925 (P-SSO-3-6) 4 12 20 µs VLoad = 4.5 to 24V RLoad = 1.2kΩ; CLoad = 4.7nF external capacitor. 2.2.9 Output fall time TLE4925C (P-SSO-3-9) tf5 0.5 0.9 1.3 µs VLoad = 5V 0.65 1.15 1.65 µs VLoad = 12V RLoad = 1.2kΩ; CLoad = 4.7nF included in package. TLE4925 (P-SSO-3-6) 0.5 0.9 1.3 µs VLoad = 5V 0.65 1.15 1.65 µs VLoad = 12V RLoad = 1.2kΩ; CLoad = 4.7nF external capacitor. 4 value of capacitor: 4.7nF±10%; (excluded drift due to temperature); ceramic: X7R; maximum voltage: 100V. Page 9 of 25 PRELIMINARY 2.2.10 delay time td 7 12.5 18 µs Only valid for Tj=25°C. 6 µs Valid for Tj=-40°C till 20 Tj=175°C. Higher magnetic slopes and overshoots reduce td, because the signal is filtered internal. 2.2.11 Temperature drift of ∆td 37 -6 6 µs Time over specified delay time of output to temperature range; magnetic edge not additional to td 8 kHz Operation below 1Hz 8 1.34 1.68 MHz - 625 780 970 ms VSclamp 24 27.5 V IS = 20mA < 5min. 24 27.5 V IQ = 20mA < 5min. V - 2.2.12 Frequency range f 0.001 2.2.13 Oscillator frequency fOSC 1.08 2.2.14 Offset recalibration time after last output change treset 2.2.15 Clamping voltage Output locked to state before recalibration VS-Pin 2.2.16 Clamping voltage Q- Pin VQclamp 2.2.17 Analog reset voltage VsReset Note: 2.35 2.9 The listed AC/DC and magnetic characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not other specified, typical characteristics apply at Tj = 25 °C and VS = 12 V. 2.3 Magnetic Characteristics in Running Mode No. Parameter Symbol min 2.3.1 Bias preinduction B0 2.3.2 Differential bias induction 2.3.3 Minimum signal typ max Unit Remarks -500 500 mT - ∆B0 -30 30 mT - ∆Bmin 0.55 1.5 mT 9 100 mT Additional to B0 10 0.2 mT F= 2N amplitude 2.3.4 Maximum signal ∆Bmax amplitude 2.3.5 Resistivity against ∆Bmin -0.2 mechanical stress (piezo) 5 see footnote 6. only valid for the falling edge. 7 related to Tj= 175°C. 8 output will switch if magnetic signal is changing more that 2x∆Bmin within offset recalibration time even below 1Hz once per magnetic edge 9 includes also former Bm of TLE4941-2. 10 exceeding this limit might result in decreased duty cycle performance. With higher values the internal measured signal will be clipped. This will decrease the phase accuracy. Page 10 of 25 6 PRELIMINARY Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at Tj=25°C and the given supply voltage. 3.1 Self-calibration Characteristics No. Parameter Symbol 3.1.1 No. of transitions for min typ max Unit Remarks nStart 2 - - nCalib 7 - Low accuracy of signal output at startup (startup mode) 3.1.2 No. of transitions for entering running mode switching timing permitted 3.1.3 Duty cycle in running Dty 457 507 557 % 11 mode ∆BPP = 10mT ideal sinusoidal input signal (Tj=25°C) 407 507 607 % ∆BPP = 10mT ideal sinusoidal input signal (-40°C ≤ Tj < 175°C) 3.1.4 Signal jitter in running σ1 ≤ ±0.11 12 % mode; 1 sigma value7 ∆BPP = 10mT ideal sinusoidal input signal; Tj<150°C σ2 ≤ ±0.168 % ∆BPP = 10mT ideal sinusoidal input signal; 150°C ≤ Tj < 175°C 3.1.5 Signal Jitter in running σ3 ≤ ±0.11 % ∆BPP = 10mT ideal mode at power supply of sinusoidal input Vs=13V and ripple ±3V; signal; Tj<150°C 1 sigma value* 11 12 this corresponds to a ∆B0 = 0mT (magnetic offset). typical half value of TLE4941-2 performance (depends largely on∆Bminand also on f). Page 11 of 25 PRELIMINARY 3.1.6 Effective noise value of Bneff 25 µT Tj = 25°C; The the magnetic switching magnetic noise is points normal distributed, nearly independent to frequency and without sampling noise or digital noise effects. The effective value corresponds to 1σ probability of normal distribution. Consequently a 3σ value corresponds to 0.3% probability of appearance. 70 µT Typical value corresponds to 1σ. Max value corresponds to 1σ values in the full temperature range and include technological spreads. 3.1.7 ≤ ±55 Phase error in startup mode ° ∆BPP = 10mT ideal sinusoidal input signal;13 3.1.8 Frequency distribution of Jitter shall be distributed signal jitter like white noise 13 - smaller phase errors are possible at higher signal amplitudes, because sinus signal changes to a more rectangle signal. Page 12 of 25 PRELIMINARY B Bmax ∆B ∆BPP 50% Bmin ∆ BPP = 2 x ∆B ∆B=B1-B2 (signal amplitude) t UQ tr tf VQ-High 90% td VQ-Low 50% 10% t1 T t Figure 6 Switching direction Signal T ∆T t σ 1...σ 3 = 1 1 ⋅ ⋅ ∑ (∆T ) 2 T ( n − 1) measurement condition: n ≥ 1000 Figure 7 Definition of signal jitter Page 13 of 25 PRELIMINARY Application Configurations Two possible applications are shown in Figure 8 and Figure 9 (Toothed and Magnet Wheel). The difference between two-wire and three-wire application is shown in Figure 12 for the TLE4925C and in Figure 13 for the TLE4925. Gear Tooth Sensing In the case of ferromagnetic toothed wheel application the IC has to be biased by the south or north pole of a permanent magnet (e.g. SmCO5 (Vacuumschmelze VX145)) with the dimensions 8 mm × 5 mm × 3 mm) which should cover both Hall probes. The maximum air gap depends on - the magnetic field strength (magnet used; pre-induction) and - the toothed wheel that is used (dimensions, material, etc.; resulting differential field). a centered distance of Hall probes b Hall probes to IC surface L IC surface to tooth wheel a = 2.5 mm b = 0.3 mm Figure 8 S N Sensor Spacing Conversion DIN – ASA m = 25.4 mm/p T = 25.4 mm CP DIN d z m T diameter (mm) number of teeth module m = d/z (mm) pitch T = π × m (mm) Figure 9 ASA p diameter pitch p = z/d (inch) PD pitch diameter PD = z/p (inch) CP circular pitch CP = 1 inch × π/p Toothed Wheel Dimensions Page 14 of 25 PRELIMINARY Hall Sensor 1 N (S) S (N) Figure 10 TLE4925/TLE 4925C, with Ferromagnetic Toothed Wheel Page 15 of 25 PRELIMINARY Figure 11 TLE4925/TLE 4925C, with Magnet Wheel 1 3 2 for example: RL=1,2kΩ RS =120Ω 1 3 2 for example: RP ≥200Ω RL=1,2kΩ Figure 12 Application Circuits TLE4925C Page 16 of 25 PRELIMINARY 1 3 2 for example: RL=1,2kΩ RS =120Ω 1 3 2 for example: RP ≥200Ω RL=1,2kΩ Figure 13 Application Circuits TLE4925 Page 17 of 25 PRELIMINARY S (N) N (S) Pin 3 (Q) Pin 1 (Vs) B2 B1 Branded Side Crankshaft Wheel Profile Magnetic Field Difference ∆B=B1-B2 Large airgap Small airgap ∆BENOP=1mT Hidden Hysteresis ∆BHYS=2mT ∆BENRP=-1mT Output Signal VQ Enabling point for releasing output: B1-B2>∆BENRP switches the output OFF (V Q=HIGH) Enabling point for operate point: B1-B2<∆BENOP switches the output ON (V Q=LOW) ∆BHYS=|∆BENOP-∆BENRP| Outside of a permanent magnet the magnetic induction (=flux density) points from north to the south pole. It is common to define positive flux if the south pole of a magnet is on the branded side of the IC. This is equivalent to the north pole of the magnet on the rear side of the IC. Figure 14 System Operation with hidden hysteresis Page 18 of 25 PRELIMINARY P-SSO-3-9 (Plastic Single Small Outline) Figure 15 Package Dimensions (P-SSO-3-9) Page 19 of 25 PRELIMINARY Figure 16 Hall probe spacing in the P-SSO-3-9 package Figure 17 Tape Loading Orientation in the P-SSO-3-9 package Page 20 of 25 PRELIMINARY Figure 18 Tape Loading Orientation in the P-SSO-3-6 package Page 21 of 25 PRELIMINARY Figure 19 Hall probe spacing in the P-SSO-3-6 package Page 22 of 25 PRELIMINARY Appendix: Calculation of mechanical errors: Magnetic Signal Output Signal ϕ ∆ϕ ∆ϕ Figure 20: Systematic Errorϕ and Stochastic Error ∆ϕ Systematic Phase Error ϕ The systematic error comes in because of the delay-time between the threshold point and the time when the output is switching. It can be calculated as follows: ϕ= ϕ n td 360° • n • td 60 ... systematic phase error in ° ... speed of the camshaft-wheel in min-1 ... delay time (see specification) in sec Page 23 of 25 PRELIMINARY Stochastic Phase Error ∆ϕ The stochastic phase error includes the error due to the variation of the delay time with temperature and the error caused by the resolution of the threshold. It can be calculated in the following way: ∆ϕ d = ∆ϕd n ∆td 360° • n • ∆td 60 ... stochastic phase error due to the variation of the delay time over temperature in ° … speed of the camshaft wheel in min-1 … variation of delay time over temperature in sec Jitter (Repeatability) B The phase jitter is normally caused by the analogue system noise. If there is an update of the offset-DAC due to the algorithm, what could happen after each tooth, then an additional step in the phase occurs (see description of the algorithm). This is not included in the following calculations. The noise is transformed through the slope of the magnetic edge into a phase error. The phase jitter is determined by the two formulas: ∂B ∂ϕ Bdiff_max Bdiff_typ 1σ 3σ Noise ϕ Phase-Jitter Figure17: Phase-Jitter ϕ Jitter _ typ = ∂ϕ • (Bneff _ typ ) ∂B ϕ Jitter _ max = ∂ϕ • (Bneff _ max ) ∂B Page 24 of 25 PRELIMINARY ϕJitter_typ ϕJitter_max ... ∂ϕ ∂B Bneff_typ Bneff_max ... typical phase jitter at Tj=25°C in ° (1Sigma) maximum phase jitter at Tj=175°C in ° (3Sigma) ... inverse of the magnetic slope of the edge in °/T ... ... typical value of Bdiff in T (1σ-value at Tj=25°C) maximum value of Bdiff in T (3σ-value at Tj=175°C) Example: Assumption: n = 4500 min-1 td = 14 µs ∆td = ±3 µs ∂B = 3 mT/° ∂ϕ Bneff_typ = ±40 µT (1σ-value at Tj=25°C) Bneff_max = ±210 µT (3σ-value at Tj=175°C) Calculation: ϕ = 0.378° ∆ϕd = ±0.081° ϕJitter_typ = ±0.013° ϕJitter_max = ±0.07° ... ... ... ... systematic phase error stochastic phase error due to delay time variation typical phase jitter (1σ-value at Tj=25°C) maximum phase jitter (3σ-value at Tj=175°C) Page 25 of 25