MCP25625
CAN Controller with Integrated Transceiver
General Features:
CAN Transceiver Features:
• Stand-Alone CAN2.0B Controller with Integrated
CAN Transceiver and Serial Peripheral
Interface (SPI)
• Up to 1 Mb/s Operation
• Very Low Standby Current (10 µA, typical).
• Up to 10 MHz SPI Clock Speed
• Interfaces Directly with Microcontrollers with 2.7V
to 5.5V I/O
• Available in SSOP-28L and 6x6 QFN-28L
• Temperature Ranges:
- Extended (E): -40°C to +125°C
• VDDA: 4.5V to 5.5V
• Implements ISO-11898-2 and ISO-11898-5
Standard Physical Layer Requirements
• CAN Bus Pins are Disconnected when Device is
Unpowered
- An Unpowered Node or Brown-Out Event will
not load the CAN bus
• Detection of Ground Fault:
- Permanent dominant detection on TXD
- Permanent dominant detection on bus
• Power-on Reset and Voltage Brown-Out
Protection on VDDA Pin
• Protection Against Damage Due to Short-Circuit
Conditions (Positive or Negative Battery Voltage)
• Protection Against High-Voltage Transients in
Automotive Environments
• Automatic Thermal Shutdown Protection
• Suitable for 12V and 24V Systems
• Meets or Exceeds Stringent Automotive Design
Requirements Including “Hardware Requirements for LIN, CAN and FlexRay Interfaces in
Automotive Applications”, Version 1.3, May 2012
• High-Noise Immunity Due to Differential Bus
Implementation
• High ESD Protection on CANH and CANL, meets
IEC61000-4-2 up to ±8 kV
CAN Controller Features:
• VDD: 2.7 to 5.5V
• Implements CAN 2.0B (ISO11898-1)
• Three Transmit Buffers with Prioritization and
Abort Feature
• Two Receive Buffers
• Six Filters and Two Masks, with Optional Filtering
on the First Two Data Bytes
• Supports SPI Modes 0,0 and 1,1
• Specific SPI Commands to Reduce SPI Overhead
• Buffer Full, and Request-to-Send Pins
Configurable as General Purpose I/O
• One Interrupt Output Pin
Description:
The MCP25625 is a complete, cost-effective and
small-footprint CAN solution that can be easily added
to a microcontroller with an available SPI interface.
The
MCP25625
interfaces
directly
with
microcontrollers operating at 2.7V to 5.5V, there are no
external level shifters required. In addition, the
MCP25625 connects directly to the physical CAN bus,
supporting all requirements for CAN high-speed
transceivers.
The MCP25625 meets the automotive requirements for
high-speed (up to 1 Mb/s), low quiescent current,
electromagnetic compatibility (EMC) and electrostatic
discharge (ESD).
2014 Microchip Technology Inc.
DS20005282A-page 1
MCP25625
Package Types
19 VDD
RX1BF 11
RX0BF 12
INT 13
SCK 14
18 RESET
17 CS
16 SO
15 SI
22 GND
23 RX1BF
24 RX0BF
VDDA
TXCAN
4
18
VSS
RXCAN
5
17
NC
CLKOUT
6
16
TXD
TX0RTS
7
15
STBY
EXP-29
14
20 TXCAN
19
NC
9
10
3
13
21 RXCAN
VDD
CANH
22 CLKOUT
8
OSC2
12
7
20
CANL
23 TX0RTS
25 INT
24 TXD
6
2
11
5
RESET
OSC1
VIO
25 NC
26 SCK
4
21
10
26 VSS
1
RXD
3
CS
9
27 VDDA
TX2RTS
28 RXD
2
8
1
TX1RTS
VIO
NC
CANL
CANH
STBY
TX1RTS
TX2RTS
OSC2
OSC1
GND
27 SI
MCP25625
SSOP
28 SO
MCP25625
6x6 QFN*
* Includes Exposed Thermal Pad (EP); see Table 1-1.
DS20005282A-page 2
2014 Microchip Technology Inc.
MCP25625
1.0
DEVICE OVERVIEW
1.1
A typical CAN solution consists of a CAN controller that
implements the CAN protocol, and a CAN transceiver
that serves as the interface to the physical CAN bus.
The MCP25625 integrates both the CAN controller and
the CAN transceiver. Therefore, it is a complete CAN
solution that can be easily added to a microcontroller
with an SPI interface.
FIGURE 1-1:
Block Diagram
Figure 1-1 shows the block diagram of the MCP25625.
The CAN transceiver is illustrated in the top half of the
block diagram, see Section 6.0 “CAN Transceiver”
for more details.
The CAN controller is depicted at the bottom half of the
block diagram, and described in more detail in
Section 3.0 “CAN Controller”.
MCP25625 BLOCK DIAGRAM
VIO
VDDA
Digital I/O
Supply
Thermal
Protection
POR
UVLO
VIO
TXD
Permanent
Dominant Detect
CANH
Driver
and
Slope Control
VIO
STBY
CANL
Mode
Control
VSS
Wake-up
Filter
RXD
CANH
LP_RX
CANL
Receiver
CANH
HS_RX
CANL
CS
TX Handler
TX
Prioritization
SCK
SI
SO
RXCAN
CAN
Protocol
Engine
SPI IF
RX Handler
Acceptance
Filters and
Masks
VDD
INT
RX0BF
TXCAN
Control Logic
Registers: Configuration, Control and Interrupts
GND
RX1BF
OSC1
Tx0RTS
Tx1RTS
Crystal
Oscillator
OSC2
CLKOUT
Tx2RTS
RESET
2014 Microchip Technology Inc.
DS20005282A-page 3
MCP25625
1.2
Pin Out Description
The descriptions of the pins are listed in Table 1-1.
TABLE 1-1:
MCP25625 PIN DESCRIPTION
Pin Name
6x6
QFN
SSOP
Block
(Note 1)
Pin Type
VIO
11
1
CAN Transceiver
P
Digital I/O supply pin for CAN Transceiver
NC
14
2
—
—
No Connection
CANL
12
3
CAN Transceiver
HV I/O
CAN Low-Level Voltage I/O
CANH
13
4
CAN Transceiver
HV I/O
CAN High-Level Voltage I/O
STBY
15
5
CAN Transceiver
I
Standby Mode Input
TX1RTS
8
6
CAN Controller
I
TXB1 Request To Send
TX2RTS
9
7
CAN Controller
I
TXB2 Request To Send
OSC2
20
8
CAN Controller
O
External Oscillator Output
OSC1
21
9
CAN Controller
I
External Oscillator Input
GND
22
10
CAN Controller
P
Ground
RX1BF
23
11
CAN Controller
O
RXB1 Interrupt
RX0BF
24
12
CAN Controller
O
RXB0 Interrupt
INT
25
13
CAN Controller
O
Interrupt Output
SCK
26
14
CAN Controller
I
SPI Clock Input
SI
27
15
CAN Controller
I
SPI Data Input
SO
28
16
CAN Controller
O
SPI Data Output
CS
1
17
CAN Controller
I
SPI Chip Select Input
RESET
2
18
CAN Controller
I
Reset Input
VDD
3
19
CAN Controller
P
Power for CAN Controller
TXCAN
4
20
CAN Controller
O
Transmit Output to CAN Transceiver
RXCAN
5
21
CAN Controller
I
Receive Input from CAN Transceiver
CLKOUT
6
22
CAN Controller
O
Clock Output/SOF
TX0RTS
7
23
CAN Controller
I
TXB0 Request To Send
TXD
16
24
CAN Transceiver
I
Transmit Data Input from CAN Controller
NC
17
25
—
—
No Connection
VSS
18
26
CAN Transceiver
P
Ground
VDDA
19
27
CAN Transceiver
P
Power for CAN Transceiver
RXD
10
28
CAN Transceiver
O
Receive Data Output to CAN Controller
EP
29
—
—
—
Exposed Thermal Pad
Description
Legend: P = Power, I = Input, O = Output, HV = High Voltage.
Note 1: See Section 3.0 “CAN Controller” and Section 6.0 “CAN Transceiver” for further information.
DS20005282A-page 4
2014 Microchip Technology Inc.
MCP25625
1.3
Typical Application
Figure 1-2 shows an example of a typical application
of the MCP25625. In this example the microcontroller
operates at 3.3V.
VDDA supplies the CAN transceiver and must be
connected to 5V.
VDD, VIO of the MCP25625 are connected to VDD of
the microcontroller. The digital supply can range from
2.7V to 5.5V. Therefore, the I/O of the MCP25625 is
connected directly to the microcontroller, no level
shifters are required.
The TXD and RXD pins of the CAN transceiver must be
externally connected to the TXCAN and RXCAN pins
of the CAN controller.
The SPI interface is used to configure and control the
CAN controller.
The INT pin of the MCP25625 signals an interrupt to
the microcontroller. Interrupts need to be cleared by
the microcontroller through SPI.
The usage of RXXBF and TXXRTS is optional, since
the functions of these pins can be accessed through
SPI. The RESET pin can optionally be pulled-up to
VDD of the MCP25625 using a 10 k resistor.
The CLKOUT
microcontroller.
FIGURE 1-2:
VBAT
pin
provides
the
clock
to
the
MCP25625 INTERFACING WITH A 3.3V MICROCONTROLLER
5V LDO
3.3V LDO
0.1 µF
0.1 µF
0.1 µF
0.1 µF
VDD VIO VDDA
TXD
CANH
VDD
RXD
CANH
120:
RXCAN
CANL
CANL
RA0
STBY
RA1
CS
SCK
SCK
SDO
SI
SDI
SO
MCP25625
PIC® Microcontroller
TXCAN
Optional
INT0
INT
INT1
RX0BF
INT2
RX1BF
RA2
TX0RTS
RA3
TX0RTS
RA4
TX0RTS OSC2
RA5
RESET
22 pF
22 pF
OSC1
VSS
2014 Microchip Technology Inc.
CLKOUT OSC1
GND
VSS
DS20005282A-page 5
MCP25625
NOTES:
DS20005282A-page 6
2014 Microchip Technology Inc.
MCP25625
2.0
MODES OF OPERATION
2.1
CAN Controller Modes of
Operation
The CAN controller has five modes of operation:
•
•
•
•
•
Configuration mode
Normal mode
Sleep mode
Listen-Only mode
Loopback mode
The operational
REQOP bits in
Register 4-34).
mode is selected via the
the CANCTRL register (see
When changing modes, the mode will not actually
change until all pending message transmissions are
complete. The requested mode must be verified by
reading the OPMOD bits in the CANSTAT register (see
Register 4-35).
2.2
CAN Transceiver Modes of
Operation
The CAN transceiver has two modes of operation:
• Normal mode
• Standby mode
Normal mode is selected by applying a low-level to the
STBY pin. The driver block is operational and can drive
the bus pins. The slopes of the output signals on CANH
and CANL are optimized to produce minimal
electromagnetic emissions (EME). The high-speed
differential receiver is active.
Standby mode is selected by applying a high-level to
the STBY pin. In Standby mode, the transmitter and the
high-speed part of the receiver are switched off to
minimize power consumption. The low-power receiver
and the wake-up filter are enabled in order to monitor
the bus for activity. The receive pin (RXD) will show a
delayed representation of the CAN bus, due to the
wake-up filter.
2.3
2.4
Normal Mode
Normal mode is the standard operating mode of the
MCP25625. In this mode, the device actively monitors
all bus messages and generates Acknowledge bits,
error frames, etc. This is also the only mode in which
the MCP25625 transmits messages over the CAN bus.
Both the CAN Controller and the CAN transceiver must
be in Normal mode.
2.5
Sleep/Standby Mode
The CAN controller has an internal Sleep mode that is
used to minimize the current consumption of the
device. The SPI interface remains active for reading
even when the MCP25625 is in Sleep mode, allowing
access to all registers.
Sleep mode is selected via the REQOP bits in the
CANCTRL register. The OPMOD bits in the CANSTAT
register indicate the operation mode. These bits should
be read after sending the Sleep command to the
MCP25625. The MCP25625 is active and has not yet
entered Sleep mode until these bits indicate that Sleep
mode has been entered.
When in Sleep mode, the MCP25625 stops its internal
oscillator. The MCP25625 will wake-up when bus
activity occurs or when the microcontroller sets, via the
SPI interface, the WAKIF bit in the CANINTF register to
“generate” a wake-up attempt (the WAKIE bit in the
CANINTE register must also be set in order for the
wake-up interrupt to occur).
The CAN transceiver must be in Standby mode, in
order to take advantage of the low standby current of
the transceiver. After a wake-up the microcontroller
must put the transceiver back into Normal mode using
the STBY pin.
Configuration Mode
The MCP25625 must be initialized before activation.
This is only possible if the device is in the Configuration
mode. Configuration mode is automatically selected
after power-up, a Reset, or can be entered from any
other mode by setting the REQOP bits in the
CANCTRL register. When Configuration mode is
entered, all error counters are cleared. Configuration
mode is the only mode where the following registers
are modifiable:
• CNF1, CNF2, CNF3
• TXRTSCTRL
• Acceptance filter registers
2014 Microchip Technology Inc.
DS20005282A-page 7
MCP25625
2.5.1
WAKE-UP FUNCTIONS
The CAN transceiver will monitor the CAN bus for activity. The wake-up filter inside the transceiver is enabled
to avoid a wake-up due to noise. In case there is activity
on the CAN bus, the RXD pin will go low. The CAN bus
wake-up function requires both CAN transceiver supply
voltages to be in valid range: VDDA and VIO.
The CAN controller will detect a falling edge on the
RXCAN pin, and interrupt the microcontroller if the
wake-up interrupt is enabled.
Since the internal oscillator is shut down while in Sleep
mode, it will take some amount of time for the oscillator
to start-up and the device to enable itself to receive
messages. This Oscillator Start-up Timer (OST) is
defined as 128 TOSC.
The device will ignore the message that caused the
wake-up from Sleep mode, as well as any messages
that occur while the device is “waking up”. The device
will wake-up in Listen-Only mode.
2.7
Loopback Mode
Loopback mode will allow internal transmission of
messages from the transmit buffers to the receive
buffers without actually transmitting messages on the
CAN bus. This mode can be used in system
development and testing.
In this mode, the ACK bit is ignored and the device will
allow incoming messages from itself just as if they were
coming from another node. The Loopback mode is a
silent mode, meaning no messages will be transmitted
while in this state (including error flags or Acknowledge
signals). The TXCAN pin will be in a recessive state.
The filters and masks can be used to allow only
particular messages to be loaded into the receive
registers. The masks can be set to all zeros to provide
a mode that accepts all messages. The Loopback
mode is activated by setting the REQOP bits in the
CANCTRL register.
The microcontroller must set both, the CAN controller
and CAN transceiver, to Normal mode before the
MCP25625 will be able to communicate on the bus.
2.6
Listen-Only Mode
Listen-Only mode provides a means for the MCP25625
to receive all messages (including messages with
errors) by configuring the RXM<1:0> bits in the
RXBnCTRL register. This mode can be used for bus
monitor applications or for detecting the baud rate in
“hot plugging” situations.
For auto-baud detection, it is necessary that at least
two other nodes are communicating with each other.
The baud rate can be detected empirically by testing
different values until valid messages are received.
Listen-Only mode is a silent mode, meaning no
messages will be transmitted while in this mode
(including error flags or Acknowledge signals). In
Listen-Only mode, both valid and invalid messages will
be received regardless of filters and masks or RXM bits
in the RXBxCTRL register mode bits. The error counters are reset and deactivated in this state. The ListenOnly mode is activated by setting the REQOP bits in
the CANCTRL register.
DS20005282A-page 8
2014 Microchip Technology Inc.
MCP25625
3.0
CAN CONTROLLER
3.2
The CAN controller implements the CAN protocol
version 2.0B. It is compatible with the ISO 11898-1
standard.
Figure 3-1 illustrates the block diagram of the CAN
controller. The CAN controller consists of the following
major blocks:
•
•
•
•
•
•
•
CAN protocol engine
TX Handler
RX Handler
SPI interface
Control logic with registers and interrupt logic
I/O pins
Crystal oscillator
3.1
CAN Module
The CAN protocol engine together with the TX and RX
handler provide all the functions required to receive
and transmit messages on the CAN bus. Messages are
transmitted by first loading the appropriate message
buffers and control registers. Transmission is initiated
by using control register bits via the SPI interface or by
using the transmit enable pins. Status and errors can
be checked by reading the appropriate registers. Any
message detected on the CAN bus is checked for
errors and then matched against the user-defined filters to see if it should be moved into one of the two
receive buffers.
FIGURE 3-1:
Control Logic
The control logic block controls the setup and operation
of the MCP25625 and contains the registers.
Interrupt pins are provided to allow greater system
flexibility. There is one multi-purpose interrupt pin (as
well as specific interrupt pins) for each of the receive
registers that can be used to indicate a valid message
has been received and loaded into one of the receive
buffers. Use of the specific interrupt pins is optional.
The general purpose interrupt pin, as well as STATUS
registers (accessed via the SPI interface), can also be
used to determine when a valid message has been
received.
Additionally, there are three pins available to initiate
immediate transmission of a message that has been
loaded into one of the three transmit registers. Use of
these pins is optional, as initiating message
transmissions can also be accomplished by utilizing
control registers, accessed via the SPI interface.
3.3
SPI Protocol Block
The microcontroller interfaces to the device via the SPI
interface. Registers can be accessed using the SPI
Read and Write commands. Specialized SPI
commands reduce the SPI overhead.
CAN CONTROLLER BLOCK DIAGRAM
CS
TX Handler
TX
Prioritization
SCK
SI
RXCAN
CAN
Protocol
Engine
SPI IF
SO
RX Handler
Acceptance
Filters and
Masks
VDD
INT
RX0BF
TXCAN
Control Logic
Registers: Configuration, Control and Interrupts
GND
RX1BF
OSC1
TX0RTS
TX1RTS
Crystal
Oscillator
OSC2
CLKOUT
TX2RTS
RESET
2014 Microchip Technology Inc.
DS20005282A-page 9
MCP25625
3.4
CAN Buffers and Filters
Figure 3-2 shows the CAN buffers and filters in more
detail. The MCP25625 has three transmit and two
receive buffers, two acceptance masks (one per
receive buffer), and a total of six acceptance filters.
FIGURE 3-2:
CAN BUFFERS AND PROTOCOL ENGINE
BUFFERS
Acceptance Mask
RXM1
Acceptance Filter
RXF2
Message
Queue
Control
MESSAGE
TXREQ
ABTF
MLOA
TXERR
TXB2
MESSAGE
TXREQ
ABTF
MLOA
TXERR
TXB1
MESSAGE
TXREQ
ABTF
MLOA
TXERR
TXB0
A
c
c
e
p
t
R
X
B
0
Transmit Byte Sequencer
Acceptance Mask
RXM0
Acceptance Filter
RXF3
Acceptance Filter
RXF0
Acceptance Filter
RXF4
Acceptance Filter
RXF1
Acceptance Filter
RXF5
M
A
B
Identifier
Data Field
R
X
B
1
Identifier
Data Field
PROTOCOL
ENGINE
Transmit<7:0>
A
c
c
e
p
t
Receive<7:0>
Receive
Error
Counter
REC
Transmit
Error
Counter
ErrPas
BusOff
Protocol
Finite
State
Machine
SOF
TEC
Shift<14:0>
{Transmit<5:0>, Receive<8:0>}
Comparator
CRC<14:0>
DS20005282A-page 10
Transmit
Logic
Bit
Timing
Logic
TX
RX
Clock
Generator
Configuration
Registers
2014 Microchip Technology Inc.
MCP25625
3.5
CAN Protocol Engine
3.5.3
The CAN protocol engine combines several functional
blocks, shown in Figure 3-3 and described below.
3.5.1
PROTOCOL FINITE STATE
MACHINE
The heart of the engine is the Finite State Machine
(FSM). The FSM is a sequencer that controls the
sequential data stream between the TX/RX shift
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
the parallel data stream between the TX/RX shift
registers and the buffers. The FSM ensures that the
processes of reception, arbitration, transmission and
error-signaling are performed according to the CAN
protocol. The automatic retransmission of messages
on the bus line is also handled by the FSM.
3.5.2
CYCLIC REDUNDANCY CHECK
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code, which is
transmitted after either the Control Field (for messages
with 0 data bytes) or the Data Field and is used to
check the CRC field of incoming messages.
FIGURE 3-3:
ERROR MANAGEMENT LOGIC
The Error Management Logic (EML) is responsible for
the fault confinement of the CAN device. Its two
counters, the Receive Error Counter (REC) and the
Transmit Error Counter (TEC), are incremented and
decremented by commands from the bit stream
processor. Based on the values of the error counters,
the CAN controller is set into the states error-active,
error-passive or bus-off.
3.5.4
BIT TIMING LOGIC
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus-related bit timing according to the
CAN protocol. The BTL synchronizes on a recessiveto-dominant bus transition at Start-of-Frame (hard
synchronization) and on any further recessive-todominant bus line transition if the CAN controller itself
does not transmit a dominant bit (resynchronization).
The BTL also provides programmable time segments
to compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. The programming of the BTL
depends on the baud rate and external physical delay
times.
CAN PROTOCOL ENGINE BLOCK DIAGRAM
RX
Bit Timing Logic
TX
Transmit Logic
SAM
Receive
Error Counter
Sample<2:0>
REC
TEC
StuffReg<5:0>
Transmit
Error Counter
Majority
Decision
ErrPas
BusOff
BusMon
Comparator
CRC<14:0>
Protocol
FSM
SOF
Comparator
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
Receive<7:0>
Transmit<7:0>
RecData<7:0>
TrmData<7:0>
Interface to Standard Buffer
2014 Microchip Technology Inc.
Rec/Trm Addr.
DS20005282A-page 11
MCP25625
3.6
Message Transmission
3.6.3
INITIATING TRANSMISSION
The transmit registers are described in Section 4.1
“Message Transmit Registers”.
In order to initiate message transmission, the TXREQ
bit in the TXBnCTRL register must be set for each buffer to be transmitted. This can be accomplished by:
3.6.1
• Writing to the register via the SPI Write command
• Sending the SPI RTS command
• Setting the TXnRTS pin low for the particular
transmit buffer(s) that are to be transmitted
TRANSMIT BUFFERS
The MCP25625 implements three transmit buffers.
Each of these buffers occupies 14 bytes of SRAM and
are mapped into the device memory map.
The first byte, TXBnCTRL, is a control register
associated with the message buffer. The information in
this register determines the conditions under which the
message will be transmitted and indicates the status of
the message transmission (see Register 4-1).
Five bytes are used to hold the standard and extended
identifiers, as well as other message arbitration
information (see Registers 4-3 through 4-7). The last
eight bytes are for the eight possible data bytes of the
message to be transmitted (see Register 4-8).
At a minimum, the TXBnSIDH, TXBnSIDL and
TXBnDLC registers must be loaded. If data bytes are
present in the message, the TXBnDm registers must
also be loaded. If the message is to use extended
identifiers, the TXBnEIDm registers must also be
loaded and the EXIDE bit in the TXBnSIDL register
should be set.
Prior to sending the message, the microcontroller must
initialize the TXInE bit in the CANINTE register to
enable or disable the generation of an interrupt when
the message is sent.
Note:
3.6.2
The TXREQ bit in the TXBnCTRL register
must be clear (indicating the transmit buffer is not pending transmission) before
writing to the transmit buffer.
TRANSMIT PRIORITY
Transmit priority is a prioritization within the CAN controller of the pending transmittable messages. This is
independent from, and not necessarily related to, any
prioritization implicit in the message arbitration scheme
built into the CAN protocol.
If transmission is initiated via the SPI interface, the
TXREQ bit can be set at the same time as the TXP
priority bits.
When the TXREQ is set, the ABTF, MLOA and TXERR
bits in the TXBnCTRL register will be cleared automatically.
Note:
Once the transmission has completed successfully, the
TXREQ bit will be cleared, the TXnIF bit in the
CANINTF register will be set and an interrupt will be
generated if the TXnIE bit in the CANINTE register is
set.
If the message transmission fails, the TXREQ bit will
remain set. This indicates that the message is still
pending for transmission and one of the following
condition flags will be set:
• If the message started to transmit but encountered an error condition, the TXERR bit in the
TXBnCTRL register and the MERRF bit in the
CANINTF register will be set and an interrupt will
be generated on the INT pin if the MERRE bit in
the CANINTE register is set
• If arbitration is lost, the MLOA bit in the
TXBnCTRL register will be set
Note:
Prior to sending the SOF, the priority of all buffers that
are queued for transmission is compared. The transmit
buffer with the highest priority will be sent first. For
example, if transmit buffer 0 has a higher priority setting
than transmit buffer 1, buffer 0 will be sent first.
If two buffers have the same priority setting, the buffer
with the highest buffer number will be sent first. For
example, if transmit buffer 1 has the same priority
setting as transmit buffer 0, buffer 1 will be sent first.
The TXP<1:0> bits in the TXBnCTRL register (see
Register 4-1) allow the selection of four levels of
transmit priority for each transmit buffer individually. A
buffer with TXP bits equal to 11 has the highest
possible priority, while a buffer with TXP bits equal to
00 has the lowest possible priority.
DS20005282A-page 12
Setting the TXREQ bit in the TXBnCTRL
register does not initiate a message transmission. It merely flags a message buffer
as being ready for transmission. Transmission will start when the device detects
that the bus is available.
3.6.4
If
One-Shot
mode
is
enabled
(OSM bit in the CANCTRL register), the
above conditions will still exist. However,
the TXREQ bit will be cleared and the
message will not attempt transmission a
second time.
ONE-SHOT MODE
One-Shot mode ensures that a message will only
attempt to transmit one time. Normally, if a CAN
message loses arbitration or is destroyed by an error
frame, the message is retransmitted. With One-Shot
mode enabled, a message will only attempt to transmit
one time, regardless of arbitration loss or error frame.
One-Shot mode is required to maintain time slots in
deterministic systems, such as TTCAN.
2014 Microchip Technology Inc.
MCP25625
3.6.5
TXnRTS PINS
The TXnRTS pins are input pins that can be configured
as:
• Request-to-send inputs, which provide an
alternative means of initiating the transmission of
a message from any of the transmit buffers
• Standard digital inputs
Configuration and control of these pins is accomplished
using the TXRTSCTRL register (see Register 4-2). The
TXRTSCTRL register can only be modified when the
CAN controller is in Configuration mode (see
Section 2.0 “Modes of Operation”). If configured to
operate as a request-to-send pin, the pin is mapped
into the respective TXREQ bit in the TXBnCTRL
register for the transmit buffer. The TXREQ bit is
latched by the falling edge of the TXnRTS pin. The
TXnRTS pins are designed to allow them to be tied
directly to the RXnBF pins to automatically initiate a
message transmission when the RXnBF pin goes low.
The TXnRTS pins have internal pull-up resistors of
100 k (nominal).
3.6.6
ABORTING TRANSMISSION
The MCU can request to abort a message in a specific
message buffer by clearing the associated TXREQ bit.
In addition, all pending messages can be requested to
be aborted by setting the ABAT bit in the CANCTRL
register. This bit MUST be reset (typically after the
TXREQ bits have been verified to be cleared) to continue transmitting messages. The ABTF flag in the
TXBnCTRL register will only be set if the abort was
requested via the ABAT bit in the CANCTRL register.
Aborting a message by resetting the TXREQ bit does
NOT cause the ABTF bit to be set.
Note 1: Messages that were transmitting when
the abort was requested will continue to
transmit. If the message does not
successfully complete transmission (i.e.,
lost arbitration or was interrupted by an
error frame), it will then be aborted.
2: When One-Shot mode is enabled, if the
message is interrupted due to an error
frame or loss of arbitration, the ABTF bit
in the TXBnCTRL register will be set.
2014 Microchip Technology Inc.
DS20005282A-page 13
MCP25625
FIGURE 3-4:
TRANSMIT MESSAGE FLOWCHART
Start
The message transmission
sequence begins when the
device determines that the
TXREQ bit in the TXBnCTRL
register for any of the transmit
registers has been set.
Are any
TXREQ
bits = 1
?
No
Yes
Clearing the TXREQ bit in TxBnCTRL
register while it is set, or setting the
ABAT bit in the CANCTRL register
before the message has started
transmission, will abort the message.
Clear:
ABTF
MLOA
TXERR
in TXBnCTRL register
Is
CAN bus available
to start transmission?
is
TXREQ=0
or ABAT=1
?
No
Yes
No
Yes
Examine TXP<1:0> in the TXBnCTRL register
to Determine Highest Priority Message
Transmit Message
Was
Message Transmitted
Successfully?
Yes
Clear TXREQ
Message error
or
Lost arbitration
?
Message
Error
Set
TXERR
Lost
Arbitration
MERRE=1?
in CANINTE register
Yes
Generate
Interrupt
No
TXnIE=1?
Yes
Set
MLOA
No
Generate
Interrupt
No
Set
TXnIF in CANTINF register
Set
MERRF in CANTINF register
The TXnIE bit in the CANINTE
register determines if an
interrupt should be generated
when a message is
successfully transmitted.
GOTO START
DS20005282A-page 14
2014 Microchip Technology Inc.
MCP25625
3.7
Message Reception
3.7.2
RECEIVE PRIORITY
The registers required for message reception are
described in Section 4.2 “Message Receive
Registers”.
RXB0, the higher priority buffer, has one mask and two
message acceptance filters associated with it. The
received message is applied to the mask and filters for
RXB0 first.
3.7.1
RXB1 is the lower priority buffer, with one mask and
four acceptance filters associated with it.
RECEIVE MESSAGE BUFFERING
The MCP25625 includes two full receive buffers with
multiple acceptance filters for each. There is also a
separate Message Assembly Buffer (MAB) that acts as
a third receive buffer (see Figure 3-6).
3.7.1.1
Message Assembly Buffer
Of the three receive buffers, the MAB is always
committed to receiving the next message from the bus.
The MAB assembles all messages received. These
messages will be transferred to the RXBn buffers (see
Registers 4-12 to 4-17) only if the acceptance filter
criteria is met.
3.7.1.2
RXB0 and RXB1
The remaining two receive buffers, called RXB0 and
RXB1, can receive a complete message from the
protocol engine via the MAB. The MCU can access one
buffer, while the other buffer is available for message
reception, or for holding a previously received
message.
Note:
3.7.1.3
The entire content of the MAB is moved
into the receive buffer once a message is
accepted. This means, that regardless of
the type of identifier (standard or
extended) and the number of data bytes
received, the entire receive buffer is
overwritten with the MAB contents.
Therefore, the contents of all registers in
the buffer must be assumed to have been
modified when any message is received.
Receive Flags/interrupts
When a message is moved into either of the receive
buffers, the appropriate RXnIF bit in the CANINTF register is set. This bit must be cleared by the MCU in
order to allow a new message to be received into the
buffer. This bit provides a positive lockout to ensure
that the MCU has finished with the message before the
CAN controller attempts to load a new message into
the receive buffer.
If the RXnIE bit in the CANINTE register is set, an interrupt will be generated on the INT pin to indicate that a
valid message has been received. In addition, the
associated RXnBF pin will drive low if configured as a
receive buffer full pin. See Section 3.7.4 “RX0BF and
RX1BF Pins” for details.
2014 Microchip Technology Inc.
In addition to the message being applied to the RB0
mask and filters first, the lower number of acceptance
filters makes the match on RXB0 more restrictive and
implies a higher priority for that buffer.
When a message is received, bits <3:0> of the
RXBnCTRL register will indicate the acceptance filter
number that enabled reception and whether the
received message is a remote transfer request.
3.7.2.1
Rollover
Additionally, the RXB0CTRL register can be configured
such that, if RXB0 contains a valid message and
another valid message is received, an overflow error
will not occur and the new message will be moved into
RXB1, regardless of the acceptance criteria of RXB1.
3.7.2.2
RXM Bits
The RXM bits in the RXBnCTRL register set special
receive modes. Normally, these bits are cleared to 00
to enable reception of all valid messages as
determined by the appropriate acceptance filters. In
this case, the determination of whether or not to receive
standard or extended messages is determined by the
EXIDE bit in the RFXnSIDL register, in the acceptance
filter register.
If the RXM bits in the RXBnCTRL register are set to ‘01’
or 10, the receiver will only accept messages with standard or extended identifiers, respectively. If an acceptance filter has the EXIDE bit in the RXBnCTRL register
set such that it does not correspond with the RXM
mode, that acceptance filter is rendered useless.
These two modes of the RXM bits can be used in
systems where it is known that only standard or
extended messages will be on the bus.
If the RXM bits are set to ‘11’, the buffer will receive all
messages, regardless of the values of the acceptance
filters. Also, if a message has an error before the EOF,
that portion of the message assembled in the MAB
before the error frame will be loaded into the buffer.
This mode has some value in debugging a CAN system
and would not be used in an actual system
environment.
DS20005282A-page 15
MCP25625
3.7.3
START-OF-FRAME SIGNAL
3.7.4.1
If enabled, the Start-Of-Frame signal is generated on
the SOF pin at the beginning of each CAN message
detected on the RXCAN pin.
The RXBnBF pins can be disabled to the highimpedance state by clearing the BnBFE bit in the
BFPCTRL register.
The RXCAN pin monitors an idle bus for a recessive-todominant edge. If the dominant condition remains until
the sample point, the MCP25625 interprets this as a
SOF and a SOF pulse is generated. If the dominant
condition does not remain until the sample point, the
MCP25625 interprets this as a glitch on the bus and no
SOF signal is generated. Figure 3-5 illustrates SOF
signaling and glitch-filtering.
3.7.4.2
RX0BF AND RX1BF PINS
In addition to the INT pin, which provides an interrupt
signal to the MCU for many different conditions, the
receive buffer full pins (RX0BF and RX1BF) can be
used to indicate that a valid message has been loaded
into RXB0 or RXB1, respectively. The pins have three
different configurations (Table 3-1):
1.
2.
3.
Configured as Buffer Full
The RXBnBF pins can be configured to act as either
buffer full interrupt pins or as standard digital outputs.
Configuration and status of these pins is available via
the BFPCTRL register (Register 4-11). When set to
operate in Interrupt mode (by setting the BxBFE and
BxBFM bits in the BFPCTRL register), these pins are
active-low and are mapped to the RXnIF bit in the
CANINTF register for each receive buffer. When this bit
goes high for one of the receive buffers (indicating that
a valid message has been loaded into the buffer), the
corresponding RXBnBF pin will go low. When the
RXnIF bit is cleared by the MCU, the corresponding
interrupt pin will go to the logic-high state until the next
message is loaded into the receive buffer.
As with One-Shot mode, one use for SOF signaling is
for TTCAN-type systems. In addition, by monitoring
both the RXCAN pin and the SOF pin, an MCU can
detect early physical bus problems by detecting small
glitches before they affect the CAN communication.
3.7.4
Disabled
Disabled
Buffer Full Interrupt
Digital Output
FIGURE 3-5:
START-OF-FRAME SIGNALING
Normal SOF Signaling
START-OF-FRAME BIT
ID BIT
Sample
Point
RXCAN
SOF
Glitch-Filtering
EXPECTED START-OF-FRAME BIT
Expected
Sample
Point
BUS IDLE
RXCAN
SOF
DS20005282A-page 16
2014 Microchip Technology Inc.
MCP25625
3.7.4.3
Configured as Digital Output
TABLE 3-1:
When used as digital outputs, the BxBFM bit in the
BFPCTRL register must be cleared and BnBFE must
be set for the associated buffer. In this mode, the state
of the pin is controlled by the BnBFS bits in the same
register. Writing a ‘1’ to the BnBFS bit will cause a high
level to be driven on the associated buffer full pin, while
a ‘0’ will cause the pin to drive low. When using the pins
in this mode, the state of the pin should be modified
only by using the Bit Modify SPI command to prevent
glitches from occurring on either of the buffer full pins.
FIGURE 3-6:
CONFIGURING RXNBF PINS
BnBFE BnBFM BnBFS
Pin Status
0
X
X
Disabled, high-impedance
1
1
X
Receive buffer interrupt
1
0
0
Digital output = 0
1
0
1
Digital output = 1
RECEIVE BUFFER BLOCK DIAGRAM
Acceptance Mask
RXM1
Acceptance Filter
RXF2
Acceptance Mask
RXM0
A
c
c
e
p
t
Acceptance Filter
RXF0
Acceptance Filter
RXF4
Acceptance Filter
RXF1
Acceptance Filter
RXF5
R
X
B
0
Identifier
Data Field
Note:
Acceptance Filter
RXF3
M
A
B
Identifier
A
c
c
e
p
t
R
X
B
1
Data Field
Messages received in the MAB are initially applied to the mask and filters of RXB0. In
addition, only one filter match occurs (e.g., if the message matches both RXF0 and
RXF2, the match will be for RXF0 and the message will be moved into RXB0).
2014 Microchip Technology Inc.
DS20005282A-page 17
MCP25625
FIGURE 3-7:
RECEIVE FLOW FLOWCHART
Start
No
Detect
Start of
Message?
Yes
Begin Loading Message into
Message Assembly Buffer (MAB)
Generate
Error
Frame
No
Valid
Message
Received?
Yes
Yes
Meets
a filter criteria
for RXB0?
Meets
a filter criteria
for RXB1?
No
Yes
No
Go to Start
Determines if the receive
register is empty and able
to accept a new message
Determines if RXB0 can roll
over into RXB1, if it is full.
Is
RX0IF = 0?
Is
BUKT = 1?
No
No
Yes
Generate Overflow Error:
Set RX0OVR in EFLG reg.
Move message into RXB0
Set RX0IF =
Yes
Generate Overflow Error:
Set RX1OVRin EFLG reg.
Is
RX1IF = 0?
No
1 in CANINTF reg.
Yes
Move message into RXB1
Is
No
ERRIE = 1?
in CANINTE register
Set FILHIT0 in RXB0CTRL register
according to which filter criteria
Set RX1IF = 1 in CANINTF reg.
Yes
Generate
Interrupt on INT
RX0IE = 1?
in CANINTE register
Yes
Are
B0BFM = 1
in BFPCTRL reg.
and
B0BFE = 1?
in BF1CTRL reg.
No
DS20005282A-page 18
Yes
Set CANSTAT <3:0> according to which receive buffer
the message was loaded into
Set RXBF0
Pin = 0
Set FILHIT <2:0> in RXB1CTRL
register according to which
filter criteria was met
Yes
Generate
Interrupt on INT
RXB0
No
Go to Start
RXB1
Set RXBF1
Pin = 0
RX1IE = 1?
in CANINTE register
No
Yes
Are
B1BFM = 1
in BFPCTRL reg.
and
B1BFE = 1?
in BF1CTRL reg.
No
2014 Microchip Technology Inc.
MCP25625
3.7.5
MESSAGE ACCEPTANCE FILTERS
AND MASKS
The message acceptance filters and masks are used to
determine if a message in the message assembly buffer should be loaded into either of the receive buffers
(see Figure 3-9). Once a valid message has been
received into the MAB, the identifier fields of the message are compared to the filter values. If there is a
match, that message will be loaded into the appropriate
receive buffer.
The registers required for message filtering are
described in Section 4.3 “Acceptance Filter Registers”.
3.7.5.1
Data Byte Filtering
3.7.5.2
The filter masks (see Registers 4-22 through 4-25)
are used to determine which bits in the identifier are
examined with the filters. A truth table is shown in
Table 3-2 that indicates how each bit in the identifier is
compared to the masks and filters to determine if the
message should be loaded into a receive buffer. The
mask essentially determines which bits to apply the
acceptance filters to. If any mask bit is set to a zero,
that bit will automatically be accepted, regardless of
the filter bit.
TABLE 3-2:
FIGURE 3-8:
FILTER/MASK TRUTH TABLE
Mask Bit n
Filter Bit n
Message
Identifier
bit
Accept or
Reject bit n
0
X
X
Accept
1
0
0
Accept
1
0
1
Reject
1
1
0
Reject
1
1
1
Accept
When receiving standard data frames (11-bit identifier),
the MCP25625 automatically applies 16 bits of masks
and filters normally associated with extended
identifiers to the first 16 bits of the data field (data bytes
0 and 1). Figure 3-8 illustrates how masks and filters
apply to extended and standard data frames.
Data byte filtering reduces the load on the MCU when
implementing Higher Layer Protocols (HLPs) that filter
on the first data byte (e.g., DeviceNet™).
Filter Matching
Note 1:
X = don’t care
As shown in the receive buffers block diagram
(Figure 3-6), acceptance filters RXF0 and RXF1 (and
filter mask RXM0) are associated with RXB0. Filters
RXF2, RXF3, RXF4, RXF5 and mask RXM1 are
associated with RXB1.
MASKS AND FILTERS APPLY TO CAN FRAMES
Extended Frame
ID10
ID0 EID17
EID0
Masks and Filters apply to the entire 29-bit ID field
Standard Data Frame
ID10
ID0 *
11-bit ID Standard frame
Data Byte 0
Data Byte 1
16-bit data filtering *
* The two MSb (EID17 and EID16) mask and filter bits are not used.
2014 Microchip Technology Inc.
DS20005282A-page 19
MCP25625
3.7.5.3
FILHIT Bits
Filter matches on received messages can be
determined by the FILHIT bits in the associated
RXBnCTRL register. FILHIT0 bit in the RXB0CTRL
register for buffer 0 and FILHIT<2:0> bits in the
RXB1CTRL register for buffer 1.
The three FILHIT bits for receive buffer 1 (RXB1) are
coded as follows:
-
101 = Acceptance Filter 5 (RXF5)
100 = Acceptance Filter 4 (RXF4)
011 = Acceptance Filter 3 (RXF3)
010 = Acceptance Filter 2 (RXF2)
001 = Acceptance Filter 1 (RXF1)
000 = Acceptance Filter 0 (RXF0)
Note:
000 and 001 can only occur if the BUKT
bit in RXB0CTRL is set, allowing RXB0
messages to roll over into RXB1.
RXB0CTRL contains two copies of the BUKT bit and
the FILHIT<0> bit.
The coding of the BUKT bit enables these three bits to
be used similarly to the FILHIT bits in the RXB1CTRL
register and to distinguish a hit on filter RXF0 and
RXF1 in either RXB0 or after a rollover into RXB1.
-
If the BUKT bit is clear, there are six codes
corresponding to the six filters. If the BUKT bit is set,
there are six codes corresponding to the six filters, plus
two additional codes corresponding to RXF0 and RXF1
filters that roll over into RXB1.
3.7.5.4
Multiple Filter Matches
If more than one acceptance filter matches, the FILHIT
bits will encode the binary value of the lowest
numbered filter that matched. For example, if filter
RXF2 and filter RXF4 match, FILHIT will be loaded with
the value for RXF2. This essentially prioritizes the
acceptance filters with a lower-numbered filter having
higher priority. Messages are compared to filters in
ascending order of filter number. This also ensures that
the message will only be received into one buffer. This
implies that RXB0 has a higher priority than RXB1.
3.7.5.5
Configuring the Masks and Filters
The mask and filter registers can only be modified
when the MCP25625 is in Configuration mode (see
Section 2.0 “Modes of Operation”).
Note:
The mask and filter registers read all '0'
when in any mode except Configuration
mode.
111 = Acceptance Filter 1 (RXB1)
110 = Acceptance Filter 0 (RXB1)
001 = Acceptance Filter 1 (RXB0)
000 = Acceptance Filter 0 (RXB0)
FIGURE 3-9:
MESSAGE ACCEPTANCE MASK AND FILTER OPERATION
Acceptance Filter Register
RXFn0
Acceptance Mask Register
RXMn0
RXMn1
RXFn1
RXFni
RxRqst
RXMni
Message Assembly Buffer
Identifier
DS20005282A-page 20
2014 Microchip Technology Inc.
MCP25625
3.8
CAN Bit Time
The Nominal Bit Rate (NBR) is the number of bits per
second transmitted on the CAN bus, see Equation 3-1.
EQUATION 3-1:
NOMINAL BIT RATE/TIME
1
NBR = ----------NBT
The Nominal Bit Time (NBT) is made up of four
non-overlapping segments. Each of these segments is
made up of an integer number of so called Time
Quanta (TQ).
The length of each Time Quantum is based on the
oscillator period (TOSC). Equation 3-2 illustrates how
the Time Quantum can be programmed using the Baud
Rate Prescaler (BRP):
EQUATION 3-2:
TIME QUANTA
2 BRP + 1
TQ = 2 BRP + 1 T OSC = ----------------------------------FOSC
Figure 3-10 illustrates how the Nominal Bit Time is
made up of four segments:
• Synchronization Segment (SYNC) –
synchronizes the different nodes connected on
the CAN bus. A bit edge is expected to be within
this segment. Based on the CAN protocol, the
Synchronization Segment is 1 TQ. See
Section 3.8.3 “Synchronization” for more
details on synchronization.
• Propagation Segment (PRSEG) – compensates
for the propagation delay on the bus. It is
programmable from 1 to 8 TQ.
• Phase Segment 1 (PHSEG1) – This time
segment compensates for errors that may occur
due to phase shifts in the edges. The time
segment may be automatically lengthened during
resynchronization to compensate for the phase
shift. It is programmable from 1 to 8 TQ.
• Phase Segment 2 (PHSEG2) – This time
segment compensates for errors that may occur
due to phase shifts in the edges. The time
segment may be automatically shortened during
resynchronization to compensate for the phase
shift. It is programmable from 2 to 8 TQ.
The total number of Time Quanta in a Nominal Bit Time
is programmable and can be calculated using
Equation 3-3.
EQUATION 3-3:
TQ PER NBT
NBT
----------- = SYNC + PRSEG + PHSEG1 + PHSEG2
TQ
FIGURE 3-10:
ELEMENTS OF A NOMINAL BIT TIME
TOSC
TBRPCLK
NBT
SYNC
(1 TQ)
PRSEG
(1-8 TQ)
PHSEG1
(1-8 TQ)
PHSEG2
(2-8 TQ)
TQ
Sample Point
Nominal Bit Time
2014 Microchip Technology Inc.
DS20005282A-page 21
MCP25625
3.8.1
SAMPLE POINT
3.8.5
The sample point is the point in the Nominal Bit Time at
which the logic level is read and interpreted. The CAN
bus can be sampled once or three times, as configured
by SAM in the CNF2 register:
• SAM = 0: the sample point is located between
PHSEG1 and PHSEG2.
• SAM = 1: one sample point is located between
PHSEG1 and PHSEG2. Additionally, two samples
are taken at one-half TQ intervals prior to the end
of PHSEG1, with the value of the bit being determined by a majority decision.
The sample point in percent can be calculated using
Equation 3-4.
EQUATION 3-4:
(IPT) is the time
determine the bit
the MCP25625 is
PHSEG2 is also
Equation 3-6 and Equation 3-7 describe the conditions
for the maximum tolerance of the oscillator.
EQUATION 3-5:
The CAN controller expects an edge in the received
signal to occur within the SYNC segment. Only recessive-to-dominant edges are used for synchronization.
There are two mechanisms used for synchronization:
• Hard synchronization – forces the edge that has
occurred to lie within the SYNC segment. The bit
time counter is restarted with SYNC.
• Resynchronization – if the edge falls outside the
SYNC segment, PHSEG1 and PHSEG2 will be
adjusted.
For a more detailed description of the CAN
synchronization, please refer to AN754 –
“Understanding Microchip’s CAN Module Bit Timing”
(DS00754) and ISO11898-1.
SYNCHRONIZATION JUMP WIDTH
The Synchronization Jump Width (SJW) is the maximum amount PHSEG1 and PHSEG2 can be adjusted
during resynchronization. SJW is programmable from 1
to 4 TQ.
DS20005282A-page 22
OSCILLATOR
TOLERANCE
1 – df fnom F OSC 1 + df fnom
EQUATION 3-6:
CONDITION 1
SJW
df --------------------------------NBT
2 10 ----------TQ
EQUATION 3-7:
CONDITION 2
min PHSEG1 ,PHSEG2
df -----------------------------------------------------------------NBT
2 13 ----------- – PHSEG2
TQ
SYNCHRONIZATION
To compensate for phase shifts between the oscillator
frequencies of the nodes on the bus, each CAN controller must be able to synchronize to the relevant edge of
the incoming signal.
3.8.4
The oscillator tolerance (df), around the nominal
frequency of the oscillator (fnom), is defined in
Equation 3-5.
INFORMATION PROCESSING TIME
The Information Processing Time
required for the CAN controller to
level of a sampled bit. The IPT for
2 TQ. Therefore, the minimum of
2 TQ.
3.8.3
According to the CAN specification, the bit timing
requirements allow ceramic resonators to be used in
applications with transmission rates of up to 125 kbps,
as a rule of thumb. For the full bus speed range of the
CAN protocol, a quartz oscillator is required. A maximum node-to-node oscillator variation of 1.58% is
allowed.
SAMPLE POINT
PRSEG + PHSEG1
SP = -------------------------------------------------- 100
NBT
----------TQ
3.8.2
OSCILLATOR TOLERANCE
3.8.6
PROPAGATION DELAY
Figure 3-11 illustrates the propagation delay between
two CAN nodes on the bus. Assuming Node A is
transmitting a CAN message. The transmitted bit will
propagate from the transmitting CAN Node A, through
the transmitting CAN transceiver, over the CAN bus,
through the receiving CAN transceiver, into the
receiving CAN Node B.
During the arbitration phase of a CAN message, the
transmitter samples the bus and checks if the
transmitted bit matches the received bit. The
transmitting node has to place the sample point after
the maximum propagation delay.
Equation 3-8 describes the maximum propagation
delay; where tTXD-RXD is the propagation delay of the
transceiver, 235 ns for the MCP25625; TBUS is the
delay on the CAN bus, approximately 5 ns/m. The factor two comes from the worst case, when Node B starts
transmitting exactly when the bit from Node A arrives.
EQUATION 3-8:
MAXIMUM PROPAGATION
DELAY
T PROP = 2 t TXD – RXD + T BUS
2014 Microchip Technology Inc.
MCP25625
FIGURE 3-11:
PROPAGATION DELAY
Delay: Node A to B (TPROPAB)
TXCAN
CANH
CANH
CANL
CANL
Node A
RXCAN
Node B
RXCAN
TXCAN
CAN bus (TBUS)
Transceiver Propagation
Delay (tTXD-RXD)
Transceiver Propagation
Delay (tTXD-RXD)
Delay: Node B to A (TPROPAB)
T PROP = T PROPAB + T PROPBA = 2 t TXD – RXD + T BUS
3.8.7
BIT TIME CONFIGURATION
EXAMPLE
The following example illustrates the configuration of
the CAN bit time registers. Assuming we want to setup
a CAN network in an automobile with the following
parameters:
• 500 kbps Nominal Bit Rate (NBR)
• Sample point between 60 and 80% of the Nominal
Bit Time (NBT)
• 40m minimum bus length
TABLE 3-3:
Table 3-3 illustrates how the bit time parameters are
calculated. Since the parameters depend on multiple
constraints and equations, and are calculated using an
iterative process, it is recommended to enter the
equations into a spread sheet.
A detailed description of the Bit Time Configuration
registers can be found in Section 4.4 “Bit Time
Configuration Registers”.
STEP-BY-STEP REGISTER CONFIGURATION EXAMPLE
Parameter
Register
Constraint
Value
Unit
Equations and Comments
NBT
—
NBT 1 µs
2
us
FOSC
—
FOSC < 25 MHz
16
MHz
TQ/Bit
—
5 to 25
16
TQ
—
NBT, FOSC
125
CNF1
0 to 63
0
—
Fixed
1
TQ
Defined in ISO 11898-1
PRSEG
CNF2
1 to 8 TQ;
PRSEG > TPROP
7
TQ
Equation 3-8: TPROP = 870 ns,
minimum PRSEG = TPROP/TQ = 6.96 TQ.
Selecting 7 will allow 40m bus length
PHSEG1
CNF2
1 to 8 TQ;
PHSEG1 SJW
4
TQ
There are 8 TQ remaining for
PHSEG1 + PHSEG2. Divide the remaining
TQ in half to maximize SJW
PHSEG2
CNF3
2 to 8 TQ;
PHCSEG2 SJW
4
TQ
There are 4 TQ remaining
SJW
CNF1
1 to 4 TQ;
SJW min(PHSEG1, PHSEG2)
4
TQ
Maximizing SJW lessens the requirement for
the oscillator tolerance
Sample Point
—
Usually between 60 and 80%
69
%
Use Equation 3-4 to double check sample
point
Oscillator Tolerance
Condition 1
—
Double check
1.25
%
Equation 3-6
Oscillator Tolerance
Condition 2
—
Double check
0.98
%
Equation 3-7. Better than 1% crystal oscillator
required
BRP
SYNC
2014 Microchip Technology Inc.
Equation 3-1
Select crystal or resonator frequency, usually
16 or 20 MHz work
The sum of the TQ of all four segments must
be between 5 and 25. Selecting 16 TQ per bit
is a good starting point
ns
Equation 3-3
Equation 3-2
DS20005282A-page 23
MCP25625
3.9
Error Detection
The CAN protocol provides sophisticated error
detection mechanisms. The following errors can be
detected.
The registers required for error detection are described
in Section 4.5 “Error Detection Registers”.
3.9.1
CRC ERROR
With the Cyclic Redundancy Check (CRC), the
transmitter calculates special check bits for the bit
sequence from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC Field. The receiving node also calculates the
CRC sequence using the same formula and performs
a comparison to the received sequence. If a mismatch
is detected, a CRC error has occurred and an error
frame is generated. The message is repeated.
3.9.2
ACKNOWLEDGE ERROR
In the acknowledge field of a message, the transmitter
checks if the acknowledge slot (which has been sent
out as a recessive bit) contains a dominant bit. If not, no
other node has received the frame correctly. An
acknowledge error has occurred, an error frame is
generated and the message will have to be repeated.
3.9.3
FORM ERROR
If a node detects a dominant bit in one of the four
segments (including end-of-frame, inter-frame space,
acknowledge delimiter or CRC delimiter), a form error
has occurred and an error frame is generated. The
message is repeated.
3.9.4
BIT ERROR
A bit error occurs if a transmitter detects the opposite
bit level to what it transmitted (i.e., transmitted a
dominant and detected a recessive, or transmitted a
recessive and detected a dominant).
Exception: In the case where the transmitter sends a
recessive bit and a dominant bit is detected during the
arbitration field and the acknowledge slot, no bit error is
generated because normal arbitration is occurring.
3.9.5
STUFF ERROR
lf, between the start-of-frame and the CRC delimiter,
six consecutive bits with the same polarity are
detected, the bit-stuffing rule has been violated. A stuff
error occurs and an error frame is generated. The
message is repeated.
DS20005282A-page 24
3.9.6
ERROR STATES
Detected errors are made known to all other nodes via
error frames. The transmission of the erroneous message is aborted and the frame is repeated as soon as
possible. Furthermore, each CAN node is in one of the
three error states according to the value of the internal
error counters:
1.
2.
3.
Error-active
Error-passive
Bus-off (transmitter only)
The error-active state is the usual state where the node
can transmit messages and active error frames (made
of dominant bits) without any restrictions.
In the error-passive state, messages and passive error
frames (made of recessive bits) may be transmitted.
The bus-off state makes it temporarily impossible for
the station to participate in the bus communication.
During this state, messages can neither be received
nor transmitted. Only transmitters can go bus-off.
3.10
Error Modes and Error Counters
The MCP25625 contains two error counters: the
Receive Error Counter (REC) (see Register 4-30) and
the Transmit Error Counter (TEC) (see Register 4-29).
The values of both counters can be read by the MCU.
These counters are incremented/decremented in
accordance with the CAN bus specification.
The MCP25625 is error-active if both error counters are
below the error-passive limit of 128.
It is error-passive if at least one of the error counters
equals or exceeds 128.
It goes to bus-off if the TEC exceeds the bus-off limit of
255. The device remains in this state until the bus-off
recovery sequence is received. The bus-off recovery
sequence consists of 128 occurrences of 11
consecutive recessive bits (see Figure 3-12).
Note:
The MCP25625, after going bus-off, will
recover back to error-active without any
intervention by the MCU if the bus
remains idle for 128 x 11 bit times. If this is
not desired, the error Interrupt Service
Routine should address this.
The Current Error mode of the MCP25625 can be read
by the MCU via the EFLG register (see Register 4-31).
Additionally, there is an error state warning flag bit
(EWARN bit in the EFLG register) which is set if at least
one of the error counters equals or exceeds the error
warning limit of 96. EWARN is reset if both error
counters are less than the error warning limit.
2014 Microchip Technology Inc.
MCP25625
FIGURE 3-12:
ERROR MODES STATE DIAGRAM
Reset
REC < 127 or
TEC < 127
Error-Active
128 occurrences of
11 consecutive
“recessive” bits
REC > 127 or
TEC > 127
Error-Passive
TEC > 255
Bus-Off
3.11
Interrupts
The MCP25625 has eight sources of interrupts. The
CANINTE register contains the individual interrupt
enable bits for each interrupt source. The CANINTF
register contains the corresponding interrupt flag bit for
each interrupt source. When an interrupt occurs, the
INT pin is driven low by the MCP25625 and will remain
low until the interrupt is cleared by the MCU. An
interrupt can not be cleared if the respective condition
still prevails.
It is recommended that the Bit Modify command be
used to reset flag bits in the CANINTF register rather
than normal write operations. This is done to prevent
unintentionally changing a flag that changes during the
Write command, potentially causing an interrupt to be
missed.
It should be noted that the CANINTF flags are
read/write and an interrupt can be generated by the
microcontroller setting any of these bits, provided the
associated CANINTE bit is also set.
The Interrupt registers are described in Section 4.6
“Interrupt Registers”.
3.11.1
TABLE 3-4:
ICOD<2:0> DECODE
ICOD<2:0>
Boolean Expression
000
ERR•WAK•TX0•TX1•TX2•RX0•RX1
001
ERR
010
ERR•WAK
011
ERR•WAK•TX0
100
ERR•WAK•TX0•TX1
101
ERR•WAK•TX0•TX1•TX2
110
ERR•WAK•TX0•TX1•TX2•RX0
111
ERR•WAK•TX0•TX1•TX2•RX0•RX1
Note:
2014 Microchip Technology Inc.
INTERRUPT CODE BITS
The source of a pending interrupt is indicated in the
ICOD (interrupt code) bits in the CANSTAT register, as
indicated in Register 4-35. In the event that multiple
interrupts occur, the INT pin will remain low until all
interrupts have been reset by the MCU. The ICOD bits
will reflect the code for the highest priority interrupt that
is currently pending. Interrupts are internally prioritized
such that the lower the ICOD value, the higher the
interrupt priority. Once the highest priority interrupt
condition has been cleared, the code for the next
highest priority interrupt that is pending (if any) will be
reflected by the ICOD bits (see Table 3-4). Only those
interrupt sources that have their associated CANINTE
enable bit set will be reflected in the ICOD bits.
ERR is associated with ERRIE bit in the
CANINTE register.
DS20005282A-page 25
MCP25625
3.11.2
TRANSMIT INTERRUPT
3.12.2.1
When the transmit interrupt is enabled (TXnIE = 1 in the
CANINTE register), an interrupt will be generated on the
INT pin once the associated transmit buffer becomes
empty and is ready to be loaded with a new message.
The TXnIF bit in the CANINTF register will be set to indicate the source of the interrupt. The interrupt is cleared
by clearing the TXnIF bit.
3.11.3
RECEIVE INTERRUPT
When
the
receive
interrupt
is
enabled
(RXnIE = 1 in the CANINTE register), an interrupt will
be generated on the INT pin once a message has been
successfully received and loaded into the associated
receive buffer. This interrupt is activated immediately
after receiving the EOF field. The RXnIF bit in the
CANINTF register will be set to indicate the source of
the interrupt. The interrupt is cleared by clearing the
RXnIF bit.
3.12
Message Error Interrupt
Receiver overflow
An overflow condition occurs when the MAB has
assembled a valid receive message (the message
meets the criteria of the acceptance filters) and the
receive buffer associated with the filter is not available
for loading of a new message. The associated
RXnOVR bit in the EFLG register will be set to indicate
the overflow condition. This bit must be cleared by the
microcontroller.
3.12.2.2
Receiver Warning
The REC has reached the MCU warning limit of 96.
3.12.2.3
Transmitter Warning
The TEC has reached the MCU warning limit of 96.
3.12.2.4
Receiver Error-Passive
The REC has exceeded the error-passive limit of 127
and the device has gone to error-passive state.
3.12.2.5
Transmitter Error-Passive
When an error occurs during the transmission or
reception of a message, the message error flag
(MERRF bit in the CANINTF register) will be set and, if
the MERRE bit in the CANINTE register is set, an
interrupt will be generated on the INT pin. This is
intended to be used to facilitate baud rate
determination when used in conjunction with ListenOnly mode.
The TEC has exceeded the error-passive limit of 127
and the device has gone to error-passive state.
3.12.1
Interrupts are directly associated with one or more
status flags in the CANINTF register. Interrupts are
pending as long as one of the flags is set. Once an
interrupt flag is set by the device, the flag can not be
reset by the MCU until the interrupt condition is
removed.
BUS ACTIVITY WAKE-UP
INTERRUPT
When the CAN controller is in Sleep mode and the bus
activity wake-up interrupt is enabled (WAKIE = 1 in the
CANINTE register), an interrupt will be generated on the
INT pin and the WAKIF bit in the CANINTF register will be
set when activity is detected on the CAN bus. This
interrupt causes the CAN controller to exit Sleep mode.
The interrupt is reset by clearing the WAKIF bit.
Note:
3.12.2
The CAN controller
Listen-Only mode.
wakes
up
into
ERROR INTERRUPT
When the error interrupt is enabled (ERRIE = 1 in the
CANINTE register), an interrupt is generated on the
INT pin if an overflow condition occurs or if the error
state of the transmitter or receiver has changed. The
Error Flag (EFLG) register will indicate one of the
following conditions.
DS20005282A-page 26
3.12.2.6
Bus-Off
The TEC has exceeded 255 and the device has gone
to bus-off state.
3.12.3
3.13
INTERRUPT ACKNOWLEDGE
Oscillator
The MCP25625 is designed to be operated with a crystal or ceramic resonator connected to the OSC1 and
OSC2 pins. The MCP25625 oscillator design requires
the use of a parallel cut crystal. Use of a series cut
crystal may give a frequency out of the crystal
manufacturer’s specifications. A typical oscillator circuit
is shown in Figure 3-13. The MCP25625 may also be
driven by an external clock source connected to the
OSC1 pin, as shown in Figure 3-14 and Figure 3-15.
3.13.1
OSCILLATOR START-UP TIMER
The MCP25625 utilizes an Oscillator Start-up Timer
(OST) that holds the MCP25625 in Reset to ensure that
the oscillator has stabilized before the internal state
machine begins to operate. The OST maintains Reset
for the first 128 OSC1 clock cycles after power-up or a
wake-up from Sleep mode occurs. It should be noted
that no SPI protocol operations should be attempted
until after the OST has expired.
2014 Microchip Technology Inc.
MCP25625
3.13.2
CLKOUT PIN
The CLKOUT pin will be active upon system Reset and
default to the slowest speed (divide by 8) so that it can
be used as the MCU clock.
The CLKOUT pin is provided to the system designer for
use as the main system clock or as a clock input for
other devices in the system. The CLKOUT has an internal prescaler which can divide FOSC by 1, 2, 4 and 8.
The CLKOUT function is enabled and the prescaler is
selected via the CANCNTRL register (see
Register 4-34).
Note:
When Sleep mode is requested, the CAN controller will
drive sixteen additional clock cycles on the CLKOUT
pin before entering Sleep mode. The Idle state of the
CLKOUT pin in Sleep mode is low. When the CLKOUT
function is disabled (CLKEN = 0 in the CANCNTRL
register) the CLKOUT pin is in a high-impedance state.
The maximum frequency on CLKOUT is
specified as 25 MHz (see Table 7-5).
FIGURE 3-13:
The CLKOUT function is designed to ensure that
tHCLKOUT and tLCLKOUT timings are preserved when the
CLKOUT pin function is enabled, disabled or the
prescaler value is changed.
CRYSTAL/CERAMIC RESONATOR OPERATION
OSC1
C1
To internal logic
XTAL
C2
RF(2)
Sleep
RS(1)
OSC2
Note 1: A series resistor (RS) may be required for AT strip-cut crystals.
2: The feedback resistor (RF ), is typically in the range of 2 to 10 M.
FIGURE 3-14:
EXTERNAL CLOCK SOURCE
Clock from
external system
OSC1
(1)
Open
OSC2
Note 1: A resistor to ground may be used to reduce system noise. This may increase system current.
2: Duty cycle restrictions must be observed (see Table 7-2).
2014 Microchip Technology Inc.
DS20005282A-page 27
MCP25625
FIGURE 3-15:
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT (Note 1)
330 k
330 k
74AS04
74AS04
To Other
Devices
74AS04
MCP25625
OSC1
0.1 mF
XTAL
Note 1: Duty cycle restrictions must be observed (see Table 7-2).
TABLE 3-5:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Typical Capacitor Values Used:
Mode
Freq.
OSC1
OSC2
HS
8.0 MHz
27 pF
27 pF
16.0 MHz
22 pF
22 pF
TABLE 3-6:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc
Type(1)(4)
Crystal
Freq.(2)
HS
4 MHz
Typical Capacitor
Values Tested:
C1
C2
27 pF
27 pF
Capacitor values are for design guidance only:
8 MHz
22 pF
22 pF
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
20 MHz
15 pF
15 pF
Different capacitor values may be required to
produce acceptable oscillator operation. The user
should test the performance of the oscillator over the
expected VDD and temperature range for the
application.
See the notes following Table 3-6 for additional
information.
Resonators Used:
4.0 MHz
Capacitor values are for design guidance only:
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to
produce acceptable oscillator operation. The user
should test the performance of the oscillator over the
expected VDD and temperature range for the
application.
See the notes following this Table for additional
information.
8.0 MHz
Crystals Used(3):
16.0 MHz
4.0 MHz
8.0 MHz
20.0 MHz
Note 1:
2:
3:
4:
DS20005282A-page 28
While higher capacitance increases the
stability of the oscillator, it also increases
the start-up time.
Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
RS may be required to avoid overdriving
crystals with low drive level specification.
Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
2014 Microchip Technology Inc.
MCP25625
3.14
Reset
The MCP25625 differentiates between two Resets:
1.
2.
Hardware Reset – Low on RESET pin
SPI Reset – Reset via SPI command
Both of these Resets are functionally equivalent. It is
important to provide one of these two Resets after
power-up to ensure that the logic and registers are in
their default state. A hardware Reset can be achieved
automatically by placing an RC on the RESET pin (see
Figure 3-16). The values must be such that the device
is held in Reset for a minimum of 2 µs after VDD
reaches operating voltage, as indicated in the electrical
specification (tRL).
FIGURE 3-16:
RESET PIN CONFIGURATION EXAMPLE
VDD
VDD
D(1)
R
R1(2)
RESET
C
Note 1: The diode D helps discharge the capacitor quickly when VDD powers down.
2: R1 = 1 k to 10 k will limit any current flowing into RESET from external
capacitor C, in the event of RESET pin breakdown due to Electrostatic
Discharge (ESD) or Electrical Overstress (EOS).
2014 Microchip Technology Inc.
DS20005282A-page 29
MCP25625
NOTES:
DS20005282A-page 30
2014 Microchip Technology Inc.
MCP25625
4.0
REGISTER MAP
reading and writing of data. Some specific control and
STATUS registers allow individual bit modification
using the SPI Bit Modify command. The registers that
allow this command are shown as shaded locations in
Table 4-1. A summary of the MCP25625 control
registers is shown in Table 4-2.
The register map for the MCP25625 is shown in
Table 4-1. Address locations for each register are
determined by using the column (higher-order four
bits) and row (lower-order four bits) values. The registers have been arranged to optimize the sequential
TABLE 4-1:
CAN CONTROLLER REGISTER MAP (Note 1)
Higher-Order Address Bits
Lower
Address
Bits
0000 xxxx
0001 xxxx
0010 xxxx
0011 xxxx
0100 xxxx
0101 xxxx
0110 xxxx
0111 xxxx
0000
RXF0SIDH
RXF3SIDH
RXM0SIDH
TXB0CTRL
TXB1CTRL
TXB2CTRL
RXB0CTRL
RXB1CTRL
0001
RXF0SIDL
RXF3SIDL
RXM0SIDL
TXB0SIDH
TXB1SIDH
TXB2SIDH
RXB0SIDH
RXB1SIDH
0010
RXF0EID8
RXF3EID8
RXM0EID8
TXB0SIDL
TXB1SIDL
TXB2SIDL
RXB0SIDL
RXB1SIDL
0011
RXF0EID0
RXF3EID0
RXM0EID0
TXB0EID8
TXB1EID8
TXB2EID8
RXB0EID8
RXB1EID8
0100
RXF1SIDH
RXF4SIDH
RXM1SIDH
TXB0EID0
TXB1EID0
TXB2EID0
RXB0EID0
RXB1EID0
0101
RXF1SIDL
RXF4SIDL
RXM1SIDL
TXB0DLC
TXB1DLC
TXB2DLC
RXB0DLC
RXB1DLC
0110
RXF1EID8
RXF4EID8
RXM1EID8
TXB0D0
TXB1D0
TXB2D0
RXB0D0
RXB1D0
0111
RXF1EID0
RXF4EID0
RXM1EID0
TXB0D1
TXB1D1
TXB2D1
RXB0D1
RXB1D1
1000
RXF2SIDH
RXF5SIDH
CNF3
TXB0D2
TXB1D2
TXB2D2
RXB0D2
RXB1D2
1001
RXF2SIDL
RXF5SIDL
CNF2
TXB0D3
TXB1D3
TXB2D3
RXB0D3
RXB1D3
1010
RXF2EID8
RXF5EID8
CNF1
TXB0D4
TXB1D4
TXB2D4
RXB0D4
RXB1D4
1011
RXF2EID0
RXF5EID0
CANINTE
TXB0D5
TXB1D5
TXB2D5
RXB0D5
RXB1D5
1100
BFPCTRL
TEC
CANINTF
TXB0D6
TXB1D6
TXB2D6
RXB0D6
RXB1D6
1101
TXRTSCTRL
REC
EFLG
TXB0D7
TXB1D7
TXB2D7
RXB0D7
RXB1D7
1110
CANSTAT
CANSTAT
CANSTAT
CANSTAT
CANSTAT
CANSTAT
CANSTAT
CANSTAT
CANCTRL
CANCTRL
CANCTRL
CANCTRL
CANCTRL
CANCTRL
CANCTRL
CANCTRL
1111
Note 1:
Shaded register locations indicate that these allow the user to manipulate individual bits using the Bit Modify command.
TABLE 4-2:
Register
Name
CONTROL REGISTER SUMMARY
Address
(Hex)
Bit 7
Bit 6
BFPCTRL
0C
—
—
B1BFS
B0BFS
B1BFE
B0BFE
TXRTSCTRL
0D
—
—
B2RTS
B1RTS
B0RTS
B2RTSM
CANSTAT
xE
OPMOD2
OPMOD1 OPMOD0
—
ICOD2
ICOD1
ICOD0
CANCTRL
xF
REQOP2
REQOP1
ABAT
OSM
CLKEN
CLKPRE1
TEC
1C
REC
1D
CNF3
28
SOF
WAKFIL
—
—
—
CNF2
29
BTLMODE
SAM
PHSEG12
PHSEG11
PHSEG10
CNF1
2A
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
CANINTE
2B
MERRE
WAKIE
ERRIE
TX2IE
TX1IE
TX0IE
Bit 5
Bit 4
REQOP0
Bit 3
Bit 2
Bit 0
POR/RST
Value
B1BFM
B0BFM
--00 0000
B1RTSM
B0RTSM
--xx x000
—
100- 000-
Bit 1
CLKPRE0 1110 0111
Transmit Error Counter (TEC)
0000 0000
Receive Error Counter (REC)
0000 0000
PHSEG22 PHSEG21 PHSEG20 00-- -000
PRSEG2
PRSEG1
PRSEG0
0000 0000
BRP1
BRP0
0000 0000
RX1IE
RX0IE
0000 0000
CANINTF
2C
MERRF
WAKIF
ERRIF
TX2IF
TX1IF
TX0IF
RX1IF
RX0IF
0000 0000
EFLG
2D
RX1OVR
RX0OVR
TXBO
TXEP
RXEP
TXWAR
RXWAR
EWARN
0000 0000
TXB0CTRL
30
—
ABTF
MLOA
TXERR
TXREQ
—
TXP1
TXP0
-000 0-00
TXB1CTRL
40
—
ABTF
MLOA
TXERR
TXREQ
—
TXP1
TXP0
-000 0-00
TXB2CTRL
50
—
ABTF
MLOA
TXERR
TXREQ
—
TXP1
TXP0
-000 0-00
RXB0CTRL
60
—
RXM1
RXM0
—
RXRTR
BUKT
BUKT1
FILHIT0
-00- 0000
RXB1CTRL
70
—
RXM1
RXM0
—
RXRTR
FILHIT2
FILHIT1
FILHIT0
-00- 0000
2014 Microchip Technology Inc.
DS20005282A-page 31
MCP25625
4.1
Message Transmit Registers
REGISTER 4-1:
TXBnCTRL – TRANSMIT BUFFER n CONTROL REGISTER
(ADDRESS: 30h, 40h, 50h)
U-0
R-0
R-0
R-0
R/W-0
U-0
R/W-0
R/W-0
—
ABTF
MLOA
TXERR
TXREQ
—
TXP1
TXP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
ABTF: Message Aborted Flag bit
1 = Message was aborted
0 = Message completed transmission successfully
bit 5
MLOA: Message Lost Arbitration bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4
TXERR: Transmission Error Detected bit
1 = A bus error occurred while the message was being transmitted
0 = No bus error occurred while the message was being transmitted
bit 3
TXREQ: Message Transmit Request bit
1 = Buffer is currently pending transmission (MCU sets this bit to request message be transmitted –
bit is automatically cleared when the message is sent)
0 = Buffer is not currently pending transmission (MCU can clear this bit to request a message abort)
bit 2
Unimplemented: Read as ‘0’
bit 1-0
TXP<1:0>: Transmit Buffer Priority bits
11 = Highest Message Priority
10 = High Intermediate Message Priority
01 = Low Intermediate Message Priority
00 = Lowest Message Priority
DS20005282A-page 32
2014 Microchip Technology Inc.
MCP25625
REGISTER 4-2:
TXRTSCTRL – TXnRTS PIN CONTROL AND STATUS REGISTER
(ADDRESS: 0Dh)
U-0
U-0
R-x
R-x
R-x
R/W-0
R/W-0
R/W-0
—
—
B2RTS
B1RTS
B0RTS
B2RTSM
B1RTSM
B0RTSM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
B2RTS: TX2RTS Pin State bit
- Reads state of TX2RTS pin when in Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
bit 4
B1RTS: TX1RTX Pin State bit
- Reads state of TX1RTS pin when in Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
bit 3
B0RTS: TX0RTS Pin State bit
- Reads state of TX0RTS pin when in Digital Input mode
- Reads as ‘0’ when pin is in ‘Request-to-Send’ mode
bit 2
B2RTSM: TX2RTS Pin mode bit
1 = Pin is used to request message transmission of TXB2 buffer (on falling edge)
0 = Digital input
bit 1
B1RTSM: TX1RTS Pin mode bit
1 = Pin is used to request message transmission of TXB1 buffer (on falling edge)
0 = Digital input
bit 0
B0RTSM: TX0RTS Pin mode bit
1 = Pin is used to request message transmission of TXB0 buffer (on falling edge)
0 = Digital input
REGISTER 4-3:
TXBnSIDH – TRANSMIT BUFFER n STANDARD IDENTIFIER HIGH
(ADDRESS: 31h, 41h, 51h)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
SID<10:3>: Standard Identifier bits
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MCP25625
REGISTER 4-4:
TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER LOW
(ADDRESS: 32h, 42h, 52h)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
SID<2:0>: Standard Identifier bits
bit 4
Unimplemented: Reads as ‘0’
bit 3
EXIDE: Extended Identifier Enable bit
1 = Message will transmit extended identifier
0 = Message will transmit standard identifier
bit 2
Unimplemented: Reads as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
REGISTER 4-5:
x = Bit is unknown
TXBnEID8 – TRANSMIT BUFFER n EXTENDED IDENTIFIER HIGH
(ADDRESS: 33h, 43h, 53h)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
EID<15:8>: Extended Identifier bits
REGISTER 4-6:
TXBnEID0 – TRANSMIT BUFFER n EXTENDED IDENTIFIER LOW
(ADDRESS: 34h, 44h, 54h)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
EID<7:0>: Extended Identifier bits
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MCP25625
REGISTER 4-7:
TXBnDLC - TRANSMIT BUFFER n DATA LENGTH CODE
(ADDRESS: 35h, 45h, 55h)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
RTR
—
—
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Reads as ‘0’
bit 6
RTR: Remote Transmission Request bit
1 = Transmitted Message will be a Remote Transmit Request
0 = Transmitted Message will be a Data Frame
bit 5-4
Unimplemented: Reads as ‘0’
bit 3-0
DLC<3:0>: Data Length Code bits
Sets the number of data bytes to be transmitted (0 to 8 bytes) (1)
Note 1:
It is possible to set the DLC to a value greater than eight, however only eight bytes are transmitted.
REGISTER 4-8:
TXBnDm – TRANSMIT BUFFER n DATA BYTE m
(ADDRESS: 36h - 3Dh, 46h - 4Dh, 56h - 5Dh)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
TXBnDm7
TXBnDm6
TXBnDm5
TXBnDm4
TXBnDm3
TXBnDm2
TXBnDm1
TXBnDm0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
TXBnDm<7:0>: Transmit Buffer n Data Field Bytes m
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DS20005282A-page 35
MCP25625
4.2
Message Receive Registers
REGISTER 4-9:
RXB0CTRL – RECEIVE BUFFER 0 CONTROL (ADDRESS: 60h)
U-0
R/W-0
R/W-0
U-0
R-0
R/W-0
R-0
R-0
—
RXM1
RXM0
—
RXRTR
BUKT
BUKT1
FILHIT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-5
RXM<1:0>: Receive Buffer Operating mode bits
11 = Turn mask/filters off; receive any message
10 = Receive only valid messages with extended identifiers that meet filter criteria
01 = Receive only valid messages with standard identifiers that meet filter criteria. Extended ID filter
registers RXFnEID8 and RXFnEID0 are ignored for the messages with standard IDs.
00 = Receive all valid messages using either standard or extended identifiers that meet filter criteria.
Extended ID filter registers RXFnEID8 and RXFnEID0 are applied to first two bytes of data in
the messages with standard IDs.
bit 4
Unimplemented: Read as ‘0’
bit 3
RXRTR: Received Remote Transfer Request bit
1 = Remote Transfer Request Received
0 = No Remote Transfer Request Received
bit 2
BUKT: Rollover Enable bit
1 = RXB0 message will rollover and be written to RXB1 if RXB0 is full
0 = Rollover disabled
bit 1
BUKT1: Read-only Copy of BUKT bit (used internally by the MCP25625)
bit 0
FILHIT0: Filter Hit bit – indicates which acceptance filter enabled reception of message(1)
1 = Acceptance Filter 1 (RXF1)
0 = Acceptance Filter 0 (RXF0)
Note 1:
If a rollover from RXB0 to RXB1 occurs, the FILHIT bit will reflect the filter that accepted the message that
rolled over.
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MCP25625
REGISTER 4-10:
RXB1CTRL – RECEIVE BUFFER 1 CONTROL (ADDRESS: 70h)
U-0
R/W-0
R/W-0
U-0
R-0
R-0
R-0
R-0
—
RXM1
RXM0
—
RXRTR
FILHIT2
FILHIT1
FILHIT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-5
RXM<1:0>: Receive Buffer Operating mode bits
11 = Turn mask/filters off; receive any message
10 = Receive only valid messages with extended identifiers that meet filter criteria
01 = Receive only valid messages with standard identifiers that meet filter criteria
00 = Receive all valid messages using either standard or extended identifiers that meet filter criteria
bit 4
Unimplemented: Read as ‘0’
bit 3
RXRTR: Received Remote Transfer Request bit
1 = Remote Transfer Request Received
0 = No Remote Transfer Request Received
bit 2-0
FILHIT<2:0>: Filter Hit bits – indicates which acceptance filter enabled reception of message
101 = Acceptance Filter 5 (RXF5)
100 = Acceptance Filter 4 (RXF4)
011 = Acceptance Filter 3 (RXF3)
010 = Acceptance Filter 2 (RXF2)
001 = Acceptance Filter 1 (RXF1) (Only if BUKT bit set in RXB0CTRL)
000 = Acceptance Filter 0 (RXF0) (Only if BUKT bit set in RXB0CTRL)
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MCP25625
REGISTER 4-11:
BFPCTRL – RXnBF PIN CONTROL AND STATUS (ADDRESS: 0Ch)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
B1BFS
B0BFS
B1BFE
B0BFE
B1BFM
B0BFM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5
B1BFS: RX1BF Pin State bit (Digital Output mode only)
- Reads as ‘0’ when RX1BF is configured as interrupt pin
bit 4
B0BFS: RX0BF Pin State bit (Digital Output mode only)
- Reads as ‘0’ when RX0BF is configured as interrupt pin
bit 3
B1BFE: RX1BF Pin Function Enable bit
1 = Pin function enabled, operation mode determined by B1BFM bit
0 = Pin function disabled, pin goes to high-impedance state
bit 2
B0BFE: RX0BF Pin Function Enable bit
1 = Pin function enabled, operation mode determined by B0BFM bit
0 = Pin function disabled, pin goes to high-impedance state
bit 1
B1BFM: RX1BF Pin Operation mode bit
1 = Pin is used as interrupt when valid message loaded into RXB1
0 = Digital Output mode
bit 0
B0BFM: RX0BF Pin Operation mode bit
1 = Pin is used as interrupt when valid message loaded into RXB0
0 = Digital Output mode
DS20005282A-page 38
x = Bit is unknown
2014 Microchip Technology Inc.
MCP25625
REGISTER 4-12:
RXBnSIDH – RECEIVE BUFFER n STANDARD IDENTIFIER HIGH
(ADDRESS: 61h, 71h)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
SID<10:3>: Standard Identifier bits
These bits contain the eight Most Significant bits of the Standard Identifier for the received message.
REGISTER 4-13:
RXBnSIDL – RECEIVE BUFFER n STANDARD IDENTIFIER LOW
(ADDRESS: 62h, 72h)
R-x
R-x
R-x
R-x
R-x
U-0
R-x
R-x
SID2
SID1
SID0
SRR
IDE
—
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
SID<2:0>: Standard Identifier bits
These bits contain the three Least Significant bits of the Standard Identifier for the received message.
bit 4
SRR: Standard Frame Remote Transmit Request bit (valid only if IDE bit = ‘0’)
1 = Standard Frame Remote Transmit Request Received
0 = Standard Data Frame Received
bit 3
IDE: Extended Identifier Flag bit
This bit indicates whether the received message was a Standard or an Extended Frame
1 = Received message was an Extended Frame
0 = Received message was a Standard Frame
bit 2
Unimplemented: Reads as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
These bits contain the two Most Significant bits of the Extended Identifier for the received message.
2014 Microchip Technology Inc.
DS20005282A-page 39
MCP25625
REGISTER 4-14:
RXBnEID8 – RECEIVE BUFFER n EXTENDED IDENTIFIER HIGH
(ADDRESS: 63h, 73h)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
EID<15:8>: Extended Identifier bits
These bits hold bits 15 through 8 of the Extended Identifier for the received message.
REGISTER 4-15:
RXBnEID0 – RECEIVE BUFFER n EXTENDED IDENTIFIER LOW
(ADDRESS: 64h, 74h)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
EID<7:0>: Extended Identifier bits
These bits hold the Least Significant eight bits of the Extended Identifier for the received message.
REGISTER 4-16:
RXBnDLC – RECEIVE BUFFER n DATA LENGTH CODE (ADDRESS: 65h, 75h)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
—
RTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Reads as ‘0’
bit 6
RTR: Extended Frame Remote Transmission Request bit (valid only when IDE bit in RXBnSID register
is 1)
1 = Extended Frame Remote Transmit Request Received
0 = Extended Data Frame Received
bit 5
RB1: Reserved Bit 1
bit 4
RB0: Reserved Bit 0
bit 3-0
DLC<3:0>: Data Length Code bits
Indicates number of data bytes that were received
DS20005282A-page 40
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MCP25625
REGISTER 4-17:
RXBnDM – RECEIVE BUFFER n DATA BYTE M (ADDRESS: 66h - 6Dh, 76h - 7Dh)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
RBnD7
RBnD6
RBnD5
RBnD4
RBnD3
RBnD2
RBnD1
RBnD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
4.3
x = Bit is unknown
RBnD<7:0>: Receive Buffer n Data Field Bytes m
Eight bytes containing the data bytes for the received message.
Acceptance Filter Registers
REGISTER 4-18:
RXFnSIDH – FILTER n STANDARD IDENTIFIER HIGH
(ADDRESS: 00h, 04h, 08h, 10h, 14h, 18h) (Note 1)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
SID<10:3>: Standard Identifier Filter bits
These bits hold the filter bits to be applied to bits <10:3> of the Standard Identifier portion of a received
message.
The mask and filter registers read all '0' when in any mode, except Configuration mode.
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MCP25625
REGISTER 4-19:
RXFnSIDL – FILTER n STANDARD IDENTIFIER LOW
(ADDRESS: 01h, 05h, 09h, 11h, 15h, 19h)(Note 1)
R/W-x
R/W-x
R/W-x
U-0
R/W-x
U-0
R/W-x
R/W-x
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
SID<2:0>: Standard Identifier Filter bits
These bits hold the filter bits to be applied to bits <2:0> of the Standard Identifier portion of a received
message.
bit 4
Unimplemented: Reads as ‘0’
bit 3
EXIDE: Extended Identifier Enable bit
1 = Filter is applied only to Extended Frames
0 = Filter is applied only to Standard Frames
bit 2
Unimplemented: Reads as ‘0’
bit 1-0
EID<17:16>: Extended Identifier Filter bits
These bits hold the filter bits to be applied to bits <17:16> of the Extended Identifier portion of a
received message.
Note 1:
The mask and filter registers read all '0' when in any mode, except Configuration mode.
REGISTER 4-20:
RXFnEID8 – FILTER n EXTENDED IDENTIFIER HIGH
(ADDRESS: 02h, 06h, 0Ah, 12h, 16h, 1Ah)(Note 1)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
EID<15:8>: Extended Identifier bits
These bits hold the filter bits to be applied to bits <15:8> of the Extended Identifier portion of a received
message or to byte 0 in received data if corresponding RXM = 00 and EXIDE = 0.
The mask and filter registers read all ‘0’ when in any mode, except Configuration mode.
DS20005282A-page 42
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MCP25625
REGISTER 4-21:
RXFnEID0 – FILTER n EXTENDED IDENTIFIER LOW
(ADDRESS: 03h, 07h, 0Bh, 13h, 17h, 1Bh)(Note 1)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
EID<7:0>: Extended Identifier bits
These bits hold the filter bits to be applied to bits <7:0> of the Extended Identifier portion of a received
message or to byte 1 in received data if corresponding RXM = 00 and EXIDE = 0.
The mask and filter registers read all ‘0’ when in any mode, except Configuration mode.
REGISTER 4-22:
RXMnSIDH – MASK n STANDARD IDENTIFIER HIGH
(ADDRESS: 20h, 24h)(Note 1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
SID<10:3>: Standard Identifier Mask bits
These bits hold the mask bits to be applied to bits <10:3> of the Standard Identifier portion of a received
message.
The mask and filter registers read all ‘0’ when in any mode, except Configuration mode.
2014 Microchip Technology Inc.
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MCP25625
REGISTER 4-23:
RXMnSIDL – MASK n STANDARD IDENTIFIER LOW
(ADDRESS: 21h, 25h)(Note 1)
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
SID2
SID1
SID0
—
—
—
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
SID<2:0>: Standard Identifier Mask bits
These bits hold the mask bits to be applied to bits<2:0> of the Standard Identifier portion of a received
message.
bit 4-2
Unimplemented: Reads as ‘0’
bit 1-0
EID<17:16>: Extended Identifier Mask bits
These bits hold the mask bits to be applied to bits <17:16> of the Extended Identifier portion of a
received message.
Note 1:
The mask and filter registers read all ‘0’ when in any mode, except Configuration mode.
REGISTER 4-24:
RXMnEID8 – MASK n EXTENDED IDENTIFIER HIGH
(ADDRESS: 22h, 26h)(Note 1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
EID<15:8>: Extended Identifier bits
These bits hold the filter bits to be applied to bits <15:8> of the Extended Identifier portion of a received
message. If corresponding RXM = 00 and EXIDE = 0, these bits are applied to byte 0 in received data.
The mask and filter registers read all ‘0’ when in any mode, except Configuration mode.
DS20005282A-page 44
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MCP25625
REGISTER 4-25:
RXMnEID0 – MASK n EXTENDED IDENTIFIER LOW
(ADDRESS: 23h, 27h)(Note 1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
EID<7:0>: Extended Identifier Mask bits
These bits hold the filter bits to be applied to bits <7:0> of the Extended Identifier portion of a received
message. If corresponding RXM = 00 and EXIDE = 0, these bits are applied to byte 1 in received data.
Note 1:
4.4
x = Bit is unknown
The mask and filter registers read all '0' when in any mode, except Configuration mode.
Bit Time Configuration Registers
REGISTER 4-26:
CNF1 – CONFIGURATION 1 (ADDRESS: 2Ah)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
SJW<1:0>: Synchronization Jump Width Length bits
11 = Length = 4 x TQ
10 = Length = 3 x TQ
01 = Length = 2 x TQ
00 = Length = 1 x TQ
bit 5-0
BRP<5:0>: Baud Rate Prescaler bits
TQ = 2 x (BRP + 1)/FOSC
2014 Microchip Technology Inc.
x = Bit is unknown
DS20005282A-page 45
MCP25625
REGISTER 4-27:
CNF2 – CONFIGURATION 1 (ADDRESS: 29h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BTLMODE
SAM
PHSEG12
PHSEG11
PHSEG10
PRSEG2
PRSEG1
PRSEG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
BTLMODE: PS2 Bit Time Length bit
1 = Length of PS2 determined by PHSEG2<2:0> bits of CNF3
0 = Length of PS2 is the greater of PS1 and IPT (2 TQ)
bit 6
SAM: Sample Point Configuration bit
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 5-3
PHSEG1<2:0>: PS1 Length bits
(PHSEG1 + 1) x TQ
bit 2-0
PRSEG<2:0>: Propagation Segment Length bits
(PRSEG + 1) x TQ
REGISTER 4-28:
CNF3 - CONFIGURATION 1 (ADDRESS: 28h)
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
SOF
WAKFIL
—
—
—
PHSEG22
PHSEG21
PHSEG20
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SOF: Start-of-Frame Signal bit
If in CANCTRL Register, CLKEN = 1:
1 = CLKOUT pin enabled for SOF signal
0 = CLKOUT pin enabled for clockout function
If CANCTRL Register, CLKEN = 0, Bit is don’t care.
bit 6
WAKFIL: Wake-up Filter bit
1 = Wake-up filter enabled
0 = Wake-up filter disabled
bit 5-3
Unimplemented: Reads as ‘0’
bit 2-0
PHSEG2<2:0>: PS2 Length bits
(PHSEG2 + 1) x TQ
Minimum valid setting for PS2 is 2 TQ
DS20005282A-page 46
x = Bit is unknown
2014 Microchip Technology Inc.
MCP25625
4.5
Error Detection Registers
REGISTER 4-29:
TEC – TRANSMIT ERROR COUNTER (ADDRESS: 1Ch)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
TEC<7:0>: Transmit Error Count bits
REGISTER 4-30:
REC – RECEIVER ERROR COUNTER (ADDRESS: 1Dh)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
REC<7:0>: Receive Error Count bits
2014 Microchip Technology Inc.
DS20005282A-page 47
MCP25625
REGISTER 4-31:
EFLG – ERROR FLAG (ADDRESS: 2Dh)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
RX1OVR
RX0OVR
TXBO
TXEP
RXEP
TXWAR
RXWAR
EWARN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RX1OVR: Receive Buffer 1 Overflow Flag bit
- Set when a valid message is received for RXB1 and RX1IF bit in the CANINTF register is 1
- Must be reset by MCU
bit 6
RX0OVR: Receive Buffer 0 Overflow Flag bit
- Set when a valid message is received for RXB0 and CANINTF.RX0IF bit in the CANINTF register is 1
- Must be reset by MCU
bit 5
TXBO: Bus-Off Error Flag bit
- Bit set when TEC reaches 255
- Reset after a successful bus recovery sequence
bit 4
TXEP: Transmit Error-Passive Flag bit
- Set when TEC is equal to or greater than 128
- Reset when TEC is less than 128
bit 3
RXEP: Receive Error-Passive Flag bit
- Set when REC is equal to or greater than 128
- Reset when REC is less than 128
bit 2
TXWAR: Transmit Error Warning Flag bit
- Set when TEC is equal to or greater than 96
- Reset when TEC is less than 96
bit 1
RXWAR: Receive Error Warning Flag bit
- Set when REC is equal to or greater than 96
- Reset when REC is less than 96
bit 0
EWARN: Error Warning Flag bit
- Set when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)
- Reset when both REC and TEC are less than 96
DS20005282A-page 48
2014 Microchip Technology Inc.
MCP25625
4.6
Interrupt Registers
.
REGISTER 4-32:
CANINTE – INTERRUPT ENABLE (ADDRESS: 2Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MERRE
WAKIE
ERRIE
TX2IE
TX1IE
TX0IE
RX1IE
RX0IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
MERRE: Message Error Interrupt Enable bit
1 = Interrupt on error during message reception or transmission
0 = Disabled
bit 6
WAKIE: Wake-up Interrupt Enable bit
1 = Interrupt on CAN bus activity
0 = Disabled
bit 5
ERRIE: Error Interrupt Enable bit (multiple sources in the EFLG register)
1 = Interrupt on EFLG error condition change
0 = Disabled
bit 4
TX2IE: Transmit Buffer 2 Empty Interrupt Enable bit
1 = Interrupt on TXB2 becoming empty
0 = Disabled
bit 3
TX1IE: Transmit Buffer 1 Empty Interrupt Enable bit
1 = Interrupt on TXB1 becoming empty
0 = Disabled
bit 2
TX0IE: Transmit Buffer 0 Empty Interrupt Enable bit
1 = Interrupt on TXB0 becoming empty
0 = Disabled
bit 1
RX1IE: Receive Buffer 1 Full Interrupt Enable bit
1 = Interrupt when message received in RXB1
0 = Disabled
bit 0
RX0IE: Receive Buffer 0 Full Interrupt Enable bit
1 = Interrupt when message received in RXB0
0 = Disabled
2014 Microchip Technology Inc.
x = Bit is unknown
DS20005282A-page 49
MCP25625
REGISTER 4-33:
CANINTF – INTERRUPT FLAG (ADDRESS: 2Ch)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MERRF
WAKIF
ERRIF
TX2IF
TX1IF
TX0IF
RX1IF
RX0IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
MERRF: Message Error Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 6
WAKIF: Wake-up Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 5
ERRIF: Error Interrupt Flag bit (multiple sources in the EFLG register)
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 4
TX2IF: Transmit Buffer 2 Empty Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 3
TX1IF: Transmit Buffer 1 Empty Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 2
TX0IF: Transmit Buffer 0 Empty Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 1
RX1IF: Receive Buffer 1 Full Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
bit 0
RX0IF: Receive Buffer 0 Full Interrupt Flag bit
1 = Interrupt pending (must be cleared by MCU to reset interrupt condition)
0 = No interrupt pending
DS20005282A-page 50
2014 Microchip Technology Inc.
MCP25625
4.7
CAN Control Register
REGISTER 4-34:
CANCTRL – CAN CONTROL REGISTER (ADDRESS: XFh)
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
REQOP2
REQOP1
REQOP0
ABAT
OSM
CLKEN
CLKPRE1
CLKPRE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
REQOP<2:0>: Request Operation mode bits
000 = Set Normal Operation mode
001 = Set Sleep mode
010 = Set Loopback mode
011 = Set Listen-Only mode
100 = Set Configuration mode
All other values for REQOP bits are invalid and should not be used. On power-up, REQOP = b’111’
bit 4
ABAT: Abort All Pending Transmissions bit
1 = Request abort of all pending transmit buffers
0 = Terminate request to abort all transmissions
bit 3
OSM: One-Shot mode bit
1 = Enabled. Message will only attempt to transmit one time
0 = Disabled. Messages will reattempt transmission, if required
bit 2
CLKEN: CLKOUT Pin Enable bit
1 = CLKOUT pin enabled
0 = CLKOUT pin disabled (Pin is in high-impedance state)
bit 1-0
CLKPRE<1:0>: CLKOUT Pin Prescaler bits
00 = FCLKOUT = System Clock/1
01 = FCLKOUT = System Clock/2
10 = FCLKOUT = System Clock/4
11 = FCLKOUT = System Clock/8
2014 Microchip Technology Inc.
DS20005282A-page 51
MCP25625
REGISTER 4-35:
CANSTAT – CAN STATUS REGISTER (ADDRESS: XEh)
R-1
R-0
R-0
U-0
R-0
R-0
R-0
U-0
OPMOD2
OPMOD1
OPMOD0
—
ICOD2
ICOD1
ICOD0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
OPMOD<2:0>: Operation mode bits
000 = Device is in the Normal Operation mode
001 = Device is in Sleep mode
010 = Device is in Loopback mode
011 = Device is in Listen-Only mode
100 = Device is in Configuration mode
bit 4
Unimplemented: Read as ‘0’
bit 3-1
ICOD<2:0>: Interrupt Flag Code bits
000 = No Interrupt
001 = Error Interrupt
010 = Wake-up Interrupt
011 = TXB0 Interrupt
100 = TXB1 Interrupt
101 = TXB2 Interrupt
110 = RXB0 Interrupt
111 = RXB1 Interrupt
bit 0
Unimplemented: Read as ‘0’
DS20005282A-page 52
x = Bit is unknown
2014 Microchip Technology Inc.
MCP25625
5.0
SPI INTERFACE
The MCP25625 is designed to interface directly with
the Serial Peripheral Interface (SPI) port available on
many microcontrollers and supports Mode 0,0 and
Mode 1,1.
Commands and data are sent to the device via the SI
pin, with data being clocked in on the rising edge of
SCK. Data is driven out by the MCP25625 (on the SO
line) on the falling edge of SCK. The CS pin must be
held low while any operation is performed.
TABLE 5-1:
Table 5-1 shows the instruction bytes for all operations.
Refer to Figures 5-10 and 5-11 for detailed input and
output timing diagrams for both Mode 0,0 and Mode
1,1 operation.
Note 1: The MCP25625 expects the first byte
to
be
the
after
lowering
CS
instruction/command byte. This implies
that CS must be raised and then lowered
again to invoke another command.
SPI INSTRUCTION SET
Instruction Name
Instruction Format
Description
RESET
1100 0000
Resets internal registers to default state, set Configuration mode.
READ
0000 0011
Read data from register beginning at selected address.
READ RX BUFFER
1001 0nm0
When reading a receive buffer, reduces the overhead of a normal
Read command by placing the Address Pointer at one of four
locations, as indicated by ‘n,m’. (Note 1)
WRITE
0000 0010
Write data to register beginning at selected address.
LOAD TX BUFFER
0100 0abc
When loading a transmit buffer, reduces the overhead of a normal
Write command by placing the Address Pointer at one of six
locations as indicated by ‘a,b,c’.
RTS
(Message
Request-To-Send)
1000 0nnn
Instructs controller to begin message transmission sequence for
any of the transmit buffers.
1000 0nnn
Request-to-send for TXB2
Request-to-send for TXBO
Request-to-send for TXB1
READ STATUS
1010 0000
Quick polling command that reads several Status bits for transmit
and receive functions.
RX STATUS
1011 0000
Quick polling command that indicates filter match and message
type (standard, extended and/or remote) of received message.
BIT MODIFY
0000 0101
Allows the user to set or clear individual bits in a particular
register. (Note 2)
Note 1:
2:
5.1
The associated RX flag bit (RXnIF bits in the CANINTF register) will be cleared after bringing CS high.
Not all registers can be bit-modified with this command. Executing this command on registers that are not
bit-modifiable will force the mask to FFh. See the register map in Section 4.0 “Register Map” for a list of
the registers that apply.
RESET Instruction
The RESET instruction can be used to re-initialize the
internal registers of the MCP25625 and set Configuration mode. This command provides the same functionality, via the SPI interface, as the RESET pin.
The RESET instruction is a single-byte instruction that
requires selecting the device by pulling CS low,
sending the instruction byte and then raising CS. It is
highly recommended that the Reset command be sent
(or the RESET pin be lowered) as part of the power-on
initialization sequence.
2014 Microchip Technology Inc.
5.2
READ Instruction
The READ instruction is started by lowering the CS pin.
The READ instruction is then sent to the MCP25625
followed by the 8-bit address (A7 through A0). Next, the
data stored in the register at the selected address will
be shifted out on the SO pin.
The internal Address Pointer is automatically
incremented to the next address once each byte of
data is shifted out. Therefore, it is possible to read the
next consecutive register address by continuing to provide clock pulses. Any number of consecutive register
locations can be read sequentially using this method.
The read operation is terminated by raising the CS pin
(Figure 5-2).
DS20005282A-page 53
MCP25625
5.3
READ RX BUFFER Instruction
5.7
READ STATUS Instruction
The READ RX BUFFER instruction (Figure 5-3) provides a means to quickly address a receive buffer for
reading. This instruction reduces the SPI overhead by
one byte, the address byte. The command byte actually
has four possible values that determine the Address
Pointer location. Once the command byte is sent, the
controller clocks out the data at the address location
the same as the READ instruction (i.e., sequential reads
are possible). This instruction further reduces the SPI
overhead by automatically clearing the associated
receive flag (RXnIF bit in the CANINTF register) when
CS is raised at the end of the command.
The READ STATUS instruction allows single instruction
access to some of the often used Status bits for
message reception and transmission.
5.4
Each Status bit returned in this command may also be
read by using the standard Read command with the
appropriate register address.
WRITE Instruction
The WRITE instruction is started by lowering the CS
pin. The WRITE instruction is then sent to the
MCP25625 followed by the address and at least one
byte of data.
It is possible to write to sequential registers by
continuing to clock in data bytes, as long as CS is held
low. Data will actually be written to the register on the
rising edge of the SCK line for the D0 bit. If the CS line
is brought high before eight bits are loaded, the write
will be aborted for that data byte and previous bytes in
the command will have been written. Refer to the timing
diagram in Figure 5-4 for a more detailed illustration of
the byte write sequence.
5.5
LOAD TX BUFFER Instruction
The LOAD TX BUFFER instruction (Figure 5-5) eliminates the 8-bit address required by a normal Write
command. The 8-bit instruction sets the Address
Pointer to one of six addresses to quickly write to a
transmit buffer that points to the “ID” or “data” address
of any of the three transmit buffers.
5.6
REQUEST-TO-SEND (RTS)
Instruction
The RTS command can be used to initiate message
transmission for one or more of the transmit buffers.
The MCP25625 is selected by lowering the CS pin. The
RTS command byte is then sent. Shown in Figure 5-6,
the last three bits of this command indicate which
transmit buffer(s) are enabled to send.
This command will set the TXREQ bit in the TxBnCTRL
register for the respective buffer(s). Any or all of the last
three bits can be set in a single command. If the RTS
command is sent with nnn = 000, the command will be
ignored.
DS20005282A-page 54
The MCP25625 is selected by lowering the CS pin and
the Read Status command byte, shown in Figure 5-8, is
sent to the MCP25625. Once the command byte is sent,
the MCP25625 will return eight bits of data that contain
the status.
If additional clocks are sent after the first eight bits are
transmitted, the MCP25625 will continue to output the
Status bits as long as the CS pin is held low and clocks
are provided on SCK.
5.8
RX STATUS Instruction
The RX STATUS instruction (Figure 5-9) is used to
quickly determine which filter matched the message
and message type (standard, extended, remote). After
the command byte is sent, the controller will return
eight bits of data that contain the status data. If more
clocks are sent after the eight bits are transmitted, the
controller will continue to output the same Status bits as
long as the CS pin stays low and clocks are provided.
5.9
BIT MODIFY Instruction
The BIT MODIFY instruction provides a means for setting or clearing individual bits in specific STATUS and
control registers. This command is not available for all
registers. See Section 4.0 “Register Map” to
determine which registers allow the use of this
command.
Note:
Executing the Bit Modify command on
registers that are not bit-modifiable will
force the mask to FFh. This will allow bytewrites to the registers, not bit modify.
The part is selected by lowering the CS pin and the Bit
Modify command byte is then sent to the MCP25625.
The command is followed by the address of the
register, the mask byte and finally the data byte.
The mask byte determines which bits in the register will
be allowed to change. A ‘1’ in the mask byte will allow
a bit in the register to change, while a ‘0’ will not (see
Figure 5-1).
The data byte determines what value the modified bits
in the register will be changed to. A ‘1’ in the data byte
will set the bit and a ‘0’ will clear the bit, provided that
the mask for that bit is set to a ‘1’ (see Figure 5-7).
2014 Microchip Technology Inc.
MCP25625
FIGURE 5-1:
BIT MODIFY
Mask byte
0 0 1 1 0 1 0 1
Data byte
X X 1 0 X 0 X 1
Previous
Register
Contents
0 1 0 1 0 0 0 1
Resulting
Register
Contents
0 1 1 0 0 0 0 1
FIGURE 5-2:
READ INSTRUCTION
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
20 21 22 23
SCK
Instruction
0
SI
0
0
0
Address Byte
0
0
1
A7
1
6
5
4
3
2
1
A0
Don’t Care
Data Out
High-Impedance
7
SO
FIGURE 5-3:
6
n m
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
SCK
Instruction
1
4
3
2
1
0
READ RX BUFFER INSTRUCTION
CS
SI
5
0
0
1
n
0
m 0
Data Out
High-Impedance
7
SO
FIGURE 5-4:
Don’t Care
6
5
4
3
2
1
0
Address Points to
Address
0 0 Receive Buffer 0,
Start at RXB0SIDH
0x61
0 1 Receive Buffer 0,
Start at RXB0D0
0x66
1 0 Receive Buffer 1,
Start at RXB1SIDH
0x71
1 1 Receive Buffer 1,
Start at RXB1D0
0x76
BYTE WRITE INSTRUCTION
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
0
0
0
0
1
0
A7
6
5
4
3
2
Data Byte
1
A0
7
6
5
4
3
2
1
0
High-Impedance
SO
2014 Microchip Technology Inc.
DS20005282A-page 55
MCP25625
FIGURE 5-5:
LOAD TX BUFFER
a b c
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
Data In
Instruction
SI
0
1
0
0
0
a
b
c
7
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 5-6:
Address Points to
Addr
0 0 0 TX buffer 0, Start at
TXB0SIDH
0x31
0 0 1 TX buffer 0, Start at
TXB0D0
0x36
0 1 0 TX buffer 1, Start at
TXB1SIDH
0x41
0 1 1 TX buffer 1, Start at
TXB1D0
0x46
1 0 0 TX buffer 2, Start at
TXB2SIDH
0x51
1 0 1 TX buffer 2, Start at
TXB2D0
0x56
REQUEST-TO-SEND (RTS) INSTRUCTION
CS
0
1
2
3
4
5
6
7
0
T2
T1
T0
SCK
Instruction
1
SI
0
0
0
High-Impedance
SO
FIGURE 5-7:
BIT MODIFY INSTRUCTION
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
Address Byte
Mask Byte
Data Byte
0 0 0 0 0 1 0 1 A7 6 5 4 3 2 1 A0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
High-Impedance
SO
Note:
Not all registers can be accessed with this command. See the register map for a list of the
registers that apply.
DS20005282A-page 56
2014 Microchip Technology Inc.
MCP25625
FIGURE 5-8:
READ STATUS INSTRUCTION
CS
0
1
2
3
4
5
6
7
0
0
0
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
1
0
1
0
0
Don’t Care
Repeat
Data Out
Data Out
High-Impedance
7
SO
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RX0IF (CANINTF register)
RX1IF (CANINTFL register)
TXREQ (TXB0CNTRL register)
TX0IF (CANINTF register)
TXREQ (TXB1CNTRL register)
TX1IF (CANINTF register)
TXREQ (TXB2CNTRL register)
TX2IF (CANINTF register)
FIGURE 5-9:
RX STATUS INSTRUCTION
CS
0
1
2
3
4
5
6
7
0
0
0
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
1
0
1
1
0
Repeat
Data Out
Data Out
High-Impedance
7
SO
Received Message
Don’t Care
3
5
4
3
2
1
0
Msg Type Received
7
6
5
4
3
7
6
0
0 No RX message
0 0 Standard data frame
0 0 0 RXF0
0
1 Message in RXB0
0 1 Standard remote frame
0 0 1 RXF1
1
0 Message in RXB1
1 0 Extended data frame
0 1 0 RXF2
1
1 Messages in both buffers*
1 1 Extended remote frame
0 1 1 RXF3
The extended ID bit is mapped to
bit 4. The RTR bit is mapped to bit
3.
1 0 0 RXF4
CANINTF.RXnIF bits are mapped to
bits 7 and 6.
4
6
* Buffer 0 has higher priority, therefore, RXB0 status is
reflected in bits 4:0.
2014 Microchip Technology Inc.
2
1 0
2
1
0
Filter Match
1 0 1 RXF5
1 1 0 RXF0 (rollover to RXB1)
1 1 1 RXF1 (rollover to RXB1)
DS20005282A-page 57
MCP25625
FIGURE 5-10:
SPI INPUT TIMING
3
CS
11
Mode 1,1
SCK
6
1
7
10
2
Mode 0,0
4
5
SI
MSB in
LSB in
High-Impedance
SO
FIGURE 5-11:
SPI OUTPUT TIMING
CS
SCK
8
2
9
Mode 1,1
Mode 0,0
12
13
SO
SI
DS20005282A-page 58
MSB out
14
LSB out
Don’t Care
2014 Microchip Technology Inc.
MCP25625
6.0
CAN TRANSCEIVER
The CAN transceiver is a differential, high-speed, faulttolerant interface to the CAN physical bus. It is fully
compatible with the ISO-11898-2 and ISO-11898-5
standards. It operates at speeds of up to 1 Mb/s.
The CAN transceiver meets the stringent automotive
EMC and ESD requirements.
Figure 6-1 illustrates the block diagram of the CAN
transceiver.
The CAN transceiver converts the digital TXCAN signal
generated by the CAN controller to signals suitable for
transmission over the physical CAN bus (differential
output). It also translates the differential CAN bus voltage to the RXCAN input signal of the CAN controller.
FIGURE 6-1:
CAN TRANSCEIVER BLOCK DIAGRAM
VIO
VDDA
Digital I/O
Supply
Thermal
Protection
POR
UVLO
VIO
TXD
Permanent
Dominant Detect
CANH
Driver
and
Slope Control
VIO
STBY
CANL
Mode
Control
VSS
Wake-up
Filter
RXD
CANH
LP_RX
CANL
Receiver
CANH
HS_RX
CANL
2014 Microchip Technology Inc.
DS20005282A-page 59
MCP25625
6.1
Transmitter Function
The CAN bus has two states: Dominant and
Recessive. A Dominant state occurs when the
differential voltage between CANH and CANL is
greater than VDIFF(D)(I). A Recessive state occurs
when the differential voltage is less than VDIFF(R)(I).
The Dominant and Recessive states correspond to the
Low and High state of the TXD input pin, respectively.
However, a Dominant state initiated by another CAN
node will override a Recessive state on the CAN bus.
6.2
Receiver Function
In Normal mode, the RXD output pin reflects the differential bus voltage between CANH and CANL. The Low
and High states of the RXD output pin correspond to the
Dominant and Recessive states of the CAN bus,
respectively.
6.3
Internal Protection
CANH and CANL are protected against battery shortcircuits and electrical transients that can occur on the
CAN bus. This feature prevents destruction of the
transmitter output stage during such a Fault condition.
The device is further protected from excessive current
loading by thermal shutdown circuitry that disables the
output drivers when the junction temperature exceeds
a nominal limit of +175°C. All other parts of the chip
remain operational, and the chip temperature is lowered due to the decreased power dissipation in the
transmitter outputs. This protection is essential to
protect against bus line short-circuit-induced damage.
6.4
Permanent Dominant Detection
The CAN transceiver device prevents two conditions:
• Permanent dominant condition on TXD
• Permanent dominant condition on the bus
In Normal mode, if the CAN transceiver detects an
extended Low state on the TXD input, it will disable the
CANH and CANL output drivers in order to prevent the
corruption of data on the CAN bus. The drivers will
remain disabled until TXD goes High.
In Standby mode, if the CAN transceiver detects an
extended dominant condition on the bus, it will set the
RXD pin to Recessive state. This allows the attached
controller to go to Low-Power mode until the dominant
issue is corrected. RXD is latched High until a
Recessive state is detected on the bus, and the
wake-up function is enabled again.
6.5
Power-On Reset (POR) and
Undervoltage Detection
The MCP25625 has undervoltage detection on both
supply pins: VDDA and VIO. Typical undervoltage
thresholds are 1.2V for VIO and 4V for VDDA.
When the device is powered on, CANH and CANL
remain in a high-impedance state until both VDDA and
VIO exceed their undervoltage levels. In addition,
CANH and CANL will remain in a high-impedance state
if TXD is Low when both undervoltage thresholds are
reached. CANH and CANL will become active only
after TXD is asserted High. Once powered on, CANH
and CANL will enter a high-impedance state if the voltage level at VDDA drops below the undervoltage level,
providing voltage brown-out protection during normal
operation.
In Normal mode, the receiver output is forced to
Recessive state during an undervoltage condition on
VDDA. In Standby mode, the low-power receiver is only
enabled when both VDDA and VIO supply voltages rise
above their respective undervoltage thresholds. Once
these threshold voltages are reached, the low-power
receiver is no longer controlled by the POR comparator
and remains operational down to about 2.5V on the
VDDA supply. The CAN transceiver transfers data to the
RXD pin down to 1V on the VIO supply.
6.6
6.6.1
Pin Description
TRANSMITTER DATA
INPUT PIN (TXD)
The CAN transceiver drives the differential output pins
CANH and CANL according to TXD. It is connected to
the TXCAN pin of the CAN controller. When TXD is Low,
CANH and CANL are in the Dominant state. When TXD
is High, CANH and CANL are in the Recessive state,
provided that another CAN node is not driving the CAN
bus with a Dominant state. TXD is connected to an
internal pull-up resistor (nominal 33 k) to VIO.
6.6.2
GROUND SUPPLY PIN (VSS)
Ground supply pin.
6.6.3
SUPPLY VOLTAGE PIN (VDDA)
Positive supply voltage pin. Supplies transmitter and
receiver, including the wake-up receiver.
Both conditions have a time-out of 1.25 ms (typical).
This implies a maximum bit time of 69.44 µs
(14.4 kHz), allowing up to 18 consecutive dominant bits
on the bus.
DS20005282A-page 60
2014 Microchip Technology Inc.
MCP25625
6.6.4
RECEIVER DATA
OUTPUT PIN (RXD)
RXD is a CMOS-compatible output that drives High or
Low depending on the differential signals on the CANH
and CANL pins, and is usually connected to the
receiver data input of the CAN controller device. RXD is
High when the CAN bus is Recessive, and Low in the
Dominant state. RXD is supplied by VIO.
6.6.5
VIO PIN
Supply for digital I/O pins of the CAN transceiver.
6.6.6
CAN LOW PIN (CANL)
The CANL output drives the Low side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANL disconnects from the
bus when VDDA is not powered.
6.6.7
CAN HIGH PIN (CANH)
The CANH output drives the high-side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANH disconnects from the
bus when VDDA is not powered.
6.6.8
STANDBY MODE INPUT PIN (STBY)
This pin selects between Normal or Standby mode of
the CAN transceiver. In Standby mode, the transmitter
and the high-speed receiver are turned off, only the low
power receiver and wake-up filter are active. STBY is
connected to an internal MOS pull-up resistor to VIO.
The value of the MOS pull-up resistor depends on the
supply voltage. Typical values are 660 k for 5V,
1.1 M for 3.3V and 4.4 M for 1.8V
6.6.9
EXPOSED THERMAL PAD (EP)
It is recommended to connect this pad to VSS to
enhance electromagnetic immunity and thermal
resistance.
2014 Microchip Technology Inc.
DS20005282A-page 61
MCP25625
NOTES:
DS20005282A-page 62
2014 Microchip Technology Inc.
MCP25625
7.0
ELECTRICAL
CHARACTERISTICS
7.1
Absolute Maximum Ratings†
VDD.............................................................................................................................................................................7.0V
VDDA ...........................................................................................................................................................................7.0V
VIO ..............................................................................................................................................................................7.0V
DC Voltage at CANH, CANL ........................................................................................................................ -58V to +58V
DC Voltage at TXD, RXD, STBY w.r.t VSS ............................................................................................-0.3V to VIO + 0.3V
DC Voltage at all other I/O w.r.t GND ................................................................................................-0.3V to VDD + 0.3V
Transient Voltage on CANH, CANL (ISO-7637) (Figure 7-5) ................................................................... -150V to +100V
Storage temperature ...............................................................................................................................-55°C to +150°C
Operating ambient temperature ..............................................................................................................-40°C to +125°C
Virtual Junction Temperature, TVJ (IEC60747-1) ....................................................................................-40°C to +150°C
Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C
ESD protection on CANH and CANL pins (IEC 61000-4-2)..................................................................................... ±8 kV
ESD protection on CANH and CANL pins (IEC 801; Human Body Model).............................................................. ±8 kV
ESD protection on all other pins (IEC 801; Human Body Model)............................................................................. ±4 kV
ESD protection on all pins (IEC 801; Machine Model) ............................................................................................±300V
ESD protection on all pins (IEC 801; Charge Device Model)..................................................................................±750V
† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2014 Microchip Technology Inc.
DS20005282A-page 63
MCP25625
7.2
CAN Controller Characteristics
TABLE 7-1:
DC CHARACTERISTICS
Electrical Characteristics:
Sym.
Characteristic
Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V
Min.
Max.
Units
VDD
Supply Voltage
2.7
5.5
V
VRET
Register Retention Voltage
2.4
—
V
2
VDD + 1
V
0.7 VDD
Conditions
High-Level Input Voltage
VIH
RXCAN
SCK, CS, SI, TXnRTS Pins
VDD + 1
V
OSC1
0.85
VDD
VDD
V
RESET
0.85 VDD
VDD
V
RXCAN, TXnRTS Pins
-0.3
0.15 VDD
V
SCK, CS, SI
-0.3
0.4 VDD
V
OSC1
VSS
0.3 VDD
V
RESET
VSS
0.15 VDD
V
Low-Level Input Voltage
VIL
Low-Level Output Voltage
TXCAN
—
0.6
V
IOL = +6.0 mA, VDD = 4.5V
RXnBF Pins
—
0.6
V
IOL = +8.5 mA, VDD = 4.5V
SO, CLKOUT
—
0.6
V
IOL = +2.1 mA, VDD = 4.5V
INT
—
0.6
V
IOL = +1.6 mA, VDD = 4.5V
TXCAN, RXnBF Pins
VDD – 0.7
—
V
IOH = -3.0 mA, VDD = 4.5V
SO, CLKOUT
VDD – 0.5
—
V
IOH = -400 µA, VDD = 4.5V
INT
VDD – 0.7
—
V
IOH = -1.0 mA, VDD = 4.5V
All I/O except OSC1 and
TXnRTS pins
-1
+1
µA
CS = RESET = VDD,
VIN = VSS to VDD
OSC1 Pin
-5
+5
µA
CINT
Internal Capacitance
(All Inputs and Outputs)
—
7
pF
TAMB = +25°C, fC = 1.0 MHz,
VDD = 0V (Note 1)
IDD
Operating Current
—
10
mA
VDD = 5.5V, FOSC = 25 MHz,
FCLK = 1 MHz, SO = Open
IDDS
Standby Current (Sleep mode)
—
8
µA
CS, TXnRTS = VDD, Inputs tied
to VDD or VSS, -40°C TO +125°C
VOL
High-Level Output Voltage
VOH
Input Leakage Current
ILI
Note 1:
Characterized, not 100% tested.
TABLE 7-2:
OSCILLATOR TIMING CHARACTERISTICS
Oscillator Timing Characteristics (Note 1)
Sym.
Characteristic
Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V
Min.
Max.
Units
FOSC
Clock-In Frequency
1
25
MHz
TOSC
Clock-In Period
40
1000
ns
0.45
0.55
—
tDUTY
Note 1:
Duty Cycle (External Clock Input)
Conditions
TOSH/(TOSH + TOSL)
Characterized, not 100% tested.
DS20005282A-page 64
2014 Microchip Technology Inc.
MCP25625
TABLE 7-3:
CAN INTERFACE AC CHARACTERISTICS
CAN Interface AC Characteristics
Sym.
tWF
Characteristic
Wake-up Noise Filter
TABLE 7-4:
Min.
Max.
Units
100
—
ns
Sym.
Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V
Characteristic
Min.
Max.
Units
2
—
µs
RESET Pin Low Time
TABLE 7-5:
Conditions
CLKOUT PIN AC CHARACTERISTICS
CLKOUT Pin AC/DC Characteristics
Param.
No.
Conditions
RESET AC CHARACTERISTICS
RESET AC Characteristics
tRL
Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V
Sym.
Characteristic
Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V
Min.
Max.
Units
—
ns
TOSC = 40 ns (Note 1)
tHCLKOUT
CLKOUT Pin High Time
10
Conditions
tLCLKOUT
CLKOUT Pin Low Time
10
—
ns
TOSC = 40 ns (Note 1)
tRCLKOUT
CLKOUT Pin Rise Time
—
10
ns
Measured from 0.3 VDD
to 0.7 VDD (Note 1)
tFCLKOUT
CLKOUT Pin Fall Time
—
10
ns
Measured from 0.7 VDD
to 0.3 VDD (Note 1)
tDCLKOUT
CLOCKOUT Propagation
Delay
—
100
ns
(Note 1)
15
tHSOF
Start-Of-Frame High Time
—
2 TOSC
ns
(Note 1)
16
tDSOF
Start-Of-Frame Propagation
Delay
—
2 TOSC + 0.5 TQ
ns
Measured from CAN bit sample
point. Device is a receiver.
BRP<5:0> = 0 in CNF1 the
register (Note 2)
Note 1:
2:
All CLKOUT mode functionality and output frequency is tested at device frequency limits, however, CLKOUT
prescaler is set to divide by one. Characterized, not 100% tested.
Characterized, not 100% tested.
TABLE 7-6:
SPI INTERFACE AC CHARACTERISTICS
SPI Interface AC Characteristics
Param.
No.
Sym.
Characteristic
Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V
Min.
Max.
Units
Conditions
FCLK
Clock Frequency
—
10
MHz
1
tCSS
CS Setup Time
50
—
ns
2
tCSH
CS Hold Time
50
—
ns
3
tCSD
CS Disable Time
50
—
ns
4
tSU
Data Setup Time
10
—
ns
5
tHD
Data Hold Time
10
—
ns
6
tR
CLK Rise Time
—
2
µs
(Note 1)
7
tF
CLK Fall Time
—
2
µs
(Note 1)
8
tHI
Clock High Time
45
—
ns
9
tLO
Clock Low Time
45
—
ns
10
tCLD
Clock Delay Time
50
—
ns
tCLE
Clock Enable Time
50
—
ns
11
Note 1:
Characterized, not 100% tested.
2014 Microchip Technology Inc.
DS20005282A-page 65
MCP25625
TABLE 7-6:
SPI INTERFACE AC CHARACTERISTICS (CONTINUED)
SPI Interface AC Characteristics
Extended (E): TAMB = -40°C to +125°C; VDD = 2.7V to 5.5V
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
12
tV
Output Valid from Clock Low
—
45
ns
13
tHO
Output Hold Time
0
—
ns
tDIS
Output Disable Time
—
100
ns
14
Note 1:
Conditions
Characterized, not 100% tested.
FIGURE 7-1:
START-OF-FRAME PIN AC CHARACTERISTICS
RXCAN
16
sample point
15
7.3
CAN Transceiver Characteristics
7.3.1
DC CHARACTERISTICS
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C; VDDA = 4.5V to 5.5V, VIO = 2.7V to 5.5V,
RL = 60; unless otherwise specified.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Conditions
Voltage Range
VDDA
4.5
—
5.5
Supply Current
IDD
—
5
10
—
45
70
IDDS
—
5
15
µA
High Level of the POR
Comparator
VPORH
3.8
—
4.3
V
Low Level of the POR
Comparator
VPORL
3.4
—
4.0
V
Hysteresis of POR Comparator
VPORD
0.3
—
0.8
V
VIO
2.7
—
5.5
V
IIO
—
4
30
µA
—
85
500
IDDS
—
0.3
1
µA
(Note 1)
VUVD(IO)
—
1.2
—
V
(Note 1)
SUPPLY
VDDA Pin
Standby Current
mA
Recessive; VTXD = VDDA
Dominant; VTXD = 0V
Includes IIO
VIO Pin
Digital Supply Voltage Range
Supply Current on VIO
Standby Current
Undervoltage detection on VIO
Note 1:
2:
Recessive; VTXD = VIO
Dominant; VTXD = 0V
Characterized; not 100% tested.
-12V to 12V is ensured by characterization, tested from -2V to 7V.
DS20005282A-page 66
2014 Microchip Technology Inc.
MCP25625
7.3.1
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C; VDDA = 4.5V to 5.5V, VIO = 2.7V to 5.5V,
RL = 60; unless otherwise specified.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Conditions
BUS LINE (CANH; CANL) TRANSMITTER
CANH; CANL:
Recessive Bus Output Voltage
VO(R)
2.0
0.5VDDA
3.0
V
VTXD = VDDA; No load
CANH; CANL:
Bus Output Voltage in Standby
VO(S)
-0.1
0.0
+0.1
V
STBY = VTXD = VDDA; No load
Recessive Output Current
IO(R)
-5
—
+5
mA
VO(D)
2.75
3.50
4.50
V
0.50
1.50
2.25
CANH: Dominant
Output Voltage
CANL: Dominant
Output Voltage
-24V < VCAN < +24V
TXD = 0; RL = 50 to 65
RL = 50 to 65
Symmetry of Dominant
Output Voltage
(VDD – VCANH – VCANL)
VO(D)(M)
-400
0
+400
mV
Dominant: Differential
Output Voltage
VO(DIFF)
1.5
2.0
3.0
V
-120
0
12
mV
VTXD = VDDA
Figure 7-2, Figure 7-4
-500
0
50
mV
VTXD = VDDA, no load.
Figure 7-2, Figure 7-4
-120
85
—
mA
VTXD = VSS; VCANH = 0V;
CANL: floating
-100
—
—
mA
same as above, but
VDDA = 5V, TAMB = +25°C
(Note 1)
—
75
+120
mA
VTXD = VSS; VCANL = 18V;
CANH: floating
—
—
+100
mA
same as above, but
VDD=5V, TAMB = +25°C (Note 1)
-1.0
—
+0.5
V
-1.0
—
+0.4
0.9
—
VDDA
1.0
—
VDDA
Recessive:
Differential Output Voltage
CANH: Short Circuit
Output Current
IO(SC)
CANL: Short Circuit
Output Current
VTXD = VSS (Note 1)
VTXD = VSS; RL = 50 to 65
Figure 7-2, Figure 7-4
BUS LINE (CANH; CANL) RECEIVER
Recessive Differential
Input Voltage
Dominant Differential
Input Voltage
Note 1:
2:
VDIFF(R)(I)
VDIFF(D)(I)
Normal mode;
-12V < V(CANH, CANL) < +12V;
See Figure 7-6 (Note 2)
Standby mode;
-12V < V(CANH, CANL) < +12V;
See Figure 7-6 (Note 2)
V
Normal mode;
-12V < V(CANH, CANL) < +12V;
See Figure 7-6 (Note 2)
Standby mode;
-12V < V(CANH, CANL) < +12V;
See Figure 7-6 (Note 2)
Characterized; not 100% tested.
-12V to 12V is ensured by characterization, tested from -2V to 7V.
2014 Microchip Technology Inc.
DS20005282A-page 67
MCP25625
7.3.1
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C; VDDA = 4.5V to 5.5V, VIO = 2.7V to 5.5V,
RL = 60; unless otherwise specified.
Characteristic
Differential
Receiver Threshold
Sym.
Min.
Typ.
Max.
Units
VTH(DIFF)
0.5
0.7
0.9
V
0.4
—
1.15
Conditions
Normal mode;
-12V < V(CANH, CANL) < +12V;
See Figure 7-6 (Note 2)
Standby mode;
-12V < V(CANH, CANL) < +12V;
See Figure 7-6 (Note 2)
Differential
Input Hysteresis
VHYS(DIFF)
50
—
200
mV
Normal mode, see Figure 7-6,
(Note 1)
Common Mode
Input Resistance
RIN
10
—
30
k
(Note 1)
RIN(M)
-1
0
+1
%
VCANH = VCANL, (Note 1)
Differential Input
Resistance
RIN(DIFF)
10
—
100
k
(Note 1)
Common Mode
Input Capacitance
CIN(CM)
—
—
20
pF
VTXD = VDDA (Note 1)
Differential
Input Capacitance
CIN(DIFF)
—
—
10
ILI
-5
—
+5
µA
High-Level Input Voltage
VIH
0.7 VIO
—
VIO + 0.3
V
Low-Level Input Voltage
VIL
-0.3
—
0.3 VIO
V
Common Mode
Resistance Matching
CANH, CANL:
Input Leakage
VTXD = VDDA (Note 1)
VDDA = VTXD = VSTBY = 0V.
VIO = 0V, VCANH = VCANL = 5V.
DIGITAL INPUT PINS (TXD, STBY)
High-Level Input Current
IIH
-1
—
+1
µA
TXD: Low-Level Input Current
IIL(TXD)
-270
-150
-30
µA
STBY: Low-Level Input Current
IIL(STBY)
-30
—
-1
µA
High-Level Output Voltage
VOH
VIO - 0.4
—
—
V
IOH = -1 mA; typical -2 mA
Low-Level Output Voltage
VOL
—
—
0.4
V
IOL = 4 mA; typical 8 mA
TJ(SD)
165
175
185
°C
-12V < V(CANH, CANL) < +12V,
(Note 1)
TJ(HYST)
20
—
30
°C
-12V < V(CANH, CANL) < +12V,
(Note 1)
RECEIVE DATA (RXD) OUTPUT
THERMAL SHUTDOWN
Shutdown
Junction Temperature
Shutdown
Temperature Hysteresis
Note 1:
2:
Characterized; not 100% tested.
-12V to 12V is ensured by characterization, tested from -2V to 7V.
DS20005282A-page 68
2014 Microchip Technology Inc.
MCP25625
7.3.2
AC CHARACTERISTICS
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C; VDDA = 4.5V to 5.5V, VIO = 2.7V to 5.5V,
RL = 60; unless otherwise specified.
Param.
No.
Sym
1
tBIT
Bit Time
2
fBIT
Bit Frequency
3
tTXD-BUSON
4
5
6
tBUSOFF-RXD Delay Bus Recessive to RXD
7
Min
Typ
Max
Units
1
—
69.44
µs
14.4
—
1000
kHz
—
—
70
ns
tTXD-BUSOFF Delay TXD High to Bus Recessive
—
—
125
ns
tBUSON-RXD
—
—
70
ns
—
—
110
ns
—
—
125
ns
tTXD - RXD
Characteristic
Delay TXD Low to Bus Dominant
Delay Bus Dominant to RXD
Propagation Delay TXD to RXD
8
9
10
tFLTR(WAKE) Delay Bus Dominant to RXD
(Standby mode)
tWAKE
Delay Standby
to Normal mode
Conditions
Negative edge on TXD
—
—
235
0.5
1
4
µs
Positive edge on TXD
Standby mode
5
25
40
µs
Negative edge on STBY
11
tPDT
Permanent Dominant Detect Time
—
1.25
—
ms
TXD = 0V
12
tPDTR
Permanent Dominant Timer Reset
—
100
—
ns
The shortest recessive
pulse on TXD or CAN bus
to reset Permanent
Dominant Timer
2014 Microchip Technology Inc.
DS20005282A-page 69
MCP25625
FIGURE 7-2:
PHYSICAL BIT REPRESENTATION AND SIMPLIFIED BIAS IMPLEMENTATION
Normal Mode
Standby Mode
CANH, CANL
CANH
CANL
Recessive
Dominant
Recessive
Time
VDDA
CANH
Normal
VDDA/2
RXD
Standby
Mode
CANL
FIGURE 7-3:
TEST LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDDA/2
RL
CL
Pin
CL
Pin
RL = 464
CL = 50 pF
DS20005282A-page 70
for all digital pins
VSS
VSS
2014 Microchip Technology Inc.
MCP25625
FIGURE 7-4:
TEST CIRCUIT FOR ELECTRICAL CHARACTERISTICS
0.1 µF
VDDA
CANH
TXD
CAN
Transceiver
RL
100 pF
RXD
30 pF
CANL
STBY
GND
Note: VIO is connected to VDDA.
FIGURE 7-5:
TEST CIRCUIT FOR AUTOMOTIVE TRANSIENTS
CANH
TXD
RXD
CAN
Transceiver
Transient
Generator
RL
CANL
STBY
GND
500 pF
500 pF
Note: VIO is connected to VDDA.
The wave forms of the applied transients shall be in accordance
with ISO-7637, Part 1, test pulses 1, 2, 3a and 3b.
FIGURE 7-6:
HYSTERESIS OF THE RECEIVER
RXD (receive data
output voltage)
VOH
VDIFF (r)(i)
VDIFF (d)(i)
VOL
VDIFF (h)(i)
0.5
2014 Microchip Technology Inc.
VDIFF (V)
0.9
DS20005282A-page 71
MCP25625
FIGURE 7-7:
TIMING DIAGRAM FOR AC CHARACTERISTICS
VDDA
TXD (transmit data
input voltage)
0V
VDIFF (CANH,
CANL differential
voltage)
RXD (receive data
output voltage)
3
5
6
4
7
8
FIGURE 7-8:
TIMING DIAGRAM FOR WAKEUP FROM STANDBY
VSTBY
Input Voltage
VDDA
0V
VDDA/2
VCANH/VCANL
0
VTXD = VDDA
FIGURE 7-9:
10
PERMANENT DOMINANT TIMER RESET DETECT
Minimum pulse width until CAN bus goes to dominant after the falling edge
TXD
VDIFF (VCANH-VCANL)
Driver is off
11
DS20005282A-page 72
12
2014 Microchip Technology Inc.
MCP25625
7.4
Thermal Specifications
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
—
+125
C
Operating Temperature Range
TA
-40
—
+125
C
Storage Temperature Range
TA
-65
—
+150
C
Thermal Resistance, 28L-QFN 6x6
JA
—
32.8
—
C/W
Thermal Resistance, 28L-SSOP
JA
—
80
—
C/W
Thermal Package Resistances
2014 Microchip Technology Inc.
DS20005282A-page 73
MCP25625
7.5
Terms and Definitions
A number of terms are defined in ISO-11898 that are
used to describe the electrical characteristics of a CAN
transceiver device. These terms and definitions are
summarized in this section.
7.5.1
7.5.5
DIFFERENTIAL VOLTAGE, VDIFF
(OF CAN BUS)
Differential voltage of the two-wire CAN bus, value
VDIFF = VCANH – VCANL.
7.5.6
BUS VOLTAGE
INTERNAL CAPACITANCE, CIN
(OF A CAN NODE)
VCANL and VCANH denote the voltages of the bus line
wires CANL and CANH relative to ground of each
individual CAN node.
Capacitance seen between CANL (or CANH) and
ground during the Recessive state, when the CAN
node is disconnected from the bus (see Figure 7-10).
7.5.2
7.5.7
COMMON MODE BUS VOLTAGE
RANGE
Boundary voltage levels of VCANL and VCANH with
respect to ground, for which proper operation will occur,
if up to the maximum number of CAN nodes are
connected to the bus.
7.5.3
DIFFERENTIAL INTERNAL
CAPACITANCE, CDIFF
(OF A CAN NODE)
Capacitance seen between CANL and CANH during
the Recessive state, when the CAN node is
disconnected from the bus (see Figure 7-10).
7.5.4
DIFFERENTIAL INTERNAL
RESISTANCE, RDIFF
(OF A CAN NODE)
Resistance seen between CANL and CANH during the
Recessive state when the CAN node is disconnected
from the bus (see Figure 7-10).
DS20005282A-page 74
INTERNAL RESISTANCE, RIN
(OF A CAN NODE)
Resistance seen between CANL (or CANH) and
ground during the Recessive state, when the CAN
node is disconnected from the bus (see Figure 7-10).
FIGURE 7-10:
PHYSICAL LAYER
DEFINITIONS
ECU
RIN
CANL
RIN
CDIFF
RDIFF
CANH
CIN
CIN
GROUND
2014 Microchip Technology Inc.
MCP25625
NOTES:
2014 Microchip Technology Inc.
DS20005282A-page 75
MCP25625
8.0
PACKAGING INFORMATION
8.1
Package Marking Information
28-Lead QFN (6x6 mm)
PIN 1
XXXXXXXX
XXXXXXXX
YYWWNNN
28-Lead SSOP (5.30 mm)
Example
PIN 1
MCP25625
E/ML ^^
e3
1405256
Example
MCP25625
e3
E/SS ^^
1405256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005282A-page 76
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (e3)
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2014 Microchip Technology Inc.
MCP25625
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b
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2
1
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±
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
2014 Microchip Technology Inc.
DS20005282A-page 77
MCP25625
/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@
ZLWKPP&RQWDFW/HQJWK
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KWWSZZZPLFURFKLSFRPSDFNDJLQJ
DS20005282A-page 78
2014 Microchip Technology Inc.
MCP25625
/HDG3ODVWLF6KULQN6PDOO2XWOLQH66±PP%RG\>6623@
1RWH
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
D
N
E
E1
1 2
NOTE 1
b
e
c
A2
A
φ
A1
L
L1
8QLWV
'LPHQVLRQ/LPLWV
1XPEHURI3LQV
0,//,0(7(56
0,1
1
120
0$;
3LWFK
H
2YHUDOO+HLJKW
$
±
%6&
±
0ROGHG3DFNDJH7KLFNQHVV
$
6WDQGRII
$
±
±
2YHUDOO:LGWK
(
0ROGHG3DFNDJH:LGWK
(
2YHUDOO/HQJWK
'
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5()
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F
±
)RRW$QJOH
/HDG:LGWK
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±
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%
2014 Microchip Technology Inc.
DS20005282A-page 79
MCP25625
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005282A-page 80
2014 Microchip Technology Inc.
MCP25625
APPENDIX A:
REVISION HISTORY
Revision A (March 2014)
• Original Release of this Document.
2014 Microchip Technology Inc.
DS20005282A-page 77
MCP25625
NOTES:
DS20005282A-page 78
2014 Microchip Technology Inc.
MCP25625
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-X
/XX
Device
Temperature
Range
Package
Examples:
a)
b)
Device:
MCP25625: CAN Controller with Integrated Transceiver
MCP25625T: CAN Controller with Integrated Transceiver
Temperature
Range:
E
=
-40°C to +125°C (Extended)
Package:
ML = Plastic Quad Flat, No Lead Package - 6x6 mm
Body with 0.55 mm Contact Length, 28-lead
SS = Plastic Shrink Small Outline - 5.30 mm Body,
28-lead
2014 Microchip Technology Inc.
c)
d)
MCP25625-E/ML: Extended Temperature,
28LD 6x6 QFN package.
MCP25625T-E/ML:Tape and Reel,
Extended Temperature,
28LD 6x6 QFN package.
MCP25625-E/SS: Extended Temperature,
28LD SSOP package.
MCP25625T-E/SS:Tape and Reel,
Extended Temperature,
28LD SSOP package.
DS20005282A-page 79
MCP25625
NOTES:
DS20005282A-page 80
2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-63276-018-0
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2014 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20005282A-page 81
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
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Tel: 852-2401-1200
Fax: 852-2401-3431
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Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
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Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 678-957-9614
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Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
DS20005282A-page 82
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
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Tel: 86-28-8665-5511
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Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
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Tel: 86-755-8864-2200
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Tel: 86-27-5980-5300
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Tel: 86-29-8833-7252
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Tel: 91-11-4160-8631
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Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
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Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
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Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
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Netherlands - Drunen
Tel: 31-416-690399
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Malaysia - Penang
Tel: 60-4-227-8870
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Poland - Warsaw
Tel: 48-22-3325737
Philippines - Manila
Tel: 63-2-634-9065
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Singapore
Tel: 65-6334-8870
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Taiwan - Hsin Chu
Tel: 886-3-5778-366
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Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
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Tel: 44-118-921-5800
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Tel: 86-756-3210040
Fax: 86-756-3210049
03/13/14
2014 Microchip Technology Inc.