MTCH650/2 Programmable Voltage Boost with Built-in Level Shifters and Serial Interface with Output Enable MTCH652 Features: MTCH650 Features: • • • • • • • • • • • • • • • • • • FIGURE 1: 21 High Voltage I/O lines 1.8V to 5.5V Input Operating Range Low Quiescent Current: <200 µA Low Shutdown Current: 1.5 µA typical Up to 100 mA Output Current with 5 mA per OUTxx Channel • Output Enable (OE) Independent of SPI Interface • 3.6 to 18V External VPPIN Range Package Type: • 28-pin SOIC, SSOP • 28-pin UQFN (4x4) 28-PIN SOIC, SSOP DIAGRAM OUT03 1 28 OUT20(1)/LC(2) OUT02 2 27 OUT04 OUT01 3 26 OUT05 OUT00 4 25 OUT06 OUT19(1)/OUT18(2) 5 OUT07 OUT18(1)/OUT17(2) 6 24 23 OUT17(1)/OSCIN(2) OE 7 22 VDD 21 VSS LE 9 20 OUT08 8 MTCH650/2 • 19 High Voltage I/O Lines Built-in Boost Internal Switch 1.8V to 5.5V Input Operating Range Low Quiescent Current: <200 µA Low Shutdown Current: 1.5 µA, typical Up to 50 mA Output Current, at VIN = 3.6V and VOUT = 12V The Boost is Driven by an External PWM Allowing for Greater Boost Flexibility Selectable Output Voltage Range: 6V, 8V, 10V, 12V, 14V, 16V and 18V Selectable Current Limiting Selectable Soft Start High-Speed SPI Interface: - 1 MHz max. Output Enable (OE) Independent of SPI Interface Built-in Discharge Circuit VPP(2)/VPPIN(1) 10 19 CLK 11 18 OUT10 OUT16 DIN OUT09 12 17 OUT11 OUT15 13 16 OUT12 OUT14 14 15 OUT13 Note 1: MTCH650 2: MTCH652 2014 Microchip Technology Inc. Preliminary DS40001749A-page 1 MTCH650/2 28-PIN UQFN DIAGRAM 28 27 26 25 24 23 22 OUT06 OUT07 VPP(2)/VPPIN(1) VDD VSS OUT08 OUT09 FIGURE 2: OUT01 OUT00 Note 1: MTCH650 2: MTCH652 DS40001749A-page 2 1 2 3 4 5 6 7 MTCH650/2 OUT19(1)/OUT18(2) 8 OUT18(1)/OUT17(2) 9 OUT17(1)/OSCIN(2) 10 OE 11 LE 12 DIN 13 CLK 14 OUT05 OUT04 OUT20(1)/LC(2) OUT03 OUT02 Preliminary 21 OUT10 20 OUT11 19 OUT12 18 OUT13 17 OUT14 16 OUT15 15 OUT16 2014 Microchip Technology Inc. MTCH650/2 TABLE 1: I/O PIN FUNCTION TABLE FOR MTCH650 28-Pin SOIC/SSOP 28-Pin UQFN Description Vss 21 24 Electrical ground or GND VDD 22 25 Input Voltage Pin VPP — — Boost Voltage Output VPPIN 23 26 Boost Voltage Input LC — — Inductor Boost Connection OE 8 11 Digital Input (ST) LE 9 12 Digital Input (ST) DIN 10 13 Digital Input (ST) CLK 11 14 Digital Input (TTL) OSCIN — — Digital Input (TTL) OUT00 4 7 HV Analog Output OUT01 3 6 HV Analog Output OUT02 2 5 HV Analog Output OUT03 1 4 HV Analog Output OUT04 27 2 HV Analog Output OUT05 26 1 HV Analog Output OUT06 25 28 HV Analog Output OUT07 24 27 HV Analog Output OUT08 20 23 HV Analog Output OUT09 19 22 HV Analog Output OUT10 18 21 HV Analog Output OUT11 17 20 HV Analog Output OUT12 16 19 HV Analog Output OUT13 15 18 HV Analog Output OUT14 14 17 HV Analog Output OUT15 13 16 HV Analog Output OUT16 12 15 HV Analog Output OUT17 7 10 HV Analog Output OUT18 6 9 HV Analog Output OUT19 5 8 HV Analog Output OUT20 28 3 HV Analog Output INPUT VOLTAGE (VDD) OUTPUT ENABLE INPUT (OE) Connect the input voltage to VDD. This pin must be decoupled to GND with a recommended 1 µf minimum capacitor. When OE is set to logic ‘0’, all output latches (OUTxx) are GND. When OE is set to logic ‘1’, all output latches that are set to drive ‘1’ will output the boost voltage level. The OE state is ignored and all OUTxx are highimpedance (High Z) during shutdown or soft-start transient. BOOST VOLTAGE INPUT (VPPIN) Boost input voltage must be decoupled to GND with recommended 1 µf minimum capacitor. 2014 Microchip Technology Inc. Preliminary DS40001749A-page 3 MTCH650/2 LATCH ENABLE INPUT (LE) Latch Enable Input (LE) is the active-low latch input used for latching-in serial data. Serial data is ignored unless LE is logic ‘0’. After clocking serial data, the data is internally latched when LE changes from logic ‘0’ to logic ‘1’. SERIAL DATA INPUT (DIN) Serial data input. SERIAL DATA CLOCK INPUT (CLK) Serial data clock input. HV OUTPUT (OUTXX) High-voltage output pins. DS40001749A-page 4 Preliminary 2014 Microchip Technology Inc. MTCH650/2 TABLE 2: I/O PIN FUNCTION TABLE FOR MTCH652 28-Pin SOIC/SSOP 28-Pin UQFN Description Vss 21 24 Electrical ground or GND VDD 22 25 Input Voltage Pin VPP 23 26 Boost Voltage Output VPPIN — — Boost Voltage Input LC 28 3 Inductor Boost Connection OE 8 11 Digital Input (ST) LE 9 12 Digital Input (ST) DIN 10 13 Digital Input (ST) CLK 11 14 Digital Input (TTL) OSCIN 7 10 Digital Input (TTL) OUT00 4 7 HV Analog Output OUT01 3 6 HV Analog Output OUT02 2 5 HV Analog Output OUT03 1 4 HV Analog Output OUT04 27 2 HV Analog Output OUT05 26 1 HV Analog Output OUT06 25 28 HV Analog Output OUT07 24 27 HV Analog Output OUT08 20 23 HV Analog Output OUT09 19 22 HV Analog Output OUT10 18 21 HV Analog Output OUT11 17 20 HV Analog Output OUT12 16 19 HV Analog Output OUT13 15 18 HV Analog Output OUT14 14 17 HV Analog Output OUT15 13 16 HV Analog Output OUT16 12 15 HV Analog Output OUT17 6 9 HV Analog Output OUT18 5 8 HV Analog Output OUT19 — — HV Analog Output OUT20 — — HV Analog Output INPUT VOLTAGE (VDD) BOOST INDUCTOR INPUT (LC) Connect the input voltage to VDD. This pin must be decoupled to GND with a recommended 1 µf minimum capacitor. The Boost Inductor Input must be decoupled to GND on the VDD side with a recommended 1 µf minimum capacitor. BOOST VOLTAGE OUTPUT (VPP) Boost output voltage must be decoupled to GND with a recommended 1 µf minimum capacitor. 2014 Microchip Technology Inc. Preliminary DS40001749A-page 5 MTCH650/2 OUTPUT ENABLE INPUT (OE) When OE is set to logic ‘0’, all output latches (OUTxx) are GND. When OE is set to logic ‘1’, all output latches that are set to drive ‘1’ will output the boost voltage level. The OE state is ignored and all OUTxx are highimpedance (High Z) during shutdown or soft-start transient. LATCH ENABLE INPUT (LE) Latch Enable Input (LE) is the active-low latch input used for latching-in serial data. Serial data is ignored unless LE is logic ‘0’. After clocking serial data, the data is internally latched when LE changes from logic ‘0’ to logic ‘1’. SERIAL DATA INPUT (DIN) Serial data input. SERIAL DATA CLOCK INPUT (CLK) Serial data clock input. PWM INPUT (OSCIN) PWM input signal for boost. HV OUTPUT (OUTXX) High-voltage output pins. DS40001749A-page 6 Preliminary 2014 Microchip Technology Inc. MTCH650/2 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 8 2.0 Power-on Reset (POR) .............................................................................................................................................................. 9 3.0 Serial Interface........................................................................................................................................................................ 10 4.0 Voltage Boost Interface ........................................................................................................................................................... 13 5.0 Application Information ............................................................................................................................................................ 14 6.0 Application Example ................................................................................................................................................................ 16 7.0 Electrical Specifications ........................................................................................................................................................... 18 8.0 Typical Performance Curves ................................................................................................................................................... 24 9.0 Packaging Information ............................................................................................................................................................. 26 The Microchip Web Site....................................................................................................................................................................... 37 Customer Change Notification Service ................................................................................................................................................ 37 Customer Support ................................................................................................................................................................................ 37 Product Identification System ............................................................................................................................................................. 38 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected]. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2014 Microchip Technology Inc. Preliminary DS40001749A-page 7 MTCH650/2 1.0 DEVICE OVERVIEW FIGURE 1-2: MTCH652 is a compact boost converter, with up to 19 level shifters, which provides an easy-to-use solution for driving High Voltage (HV) outputs. MTCH650 is a line driver device, with 21 level shifters available. FUNCTIONAL BLOCK DIAGRAM FOR MTCH652 The devices contain a Configuration register (CONFIG) and a data (DATA) register. The CONFIG register can be adjusted using the SPI interface, allowing for voltage changes during application time. The CONFIG register sets the output voltage, the current limit and the Soft Start settings. The DATA register configures the 19/21 bit output mask for the HV output latches. The Output Enable (OE) allows for efficient cycling of the boost voltage on the HV output latches without the delay of setting HV output latches via the serial interface. The HV output latches are set to ‘0’ when Output Enable (OE) is ‘0’. The HV output latches are set to the output mask when OE is ‘1’. MTCH650/2 require only a 3-wire serial interface, latch enable (LE) and two capacitors. MTCH652 requires an additional PWM and a small inductor. The PWM is used to drive the boost and allows flexibility in duty cycle and frequency. The selectable internal Soft Start limits initial in-rush currents, preventing system brownouts. Note: While MTCH650 and MTCH652 are very similar, MTCH650 does not include a built-in boost circuit. MTCH650 will require an external boost voltage device, such as MCP16301 or the output of the MTCH652. FIGURE 1-1: DS40001749A-page 8 FUNCTIONAL BLOCK DIAGRAM FOR MTCH650 Preliminary 2014 Microchip Technology Inc. MTCH650/2 2.0 POWER-ON RESET (POR) The on-chip POR circuit holds the device in a Reset state until VDD has reached VPOR. The POR is not configurable. All latches are cleared when POR is active. When VDD is below VPOR, the internal shift register will reset to all ‘0’s. 2014 Microchip Technology Inc. Preliminary DS40001749A-page 9 MTCH650/2 3.0 SERIAL INTERFACE The serial interface allows configuration of MTCH650/ 2 during operation. The clock and serial data stream are used to configure a 3-byte wide shift register prior to latching the desired data using Latch Enable (LE) input. 3.1 Loading Data The shift register is three bytes wide and shifts data from right to left. Therefore, data must be entered in MSB first to LSB last sequence, starting with the leading dummy bits set to zero if necessary. The Data Word selects which HV outputs (OUTxx) are to be cycled with Output Enable (OE). The Configuration Word sets the shutdown state, boost voltage, current limit and other miscellaneous options. In addition, Latch Enable (LE) can serve as a chipselect. A high state on LE disables the input shift registers, allowing for sharing of the SPI bus. The shift register is written using a clock input, CLK, and a data input, DIN. Data is read on the falling CLK edge. The master loads DIN when CLK is high. The MTCH650 will latch DIN data value on the CLK falling edge. The contents of the shift register are then loaded into the latches using the latch enable input, LE. The LE signal is asynchronous to the clock. Data is latched on the rising edge of LE. The LE is also a chip-select. If LE is held high, then the device will not accept new serial data. The falling edge of LE re-enables data input and resets the shift register, allowing new data to be clocked-in. In User mode, latched values are held until overwritten by new data or a POR event occurs. See Figure 3-1 for details. FIGURE 3-1: 3.2 SERIAL TIMING INTERFACE Configuration Word 3.3 Data Word The Configuration Word is selected by setting the LSB of the data stream to ‘0’. In User mode, using the MTCH652, the output voltage and current limit of the boost circuit can be selected. The Data Word consists of three bytes of data which set the 21 output pins of the MTCH650, or 19 output pins of the MTCH652, low or high. The Data Word is selected by setting the LSB of the data stream to ‘1’. Complete Configuration Word documentation can be found in Register 3-1. Complete Data Word documentation can be found in Register 3-2. DS40001749A-page 10 Preliminary 2014 Microchip Technology Inc. MTCH650/2 REGISTER 3-1: CONFIGURATION WORD REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ILIMDIS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VCMPSEN SSDIS ILIM1 ILIM0 VOUT2 VOUT1 VOUT0 SELECT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-9 Unimplemented: Read as ‘0’ bit 8 ILIMDIS: Disable Current Limit bit(1) 0 = Current limiting enabled (normal operation) 1 = Current limiting disabled bit 7 VCMPSEN: Synchronize Boost Regulator Release to OSCIN bit(1) 0 = Synchronization disabled (normal operation). When target VPP is achieved, boost regulator switches off asynchronously to OSCIN 1 = Synchronization enabled. When target VPP is achieved, boost regulator switches off on rising edge of OSCIN. bit 6 SSDIS: Disable Soft Start bit(1) 0 = Soft Start enabled (normal operation) 1 = Soft Start disabled, part will start using the current limit set by ILIM<1:0> bit 5-4 ILIM<1:0>: Current Limit Select bit(1) 00 = 200 mA 01 = 600 mA 10 = 1A 11 = Over 1.5A bit 3-1 VOUT<2:0>: Boost Voltage Select bits MTCH652: 000 = Shutdown state, Outputs (OUTxx) High-Impedance 001 = 6V 010 = 8V 011 = 10V 100 = 12V 101 = 14V 110 = 16V 111 = 18V MTCH650: 000 = Shutdown state, Outputs (OUTxx) High-Impedance 001 to 111 = Normal mode Note 1: OUT19 and OUT20 only implement on MTCH650. 2014 Microchip Technology Inc. Preliminary DS40001749A-page 11 MTCH650/2 REGISTER 3-1: bit 0 CONFIGURATION WORD REGISTER SELECT: Select Configuration Word or Data Word bit 0 = Configuration Word selected 1 = Data Word selected Note 1: OUT19 and OUT20 only implement on MTCH650. REGISTER 3-2: DATA WORD REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OUTSEL20 OUTSEL19 OUTSEL18 OUTSEL17 OUTSEL16 OUTSEL15 bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OUTSEL14 OUTSEL13 OUTSEL12 OUTSEL11 OUTSEL10 OUTSEL9 OUTSEL8 OUTSEL7 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OUTSEL6 OUTSEL5 OUTSEL4 OUTSEL3 OUTSEL2 OUTSEL1 OUTSEL0 SELECT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-22 Unimplemented: Read as ‘0’ bit 21-1 OUTSEL<20:0>: Set Output Latches High or Low bits (1) 1 = OUT_nn set high 0 = OUT_nn set low bit 0 SELECT: Select Configuration Word or Data Word bit 0 = Configuration Word selected 1 = Data Word selected Note 1: x = Bit is unknown OUT19 and OUT20 are implemented only on MTCH650. DS40001749A-page 12 Preliminary 2014 Microchip Technology Inc. MTCH650/2 4.0 VOLTAGE BOOST INTERFACE MTCH652 includes a voltage boost circuit which generates selectable High Voltage (HV) from VDD using modulated input signal in combination with external inductance and capacitance. The switch and diode are built into the device. 4.1 4.1.1 Boost Connections INPUTS OSCIN – a modulated input signal typically derived from a PWM. The duty cycle range is typically from 60 to 90%. VOUT<2:0> – 3-bit output voltage-select settings. Refer to Register 3-1 for configuration details. ILIM<1:0> – 2-bit current-limit setting used to limit the maximum current the boost can draw to prevent brown-out of current-limited power supplies. Refer to Register 3-1 for configuration details. VPPIN – HV input on MTCH650. 4.1.2 OUTPUTS VPP – HV output of the boost circuit on MTCH652. LC – Connection for both external inductor and external capacitor for the boost circuit on MTCH652. 4.2 Boost Operation Under normal operation, OSCIN modulates the gate of the internal switching transistor to build up energy in the LC and raise VPP. The internal circuitry regulates the boost voltage based on the configuration for VOUT<2:0> and ILIM<1:0>. VOUT and ILIM can be changed by the user via the serial interface. 4.3 Soft Start The boost circuit is equipped with an automatic soft-start feature. This soft-start feature prevents a high initial in-rush current from pulling down the power supply, which will result in a brown-out condition. The current is limited to approximately 200 mA during the initial 16384 OSCIN cycles or about 16 ms with 1 MHz OSCIN frequency after enabling the boost circuit. After the soft start has timed-out, the current limit reverts to the value selected by the ILIM<1:0> setting. Disable soft start by setting SSDIS = 1. 4.4 VPP Discharge When the value of VOUT<2:0> is changed to a lower voltage and the circuit is active, the VPP discharge transistor is enabled until the lower new VOUT is reached. This quickly reduces VPP to the new value. If VOUT<2:0> is changed from a lower to higher voltage, VPP discharge has no effect. 2014 Microchip Technology Inc. Preliminary DS40001749A-page 13 MTCH650/2 5.0 APPLICATION INFORMATION TABLE 5-1: 5.1 Input Capacitor Selection Using an input bypass capacitor reduces peak current transients drawn from the input supply and also reduces switching noise generated by the boost. Typically, a ceramic low ESR X5R or X7R capacitor between 1 µF to 10 µF is acceptable. In applications that are extremely sensitive to high frequency noise, smaller caps with higher operational bandwidth may be placed in parallel with standard recommended values. In applications using much lower than an 1 MHz switching frequency, or in cases with >1A peak inductor currents, larger cap sizes may also be placed in parallel with the standard values. 5.2 Output Capacitor Selection The output capacitor helps to provide a stable output voltage during sudden load transients and reduces output voltage ripple. As with the input capacitor, X5R and X7R ceramic capacitors are well suited for this application. Typical values are 1 µF to 10 µF. Note: 5.3 Increasing the capacitance value will increase the rise and fall times when switching between boost voltages. Inductor Selection MTCH652 can be used with small surface mount inductors. Typical inductance values are 1 µH to 10 µH. Note: An inductance value of 2.2 µH is recommended for initial evaluation. Several parameters are used to select the correct inductor, maximum rated current, saturation current and copper resistance (ESR). The input current can be much higher than the output current using a boost converter device. A lower ESR value will yield a higher efficiency rate for the converter, which is a common trade-off in component size versus efficiency. EXAMPLES OF RECOMMENDED INDUCTORS Value (µH) DCR (typ.) ISAT (A) Size WxLxH (mm) (TDK) MLP2012S2R2M 2.2 0.23 0.8 1.25x2.0x1.0 (Taijo Yuden) CKP2012N2R2M-T 2.2 0.2 0.8 1.25x2.0x1.0 (Samsung) CIG21C2R2MNE 2.2 0.25 0.8 1.25x2.0x1.0 (Taiyo Yuden) BRC2012T1R0M 1 0.06 1.5 1.25x2.0x1.4 (Taiyo Yuden) BRC2012T1R5MD 1.5 0.09 1.2 1.25x2.0x1.4 (Taiyo Yuden) BRC2012T2R2MD 2.2 0.11 1.1 1.25x2.0x1.4 (TDK Corporation) MLP2012S1R0MT0S1 1 0.16 1 1.25x2.0x1 (TDK Corporation) MLP2012S2R2MT0S1 2.2 0.23 0.8 1.25x2.0x1 Part Number 5.4 PCB Layout Information Mindful layout techniques are important to any switching circuitry. When wiring high-current paths, short and wide traces should be used. It is important that the input and output capacitors be placed as close as possible to MTCH652 to minimize loop area. The HV outputs should be routed away from the switching node and switching current loop. When possible, ground planes and traces should be used to help shield the feedback signal and also minimize noise and magnetic interference. In many cases, MTCH650/2 are used in conjunction with sensitive sensing lines. The HV outputs from the MTCH650/2 should be shielded or routed away from these sense lines to reduce noise (see Figure 5-1 and Figure 5-2). The saturation current specifies a point at which the inductance has rolled off a percentage of the rated value. This can range from 20% to 40% reduction in inductance. As the inductance rolls off, the inductor current increases, as does the peak switch current. It is important to keep the inductance from rolling off too much, causing the switch current to reach the peak limit. Basic inductor selection is based on a DCR < 0.25 and ISAT > 1.5 x ILIM or 1.5 x IPK (L) (whichever is greater), where ILIM = selected current limit value and IPK (L) = Peak inductor current. Examples of recommended inductors are shown in Table 5-1. DS40001749A-page 14 Preliminay 2014 Microchip Technology Inc. MTCH650/2 FIGURE 5-1: MTCH652 SOIC AND SSOP RECOMMENDED LAYOUT FIGURE 5-2: MTCH652 UQFN RECOMMENDED LAYOUT 2014 Microchip Technology Inc. Preliminay DS40001749A-page 15 MTCH650/2 6.0 APPLICATION EXAMPLE MTCH650/2 are very simple to set up and use, only requiring configuration of a Configuration Word and a Data Word. The difference between MTCH650 and MTCH652 is the addition of the PWM input and the selectable options for VOUT and ILIM. Figure 6-1 shows a typical application using a PIC® microcontroller and MTCH652. FIGURE 6-1: TYPICAL APPLICATION PIC® MCU 6.1 MTCH650/2 Connections 6.2 The following pins are required to drive MTCH650/2 from the host side: • • • • • PWM – Output (MTCH652 only) OE – Output LE – Output SDO(1) – serial data output SCLK(1) – serial data clock output The following shows the basic operations for initialization addressed in additional individual notes within this section: 1. 2. Note 1: These pins can be from a standard MSSP module or bit-banged. 3. - DS40001749A-page 16 MTCH650/2 Initialization Preliminary On the host, I/O ports to be used for OE and LE functionality should be configured as outputs. Set OE low and set LE high. Configure the host SPI port for 1 MHz or equivalent bit-bang function. It is recommended that a function that takes the bit mask and sends it to MTCH650/2 be created. Example 6-1 shows such an example. Host sends command to configure the MTCH650/2 CONFIG Word to default settings: ILIMDIS = 0 – ILO Enabled VCMPSEN = 0 – Synchronization Disabled SSDID = 0 – Soft Start Enabled ILIM = 00 – ILIM = 200 mA VOUT = 000 – Boost Disabled 2014 Microchip Technology Inc. MTCH650/2 4. (MTCH652 only) Configure the host PWM to output on the correct I/O pin. It is recommended that PWM starts at a frequency of 500 kHz with a 70% duty cycle. It may be necessary to later adjust the parameters to optimize the efficiency and ripple. EXAMPLE 6-1: 6.5 For Low-Power or Shutdown modes, set VOUT<2:0> = 000. Turn off the PWM for the absolute minimum operating power mode. 6.6 BIT-BANG CODE void send MTCH65x (unsigned long data) { unsigned int x; MTCH65x_LE_LAT_CLR; // clear LE to start for (x=0; x<24; x++) { if (data&0x800000) { MTCH65x_DIN_LAT_SET; // bit is a 1 } else { MTCH65x_DIN_LAT_CLR; // bit is a 0 } MTCH65x_CLK_LAT_SET; MTCH65x_CLK_LAT_CLR; data <<= 1; // rotate in next bit } MTCH65x_LE_LAT_SET; //set LE latch in the data Low Power HV Level Shifters, DATA Latches and OE Control of the HV level shifters is accessed through the bits OUTSEL<20:0> in the Data Word. Only bits that are set in OUTSEL will have the boost voltage set on the HV level shifters when OE is asserted. All others will remain in a de-asserted state at VSS. When OE is de-asserted, all HV level shifters will be held at VSS. The user must be aware that MTCH652 has limited current drive. Driving all HV level shifters at the same time may cause an unintended drop in boost. Alternatives for higher drive are to lower the boost voltage or use MTCH650 with an external high-voltage supply. } 6.3 SPI Specifics MTCH650/2 serial interface uses the PIC MCU MSSP SPI defaults. The specifics are: • De-assert LE • The host changes the state of DIN when CLK is low, data is latched on a low-to-high transition of CLK on the MTCH650/2 • After clocking-in all serial data assert LE, this will latch the new data into the MTCH650/2 internal registers. 6.4 Setting the Boost Voltage The boost voltage is set with VOUT<2:0> in the Configuration Word. The rise and fall times for boost voltage changes are dependent on ILIM, the capacitor and on VPP. The user must ensure that, when changing boost voltages, the new VPP voltage has settled to the correct value. 2014 Microchip Technology Inc. Preliminary DS40001749A-page 17 MTCH650/2 7.0 ELECTRICAL SPECIFICATIONS 7.1 Absolute Maximum Ratings(†) Ambient temperature under bias........................................................................................................ -40°C to +85°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on LC, VPP, OUTxx ..................................................................................................................... -0.3V to 24V on VDD pin ................................................................................................................................ -0.3V to +6.0V on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V) Total power dissipation(1) UQFN ............................................................................. 2W at ambient TA = 25°C (-20 mW/C for TA > 25°C) SOIC.......................................................................................... 1.4W at TA = 25°C (-14 mW/C for TA > 25°C) Maximum current out of VSS pin ......................................................................................................................... 1.5A Maximum current into LC pin .............................................................................................................................. 1.5A Maximum current in/out of VPP/VPPIN pin ........................................................................................................... 1.5A Maximum current into VDD pin ....................................................................................................................... 250 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA Maximum output current sunk by any I/O pin................................................................................................... 25 mA Maximum output current sourced by any I/O pin ............................................................................................. 25 mA Maximum current sourced by analog outputs, -40°C < TA < +85°C for industrial ............................................ 25 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 7.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage MTCH650/2 VDDMIN ..................................................................................................................................... +1.8V VDDMAX .................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................... +85°C Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Table 7-6: “Thermal Characteristics” to calculate device specifications. DS40001749A-page 18 Preliminary 2014 Microchip Technology Inc. MTCH650/2 7.3 DC Characteristics TABLE 7-1: BASIC OPERATING CHARACTERISTICS DC Characteristics Sym. Standard Operating Conditions (unless otherwise stated) Characteristic Min. Typ† Max. Units Conditions VDD Supply Voltage 1.8 — 5.5 V IPD Standby Current — 2 TBD µA VDD = 3.6V IDD Supply Current(1) — 1.4 TBD mA ILIM = 00, VDD = 3.6, Boost to 18V, unloaded IDD Supply Current(1) — 0.85 TBD mA ILIM = 01, VDD = 3.6, Boost to 18V, unloaded IDD Supply Current(1) — 0.8 TBD mA ILIM = 10, VDD = 3.6, Boost to 18V, unloaded VPOR Power-on Reset Release Voltage 0.7 1.1 1.75 V Note 1: ILIM = 11, current strongly dependent on OSCIN frequency and duty cycle. TABLE 7-2: I/O CHARACTERISTICS DC Characteristics Sym. Standard Operating Conditions (unless otherwise stated) Min. Typ† Max. Units VIL Digital Input Low Voltage VSS — 0.2 VDD V VIH Digital Input High Voltage 0.8 VDD — VDD V IIL Digital Input Leakage Current — ±5 ±125 nA VOL Output Low Voltage — — 0.6 V IOL = 5 mA VOH Output High Voltage VPP – 0.7 — — V IOH = 5 mA 7.4 Characteristic Conditions 85°C; VSS VPIN VDD Analog and AC Characteristics TABLE 7-3: SERIAL INTERFACE TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Max. Units SI1 tch External CLK High Time 0.5 µs SI2 tcl External CLK Low Time 0.5 µs SI3 tcper External CLK Period 1 µs SI4 fc External CLK Frequency DC 1 MHz SI5 tds DIN Setup Time 10 ns SI6 tdh DIN Hold Time 10 ns SI7 tls LE Setup Time 10 ns SI8 tlh LE High Time 10 ns Note 1: See Figure 3-1 for the corresponding timing diagram. 2014 Microchip Technology Inc. Preliminary Conditions DS40001749A-page 19 MTCH650/2 TABLE 7-4: MTCH652 VOLTAGE BOOST AND TIMING AND ANALOG CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. VB1 — VB2 VB3 VB4 VB5 Sym. FOSC — VPP VRIPP ILIMIT IAVG Characteristic Min. Typ. Max. Units External OSCIN Frequency — — 2 MHz — — 90% — VDD V VOUT = 000 (boost disabled) Duty Cycle High Voltage Output Ripple Voltage Switch Current Limit(1) Average Output Current DS40001749A-page 20 VDD – 0.8 VDD – 0.3 Conditions 5.4 6 6.6 V VOUT = 001 7.2 8 8.8 V VOUT = 010 9.0 10 11.0 V VOUT = 011 10.8 12 13.2 V VOUT = 100 12.6 14 15.4 V VOUT = 101 14.4 16 17.6 V VOUT = 110 16.2 18 19.8 V VOUT = 111 — 40 — mVPP VDD = 3.6V, Boost to VPP = 18V, 1 µH inductor, 150 pF load, 1 µF VPP capacitor, ILIM = 00 — 75 — mVPP VDD = 3.6V, Boost to VPP = 18V, 1 µH inductor, 150 pF load, 1 µF VPP capacitor, ILIM = 01 — 85 — mVPP VDD = 3.6V, Boost to VPP = 18V, 1 µH inductor, 150 pF load, 1 µF VPP capacitor, ILIM = 10 — 0.15 0.3 A ILIM = 00 — 0.6 1 A ILIM = 01 — 1 1.5 A ILIM = 10 — — 1.6 A ILIM = 11, OSCIN/duty cycle Limited — 0.5 — mA Preliminary 2014 Microchip Technology Inc. MTCH650/2 TABLE 7-4: MTCH652 VOLTAGE BOOST AND TIMING AND ANALOG CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. VB9 Sym. Characteristic tresp Response Time Fall Time Note 1: 2: Min. Typ. Max. Units Conditions — 2.3 — ms Total for all channels; VPP = 18V, Cload = 15pF per channel, OE frequency = 1 MHZ, ILIM = 00, VDD = 3.6V Boost with 1 µH inductor to VPP = 18V, CVPP = 1uF, unloaded, FOSC = 1 MHz, (Note 2) — 400 — µs Total for all channels; VPP = 18V, Cload = 15pF per channel, OE frequency = 1 MHZ, ILIM = 01, VDD = 3.6V Boost with 1 µH inductor to VPP = 18V, CVPP = 1uF, unloaded, FOSC = 1 MHz, (Note 2) — 175 — µs Total for all channels; VPP = 18V, Cload = 15pF per channel, OE frequency = 1 MHZ, ILIM = 10, VDD = 3.6V Boost with 1 µH inductor to VPP = 18V, CVPP = 1uF, unloaded, FOSC = 1 MHz, (Note 2) — — 100 µs All ILIM, VDD = 3.6V, program fall from VPP = 18V to VPP = 6V Boost with 1 µH inductor, unloaded, CVPP = 1uF, FOSC = 1 MHz These specs are tested at DC. Actual thresholds under dynamic operation may be higher. CVPP = Capacitance between VPP and VSS = C2 in application diagram. TABLE 7-5: MTCH650 VPP ANALOG CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. VP1 Sym. VPP Characteristic High Voltage Input 2014 Microchip Technology Inc. Min. Max. Units 3.6 18 V VDD < 3.6V VDD 18 V VDD 3.6V Preliminary Conditions DS40001749A-page 21 MTCH650/2 TABLE 7-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Typ. Units TH01 JA Thermal Resistance Junction to Ambient TH02 JC Thermal Resistance Junction to Case 69.7 48 18.9 C/W C/W C/W TH03 TJMAX Maximum Junction Temperature 12 150 C/W C DS40001749A-page 22 Preliminary Conditions 28-pin SOIC package 28-pin UQFN package 28-pin SOIC package 28-pin UQFN package 2014 Microchip Technology Inc. MTCH650/2 NOTES: 2014 Microchip Technology Inc. Preliminary DS40001749A-page 23 MTCH650/2 8.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided in this section are for design guidance and are not tested. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range. FIGURE 8-1: TYPICAL PWM; fPWM = 500 kHz, 70% DUTY CYCLE, VDD = 3.3V FIGURE 8-3: OE vs. OUT00; VDD = 3.3V, VPP = 18V, CVPP(C2) = 1µF FIGURE 8-2: OE vs. OUT00; VDD = 3.3V, VPP = 18V, CVPP(C2) = 10µF FIGURE 8-4: BOOST VPP 6V TO 18V AND DISCHARGE 18V TO 6V; DISCHARGE ON, VDD = 3.3V, CVPP (C2) = 10µF DS40001749A-page 24 Preliminary 2014 Microchip Technology Inc. MTCH650/2 FIGURE 8-5: BOOST VPP 6V TO 18V AND DISCHARGE 18V TO 6V; DISCHARGE ON, VDD = 3.3V, CVPP (C2) = 1µF FIGURE 8-6: RIPPLE ON VPP AND OUT00; VDD = 3.3V, VPP = 18V, CVPP (C2) = 10µF FIGURE 8-7: RIPPLE ON VPP AND OUT00; VDD = 3.3V, VPP = 18V, CVPP (C2) = 1µF 2014 Microchip Technology Inc. Preliminary DS40001749A-page 25 MTCH650/2 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX MTCH650 I/SO YYWWNNN 1322017 28-Lead SSOP (5.30 mm) Example MTCH652 I/SS 1322017 Legend: XX...X Y YY WW NNN e3 * Note: * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS40001749A-page 26 Preliminary 2014 Microchip Technology Inc. MTCH650/2 9.1 Package Marking Information (Continued) 28-Lead UQFN (4x4x0.5 mm) Example PIN 1 PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: * MTCH 652 I/MV 1322017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2014 Microchip Technology Inc. Preliminary DS40001749A-page 27 MTCH650/2 9.2 Package Details The following sections give the technical details of the packages. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001749A-page 28 Preliminary 2014 Microchip Technology Inc. MTCH650/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. Preliminary DS40001749A-page 29 MTCH650/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001749A-page 30 Preliminary 2014 Microchip Technology Inc. MTCH650/2 /HDG3ODVWLF6KULQN6PDOO2XWOLQH66±PP%RG\>6623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ ± %6& ± 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' )RRW/HQJWK / )RRWSULQW / 5() /HDG7KLFNQHVV F ± )RRW$QJOH /HDG:LGWK E ± 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% 2014 Microchip Technology Inc. Preliminary DS40001749A-page 31 MTCH650/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001749A-page 32 Preliminary 2014 Microchip Technology Inc. MTCH650/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. Preliminary DS40001749A-page 33 MTCH650/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001749A-page 34 Preliminary 2014 Microchip Technology Inc. MTCH650/2 2014 Microchip Technology Inc. Preliminary DS40001749A-page 35 MTCH650/2 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (04/2014) Initial release of this data sheet. DS40001749A-page 36 Preliminary 2014 Microchip Technology Inc. MTCH650/2 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. 2014 Microchip Technology Inc. Preliminary DS40001749A-page 37 MTCH650/2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: MTCH650; MTCH652 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I = -40C to Package:(2) SO SS MV Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) +85C MTCH652 - I/SO Industrial temperature SOIC package. MTCH650 - I/SS Industrial temperature SSOP package. (Industrial) Note 1: = = = 28-pin SOIC 28-pin SSOP 28-pin UQFN (4x4x0.5) 2: DS40001749A-page 38 Preliminary Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. For other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your local sales office. 2014 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-63276-181-1 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2014 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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