3-17V 0.5A Step-Down Converters with DCS

TPS62170, TPS62171
TPS62172, TPS62173
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SLVSAT8C – NOVEMBER 2011 – REVISED SEPTEMBER 2013
3-17V 0.5A Step-Down Converter with DCS-ControlTM
Check for Samples: TPS62170, TPS62171, TPS62172, TPS62173
FEATURES
DESCRIPTION
1
•
•
•
•
•
•
•
•
•
•
•
•
The TPS6217X family is an easy to use synchronous
step down DC-DC converter optimized for
applications with high power density. A high switching
frequency of typically 2.25MHz allows the use of
small inductors and provides fast transient response
as well as high output voltage accuracy by utilization
of the DCS-Control™ topology.
TM
DCS-Control Topology
Input Voltage Range: 3 to 17 V
Up to 500 mA Output Current
Adjustable Output Voltage from 0.9 to 6 V
Fixed Output Voltage Versions
Seamless Power Save Mode Transition
Typically 17µA Quiescent Current
Power Good Output
100% Duty Cycle Mode
Short Circuit Protection
Over Temperature Protection
Available in a 2 × 2 mm, WSON-8 Package
With its wide operating input voltage range of 3V to
17V, the devices are ideally suited for systems
powered from either a Li-Ion or other battery as well
as from 12V intermediate power rails. It supports up
to 0.5A continuous output current at output voltages
between 0.9V and 6V (with 100% duty cycle mode).
Power sequencing is also possible by configuring the
Enable and open-drain Power Good pins.
In Power Save Mode, the devices show quiescent
current of about 17μA from VIN. Power Save Mode,
entered automatically and seamlessly if load is small,
maintains high efficiency over the entire load range.
In Shutdown Mode, the device is turned off and
shutdown current consumption is less than 2μA.
APPLICATIONS
•
•
•
•
•
•
Standard 12V Rail Supplies
POL Supply from Single or Multiple Li-Ion
Battery
LDO Replacement
Embedded Systems
Digital Still Camera, Video
Mobile PC's, Tablet, Modems
The device, available in adjustable and fixed output
voltage versions, is packaged in an 8-pin WSON
package measuring 2 × 2 mm (DSG).
spacing
spacing
(3 .. 17)V
1.8V / 0.5A
2.2µH
VIN
SW
EN
10uF
VOS
TPS62171
AGND
PG
PGND
FB
100k
22uF
Figure 1. Typical Application and Efficiency
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
TPS62170, TPS62171
TPS62172, TPS62173
SLVSAT8C – NOVEMBER 2011 – REVISED SEPTEMBER 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TA
OUTPUT VOLTAGE
PART NUMBER (2)
ORDERING
PACKAGE MARKING
adjustable
TPS62170
TPS62170DSG
QUE
1.8 V
TPS62171
TPS62171DSG
QUF
3.3 V
TPS62172
TPS62172DSG
QUG
5.0 V
TPS62173
TPS62173DSG
QUH
-40°C to 85°C
(1)
(2)
PACKAGE
8-Pin WSON
For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
Contact the factory to check availability of other fixed output voltage versions.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
Pin Voltage
Range (2)
–0.3 to 20
EN
–0.3 to VIN+0.3
SW
-0.3 to VIN+0.3
V
–0.3 to 7
V
10
mA
FB, PG, VOS
Power Good sink
current
Temperature range
(1)
(2)
(3)
PG
Operating junction temperature range, TJ
–40 to 125
Storage temperature range, Tstg
–65 to 150
HBM Human body model
ESD rating (3)
UNIT
VIN
CDM Charge device model
V
°C
2
kV
0.5
kV
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
TPS6217X
THERMAL METRIC (1)
θJA
Junction-to-ambient thermal resistance
61.8
θJC(TOP)
Junction-to-case(top) thermal resistance
61.3
θJB
Junction-to-board thermal resistance
15.5
ψJT
Junction-to-top characterization parameter
0.4
ψJB
Junction-to-board characterization parameter
15.4
θJC(BOTTOM)
Junction-to-case(bottom) thermal resistance
8.6
(1)
UNITS
DSG (8) PINS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Supply Voltage, VIN
TYP
3
MAX
UNIT
17
V
Operating free air temperature, TA
–40
85
°C
Operating junction temperature, TJ
–40
125
°C
2
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ELECTRICAL CHARACTERISTICS
over free-air temperature range (TA=-40°C to +85°C), typical values at VIN=12V and TA=25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input Voltage Range (1)
17
V
IQ
Operating Quiescent Current
EN=High, IOUT=0mA, device not switching
17
25
µA
ISD
Shutdown Current (2)
EN=Low
1.5
4
µA
VUVLO
Undervoltage Lockout Threshold
2.7
2.82
TSD
Thermal Shutdown Temperature
3
Falling Input Voltage
2.6
Hysteresis
V
180
mV
160
Thermal Shutdown Hysteresis
°C
20
CONTROL (EN, PG)
VEN_H
High Level Input Threshold Voltage (EN)
0.9
VEN_L
Low Level Input Threshold Voltage (EN)
ILKG_EN
Input Leakage Current (EN)
VTH_PG
Power Good Threshold Voltage
VOL_PG
Power Good Output Low
IPG=-2mA
0.07
0.3
V
ILKG_PG
Input Leakage Current (PG)
VPG=1.8V
1
400
nA
VIN≥6V
300
600
VIN=3V
430
VIN≥6V
120
VIN=3V
165
EN=VIN or GND
V
0.3
V
0.01
1
µA
Rising (%VOUT)
92
95
98
Falling (%VOUT)
87
90
93
%
POWER SWITCH
High-Side MOSFET ON-Resistance
RDS(ON)
Low-Side MOSFET ON-Resistance
ILIMF
High-Side MOSFET Forward Current Limit (3)
VIN=12V, TA=25°C
0.85
1.05
mΩ
200
mΩ
1.35
A
OUTPUT
VREF
Internal Reference Voltage (4)
ILKG_FB
Pin Leakage Current (FB)
TPS62170, VFB=1.2V
400
nA
Output Voltage Range (TPS62170)
VIN ≥ VOUT
0.9
6.0
V
PWM mode operation, VIN≥VOUT+1V
–3
3
-3.5
4
0.8
Initial Output Voltage Accuracy (5)
VOUT
(1)
(2)
(3)
(4)
(5)
(6)
Power Save Mode operation, COUT=22µF
DC Output Voltage Load Regulation (6)
DC Output Voltage Line Regulation
5
(6)
V
%
VIN=12V, VOUT=3.3V, PWM mode operation
0.05
%/A
3V ≤ VIN ≤ 17V, VOUT=3.3V, IOUT= 0.5A, PWM
mode operation
0.02
%/V
The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
Current into VIN pin.
This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short
Circuit Protection).
This is the voltage regulated at the FB pin.
This is the accuracy provided by the device itself (line and load regulation effects are not included). For fixed voltage versions, the
(internal) resistive feedback divider is included.
Line and load regulation are depending on external component selection and layout (see Figure 13 and Figure 14).
Copyright © 2011–2013, Texas Instruments Incorporated
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DEVICE INFORMATION
DSG PACKAGE
(TOP VIEW)
PGND
1
VIN
2
EN
3
AGND
4
Exposed
Thermal
Pad
8
PG
7
SW
6
VOS
5
FB
Terminal Functions
PIN (1)
NAME
NO.
I/O
DESCRIPTION
PGND
1
VIN
2
I
Supply voltage
EN
3
I
Enable input (High = enabled, Low = disabled)
AGND
4
FB
5
I
Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended to
connect FB to AGND on fixed output voltage versions for improved thermal performance.
VOS
6
I
Output voltage sense pin and connection for the control loop circuitry.
SW
7
O
Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
PG
8
O
Exposed
Thermal Pad
(1)
4
Power ground
Analog Ground
Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires
pull-up resistor; goes high impedance, when device is switched off)
Must be connected to AGND. Must be soldered to achieve appropriate power dissipation and mechanical
reliability.
For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections.
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SLVSAT8C – NOVEMBER 2011 – REVISED SEPTEMBER 2013
FUNCTIONAL BLOCK DIAGRAM
PG
Soft
start
Thermal
Shtdwn
UVLO
VIN
PG control
HS lim
comp
power
control
control logic
EN*
gate
drive
SW
comp
LS lim
VOS
direct control
&
compensation
ramp
_
FB
comparator
+
timer tON
error
amplifier
DCS - ControlTM
*
This pin is connected to a pull down resistor internally
(see Detailed Description section).
AGND
PGND
Figure 2. TPS62170 (adjustable output voltage)
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PG
Soft
start
Thermal
Shtdwn
UVLO
VIN
PG control
HS lim
comp
power
control
control logic
EN*
gate
drive
SW
comp
LS lim
VOS
direct control
&
compensation
ramp
_
FB*
comparator
+
timer tON
error
amplifier
DCS - ControlTM
*
This pin is connected to a pull down resistor internally
(see Detailed Description section).
AGND
PGND
Figure 3. TPS62171/2/3 (fixed output voltage)
6
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SLVSAT8C – NOVEMBER 2011 – REVISED SEPTEMBER 2013
PARAMETER MEASUREMENT INFORMATION
List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
IC
17V, 1A Step-Down Converter, WSON
TPS62170DSG, Texas Instruments
L1
2.2uH, 1.4A, 3 x 2.8 x 1.2 mm
Cin
10µF, 25V, Ceramic
Standard
Cout
22µF, 6.3V, Ceramic
Standard
R1
depending on Vout
R2
depending on Vout
R3
100kΩ, Chip, 0603, 1/16W, 1%
VLF3012ST-2R2M1R4, TDK
Standard
spacing
spacing
2.2µH
VIN
VIN
EN
CIN
VOUT
SW
VOS
R3
R1
TPS62170
GND
COUT
PG
R2
PGND
FB
Figure 4. Measurement Setup
spacing
TYPICAL CHARACTERISTICS
Table of Graphs
DESCRIPTION
Efficiency
FIGURE
vs Output Current, vs Input Voltage
5 - 12
vs Output current (Load regulation)
13
vs Input Voltage (Line regulation)
14
vs Input Voltage
15
vs Output Current
16
Quiescent Current
vs Input Voltage
17
Shutdown Current
vs Input Voltage
Power FET RDS(on)
vs Input Voltage (High-Side, Low-Side)
Output Voltage Ripple
vs output Current
Maximum Output Current
vs Input Voltage
Output voltage
Switching Frequency
Waveforms
Copyright © 2011–2013, Texas Instruments Incorporated
18
19, 20
21
22
PWM-PSM-PWM Mode Transition
23, 24
Load Transient Response
25 - 28
Startup
29, 30
Typical Power Save Mode Operation
31
Typical PWM Mode Operation
32
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100.0
100.0
90.0
90.0
80.0
80.0
70.0
Efficiency (%)
VIN=17V
60.0
VIN=12V
50.0
40.0
30.0
VOUT=6.0V
L=2.2uH (VLF3012ST)
Cout=22uF
10.0
0.0
0.0001
0.001
0.01
Output Current (A)
0.1
0.0
1
8
9
10
11
12
13
Input Voltage (V)
Figure 5. Vout=6V
Figure 6. Vout=6V
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
80.0
80.0
70.0
70.0
60.0
VIN=17V
50.0
VIN=12V
VIN=5V
14
15
16
17
G001
IOUT=500mA
IOUT=1mA
60.0
IOUT=10mA
IOUT=100mA
50.0
40.0
30.0
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
20.0
10.0
0.001
0.01
Output Current (A)
0.1
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
20.0
10.0
0.0
1
4
5
6
7
8
G001
9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
Figure 7. Vout=3.3V
Figure 8. Vout=3.3V
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100.0
100.0
VIN=5V
80.0
70.0
70.0
60.0
VIN=17V
50.0
40.0
IOUT=500mA
90.0
80.0
Efficiency (%)
Efficiency (%)
7
G001
90.0
VIN=12V
30.0
60.0
IOUT=1mA
50.0
IOUT=10mA
IOUT=100mA
40.0
30.0
VOUT=1.8V
L=2.2uH (VLF3012ST)
Cout=22uF
20.0
10.0
0.0
0.0001
VOUT=6.0V
L=2.2uH (VLF3012ST)
Cout=22uF
10.0
100.0
90.0
IOUT=500mA
40.0
90.0
0.0
0.0001
IOUT=100mA
IOUT=10mA
50.0
100.0
40.0
IOUT=1mA
60.0
20.0
30.0
0.001
0.01
Output Current (A)
Figure 9. Vout=1.8V
8
70.0
30.0
VIN=6V
20.0
Efficiency (%)
EFFICIENCY
vs
INPUT VOLTAGE
Efficiency (%)
Efficiency (%)
EFFICIENCY
vs
OUTPUT CURRENT
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0.1
VOUT=1.8V
L=2.2uH (VLF3012ST)
Cout=22uF
20.0
10.0
1
G001
0.0
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
Figure 10. Vout=1.8V
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SLVSAT8C – NOVEMBER 2011 – REVISED SEPTEMBER 2013
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100.0
100.0
90.0
90.0
VIN=5V
70.0
60.0
50.0
VIN=17V
40.0
VIN=12V
30.0
10.0
0.001
60.0
50.0
IOUT=1mA
40.0
0.01
Output Current (A)
0.1
VOUT=0.9V
L=2.2uH (VLF3012ST)
Cout=22uF
10.0
0.0
1
3
4
5
6
7
G001
8 9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
Figure 11. Vout=0.9V
Figure 12. Vout=0.9V
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
3.35
Output Voltage (V)
Output Voltage (V)
IOUT=500mA
70.0
20.0
3.35
3.30
VIN=5V
VIN=12V
VIN=17V
3.25
IOUT=1mA
IOUT=10mA
IOUT=100mA
IOUT=500mA
3.30
3.25
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
3.20
0.0001
0.001
0.01
Output Current (A)
0.1
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
3.20
1
4
7
10
13
Input Voltage (V)
G001
16
G001
Figure 13. Output Voltage Accuracy (Load Regulation)
Figure 14. Output Voltage Accuracy (Line Regulation)
SWITCHING FREQUENCY
vs
OUTPUT CURRENT
SWITCHING FREQUENCY
vs
INPUT VOLTAGE
4
4
3.5
3.5
Switching Frequency (MHz)
Switching Frequency (MHz)
IOUT=100mA
30.0
VOUT=0.9V
L=2.2uH (VLF3012ST)
Cout=22uF
20.0
0.0
0.0001
IOUT=10mA
80.0
Efficiency (%)
Efficiency (%)
80.0
3
2.5
2
1.5
1
VIN=12V, VOUT=3.3V
L=2.2uH (VLF3012ST)
0.5
0
0
0.1
0.2
0.3
Output Current (A)
0.4
Figure 15. Switching Frequency
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3
2.5
2
IOUT=0.5A
1.5
1
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
0.5
0.5
G000
0
4
6
8
10
12
Input Voltage (V)
14
16
18
G000
Figure 16. Switching Frequency
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INPUT CURRENT
vs
INPUT VOLTAGE
INPUT CURRENT
vs
INPUT VOLTAGE
50.0
4.0
45.0
3.5
Input Current (µA)
Input Current (µA)
40.0
35.0
30.0
25°C
25.0
85°C
20.0
15.0
5.0
0.0
0.0
2.0
1.5
3.0
−40°C
0.5
6.0
0.0
0.0
9.0
12.0
Input Voltage (V)
15.0
18.0 20.0
−40°C
3.0
6.0
G001
9.0
12.0
Input Voltage (V)
18.0 20.0
G001
STATIC DRAIN-SOURCE-RESISTANCE (RDSon)
vs
INPUT VOLTAGE
STATIC DRAIN-SOURCE-RESISTANCE (RDSon)
vs
INPUT VOLTAGE
250.0
225.0
125°C
−40°C
125°C
200.0
85°C
175.0
150.0
25°C
125.0
−20°C
100.0
75.0
−40°C
50.0
25.0
9.0
12.0
Input Voltage (V)
15.0
0.0
3.0
18.0
6.0
9.0
12.0
15.0
Input Voltage (V)
G001
Figure 19. High-Side Switch
Figure 20. Low-Side Switch
OUTPUT VOLTAGE RIPPLE
vs
OUTPUT CURRENT
OUTPUT CURRENT
vs
INPUT VOLTAGE
0.05
18.0
20.0
G001
1.5
VOUT=3.3V,
L=2.2uH (VLF3012ST)
Cout=22uF
1.2
VIN=17V
Output Current (A)
0.04
0.03
0.02
VIN=12V
0.01
1
−40°C
0.5
85°C
VOUT=3.3V
L=2.2uH (VLF3012ST)
Cout=22uF
0.2
0
0.1
0.2
0.3
Output Current (A)
0.4
Figure 21. Output Voltage Ripple
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0.5
G000
25°C
0.8
VIN=5V
10
15.0
Figure 18. Shutdown Current
600.0
550.0
500.0
85°C
450.0
400.0
25°C
350.0
300.0
−20°C
250.0
200.0
150.0
100.0
50.0
0.0
3.0
6.0
0
25°C
Figure 17. Quiescent Current
RDSon Low−Side (mΩ)
RDSon High−Side (mΩ)
85°C
2.5
1.0
10.0
Output Voltage Ripple (V)
3.0
0
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
G000
Figure 22. Maximum Output Current
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OUTPUT VOLTAGE
vs
TIME
OUTPUT VOLTAGE
vs
TIME
Figure 23. PWM to PSM Mode Transition
Figure 24. PSM to PWM Mode Transition
TRANSIENT RESPONSE
vs
TIME
TRANSIENT RESPONSE
vs
TIME
Figure 25. Load Transient Response in PWM Mode (200mA
to 500mA)
Figure 26. Load Transient Response from Power Save Mode
(100mA to 500mA)
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TRANSIENT RESPONSE
vs
TIME
TRANSIENT RESPONSE
vs
TIME
Figure 27. Load Transient Response in PWM Mode (200mA
to 500mA), rising edge
Figure 28. Load Transient Response in PWM Mode (200mA
to 500mA), falling edge
STARTUP TO VOUT=3.3V
vs
TIME
STARTUP TO VOUT=3.3V
vs
TIME
Figure 29. Startup with Iout=100mA
Figure 30. Startup with Iout=500mA
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PSM MODE OPERATION
vs
TIME
PWM MODE OPERATION
vs
TIME
Figure 31. Typical Operation in Power Save Mode
(Iout=66mA)
Figure 32. Typical Operation in PWM mode (Iout=500mA)
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DETAILED DESCRIPTION
Device Operation
The TPS6217X synchronous switched mode power converters are based on DCS-Control™ (Direct Control with
Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage.
This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage.
It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate
response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors.
The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.25MHz with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the
load current. Since DCS-ControlTM supports both operation modes within one single building block, the transition
from PWM to Power Save Mode is seamless without effects on the output voltage.
Fixed output voltage versions provide smallest solution size and lowest current consumption, requiring only 3
external components. An internal current limit supports nominal output currents of up to 500mA.
The TPS6217X family offers both excellent DC voltage and superior load transient regulation, combined with
very low output voltage ripple, minimizing interference with RF circuits.
Pulse Width Modulation (PWM) Operation
The TPS6217X operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of about 2.25MHz. The frequency variation in PWM is controlled and depends on VIN, VOUT
and the inductance. The device operates in PWM mode as long the output current is higher than half the
inductor's ripple current. To maintain high efficiency at light loads, the device enters Power Save Mode at the
boundary to discontinuous conduction mode (DCM). This happens if the output current becomes smaller than
half the inductor's ripple current.
Power Save Mode Operation
The TPS6217X's built in Power Save Mode will be entered seamlessly, if the load current decreases. This
secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor
current is discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
TPS6217X includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated as:
V
t ON = OUT × 420ns
VIN
(1)
For very small output voltages, the on-time increases beyond the result of Equation 1, to stay above an absolute
minimum on-time, tON(min), which is around 80ns to limit switching losses. The peak inductor current in PSM can
be approximated by:
I LPSM ( peak ) =
(V IN - VOUT )
× t ON
L
(2)
When VIN decreases to typically 15% above VOUT, the TPS6217X won't enter Power Save Mode, regardless of
the load current. The device maintains output regulation in PWM mode.
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100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal
setpoint. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of
battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
VIN (min) = VOUT (min) + I OUT (RDS ( on ) + RL )
(3)
where
IOUT is the output current,
RDS(on) is the RDS(on) of the high-side FET and
RL is the DC resistance of the inductor used.
Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation.
Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.5µA. During shutdown, the internal
power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the
output voltage smoothly. If the EN pin is Low, an internal pull-down resistor of about 400kΩ is connected and
keeps it Low, to avoid bouncing. To avoid ON/OFF oscillations, a minimum slew rate of about 50mV/s is
recommended for the EN signal.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
Softstart
The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50µs and VOUT rises with a slope of about 25mV/µs. See Figure 29 and Figure 30 for typical
startup operation.
The TPS6217X can start into a pre-biased output. During monotonic pre-biased startup, the low-side MOSFET is
not allowed to turn on until the device's internal ramp sets an output voltage above the pre-bias voltage.
Current Limit And Short Circuit Protection
The TPS6217X devices are protected against heavy load and short circuit events. At heavy loads, the current
limit determines the maximum output current. If the current limit is reached, the high-side FET will be turned off.
Avoiding shoot through current, the low-side FET will be switched on to sink the inductor current. The high-side
FET will turn on again, only if the current in the low-side FET has decreased below the low side current limit
threshold.
The output current of the device is limited by the current limit (see ELECTRICAL CHARACTERISTICS). Due to
internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic
current limit can be calculated as follows:
I peak ( typ ) = I LIMF +
VL
× t PD
L
(4)
where
ILIMF is the static current limit, specified in the electrical characteristic table,
L is the inductor value,
VL is the voltage across the inductor and
tPD is the internal propagation delay.
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The dynamic high side switch peak current can be calculated as follows:
I peak ( typ ) = I LIMF _ HS +
(V IN
- VOUT )
× 30ns
L
(5)
Care on the current limit has to be taken if the input voltage is high and very small inductances are used.
Power Good (PG)
The TPS6217X has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and
maintain its specified logic low level. It is high impedance when the device is turned off due to EN, UVLO or
thermal shutdown.
Under Voltage Lockout (UVLO)
If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the
power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 180mV.
Thermal Shutdown
The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C
(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG
goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.
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APPLICATION INFORMATION
The following information is intended to be a guideline through the individual power supply design process.
Programming The Output Voltage
While the output voltage of the TPS62170 is adjustable, the TPS62171/2/3 are programmed to fixed output
voltages. For fixed output versions, the FB pin is pulled down internally and may be left floating. it is
recommended to connect it to AGND to improve thermal resistance. The adjustable version can be programmed
for output voltages from 0.9V to 6V by using a resistive divider from VOUT to AGND. The voltage at the FB pin is
regulated to 800mV. The value of the output voltage is set by the selection of the resistive divider from
Equation 6. It is recommended to choose resistor values which allow a cross current of at least 2uA, meaning the
value of R2 shouldn't exceed 400kΩ. Lower resistor values are recommended for highest accuracy and most
robust design. For applications requiring lowest current consumption, the use of fixed output voltage versions is
recommended.
æV
ö
R1 = R 2 çç OUT - 1÷÷
V
è REF
ø
(6)
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin to about 7.4V.
External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TPS6217X is optimized to work within a range of external components. The LC output filters
inductance and capacitance have to be considered together, creating a double pole, responsible for the corner
frequency of the converter (see Output Filter And Loop Stability section). Table 1 can be used to simplify the
output filter component selection.
Table 1. Recommended LC Output Filter Combinations (1)
4.7µF
10µF
22µF
47µF
100µF
200µF
2.2µH
√
√ (2)
√
√
√
3.3µH
√
√
√
√
400µF
1µH
4.7µH
(1)
(2)
The values in the table are nominal values. Variations of typically ±20% due to tolerance, saturation and DC bias are assumed.
This LC combination is the standard value and recommended for most applications.
More detailed information on further LC combinations can be found in SLVA463.
Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-toPSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under
static load conditions.
I L(max) = I OUT (max) +
DI L(max) = VOUT
DI L(max)
2
(7)
V
æ
ç 1 - OUT
ç V IN (max)
×ç
L
×f
ç (min) SW
ç
è
ö
÷
÷
÷
÷
÷
ø
(8)
where
IL(max) is the maximum inductor current,
ΔIL is the Peak to Peak Inductor Ripple Current,
L(min) is the minimum effective inductor value and
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fSW is the actual PWM Switching Frequency.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS6217X and are recommended for use:
Table 2. List of Inductors
(1)
Type
Inductance [µH]
Current [A] (1)
Dimensions [L x B x H] mm
MANUFACTURER
VLF3012ST-2R2M1R4
2.2µH, ±20%
1.9A
3.0 x 2.8 x 1.2
TDK
VLF302512MT-2R2M
2.2µH, ±20%
1.9A
3.0 x 2.5 x 1.2
TDK
VLS252012-2R2
2.2µH, ±20%
1.3A
2.5 x 2.0 x 1.2
TDK
XFL3012-222MEC
2.2µH, ±20%
1.9
3.0 x 3.0 x 1.2
Coilcraft
XFL3012-332MEC
3.3µH, ±20%
1.6
3.0 x 3.0 x 1.2
Coilcraft
XPL2010-222MLC
2.2µH, ±20%
1.3A
1.9 x 2.0 x 1.0
Coilcraft
XPL2010-332MLC
3.3µH, ±20%
1.1A
1.9 x 2.0 x 1.0
Coilcraft
LPS3015-332ML
3.3µH, ±20%
1.4A
3.0 x 3.0 x 1.4
Coilcraft
PFL2512-222ME
2.2µH, ±20%
1.0A
2.8 x 2.3 x 1.2
Coilcraft
PFL2512-333ME
3.3µH, ±20%
0.78A
2.8 x 2.3 x 1.2
Coilcraft
744028003
3.3µH, ±30%
1.0A
2.8 x 2.8 x 1.1
Wuerth
PSI25201B-2R2MS
2.2uH, ±20%
1.3A
2.0 x 2.5 x 1.2
Cyntec
NR3015T-2R2M
2.2uH, ±20%
1.5A
3.0 x 3.0 x 1.5
Taiyo Yuden
BRC2012T2R2MD
2.2µH, ±20%
1.0A
2.0 x 1.25 x 1.4
Taiyo Yuden
BRC2012T3R3MD
3.3µH, ±20%
0.87A
2.0 x 1.25 x 1.4
Taiyo Yuden
IRMS at 40°C rise or ISAT at 30% drop.
spacing
TPS6217X can be run with an inductor as low as 2.2µH. However, for applications running with low input
voltages, 3.3µH is recommended, to allow the full output current. The inductor value also determines the load
current at which Power Save Mode is entered:
I load ( PSM ) =
1
DI L
2
(9)
Using Equation 8, this current level can be adjusted by changing the inductor value.
Capacitor Selection
Output Capacitor
The recommended value for the output capacitor is 22uF. The architecture of the TPS6217X allows the use of
tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output
voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can
have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see
SLVA463).
Note: In power save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak
inductor current. Using ceramic capacitors provides small ESR and low ripple.
Input Capacitor
For most applications, 10µF will be sufficient and is recommended, though a larger value reduces input current
ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter
from the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between VIN and GND as close as possible to those pins.
spacing
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NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
spacing
Output Filter And Loop Stability
The devices of the TPS6217X family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 10:
f LC =
1
2p L × C
(10)
Proven nominal values for inductance and ceramic capacitance are given in Table 1 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which will be affected. More
information including a detailed L-C stability matrix can be found in SLVA463.
The TPS6217X devices, both fixed and adjustable versions, include an internal 25pF feedforward capacitor,
connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and
zero in the control loop with the resistors of the feedback divider, per Equation 11 and Equation 12:
f zero =
f pole =
1
2p × R1 × 25 pF
1
2p × 25 pF
(11)
æ 1
1 ö
÷÷
× çç
+
R
R
2 ø
è 1
(12)
Though the TPS6217X devices are stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more detailed discussion
on the optimization for stability vs. transient response can be found in SLVA289 and SLVA466.
If using ceramic capacitors, the DC bias effect has to be considered. The DC bias effect results in a drop in
effective capacitance as the voltage across the capacitor increases (see DC Bias effect NOTE in Capacitor
selection section).
Layout Considerations
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS6217X demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity.
Provide low inductive and resistive paths to ground for loops with high di/dt. Therefore paths conducting the
switched load current should be as short and wide as possible. Provide low capacitive paths (with respect to all
other nodes) for wires with high dv/dt. Therefore the input and output capacitance should be placed as close as
possible to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops
which conduct an alternating current should outline an area as small as possible, as this area is proportional to
the energy radiated.
Also sensitive nodes like FB and VOS should be connected with short wires, not nearby high dv/dt signals (e.g.
SW). As they carry information about the output voltage, they should be connected as close as possible to the
actual output voltage (at the output capacitor). Signals not assigned to power transmission (e.g. feedback divider)
should refer to the signal ground (AGND) and always be separated from the power ground (PGND).
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In summary, the input capacitor should be placed as close as possible to the VIN and PGND pin of the IC. This
connections should be done with wide and short traces. The output capacitor should be placed such that its
ground is as close as possible to the IC's PGND pins - avoiding additional voltage drop in traces. This connection
should also be made short and wide. The inductor should be placed close to the SW pin and connect directly to
the output capacitor - minimizing the loop area between the SW pin, inductor, output capacitor and PGND pin.
The feedback resistors, R1 and R2, should be placed close to the IC and connect directly to the AGND and FB
pins. Those connections (including VOUT) to the resistors and even more to the VOS pin should stay away from
noise sources, such as the inductor. The VOS pin should connect in the shortest way to VOUT at the output
capacitor, while the VOUT connection to the feedback divider can connect at the load.
A single point grounding scheme should be implemented with all grounds (AGND, PGND and the thermal pad)
connecting at the IC's exposed thermal pad. See for the recommended layout of the TPS6217X. More detailed
information can be found in the EVM Users Guide, SLVU483.
PGND
COUT
VOUT
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation. Although the Exposed Thermal Pad can be connected to a floating circuit board
trace, the device will have better thermal performance if it is connected to a larger ground plane. The Exposed
Thermal Pad is electrically connected to AGND.
CIN
L
VIN
AGND
R2
R1
VIN
Figure 33. Layout Example
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and (SPRA953).
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The TPS6217X is designed for a maximum operating junction temperature (Tj) of 125°C. Therefore the maximum
output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by
the package and the surrounding PCB structures. If the thermal resistance of the package is given, the size of
the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To
get an improved thermal behavior, it's recommended to use top layer metal to connect the device with wide and
thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal
performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
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Typical Applications
(5 .. 17)V
5V / 0.5A
2.2µH
VIN
SW
EN
10uF
VOS
100k
TPS62173
AGND
PG
PGND
FB
22uF
Figure 34. 5V/0.5A Power Supply
(3.3 .. 17)V
3.3V / 0.5A
2.2µH
VIN
SW
EN
10uF
VOS
100k
TPS62172
AGND
PG
PGND
FB
22uF
Figure 35. 3.3V/0.5A Power Supply
(3 .. 17)V
2.5V / 0.5A
2.2µH
VIN
SW
EN
10uF
VOS
TPS62170
AGND
PG
PGND
FB
100k
390k
22uF
180k
Figure 36. 2.5V/0.5A Power Supply
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(3 .. 17)V
1.8V / 0.5A
2.2µH
VIN
SW
EN
10uF
VOS
100k
TPS62171
AGND
PG
PGND
FB
22uF
Figure 37. 1.8V/0.5A Power Supply
(3 .. 17)V
1.5V / 0.5A
2.2µH
VIN
SW
EN
10uF
VOS
100k
TPS62170
AGND
PG
PGND
FB
130k
22uF
150k
Figure 38. 1.5V/0.5A Power Supply
(3 .. 17)V
1.2V / 0.5A
2.2µH
VIN
SW
EN
10uF
VOS
TPS62170
AGND
PG
PGND
FB
100k
75k
22uF
150k
Figure 39. 1.2V/0.5A Power Supply
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(3 .. 17)V
1V / 0.5A
2.2µH
VIN
SW
EN
VOS
10uF
AGND
PG
PGND
FB
51k
100k
TPS62170
22uF
200k
Figure 40. 1V/0.5A Power Supply
spacing
spacing
Application Example As Inverting Power Supply
spacing
The TPS62170 can be used as inverting power supply by rearranging external circuitry as shown in Figure 41.
As the former GND node now represents a voltage level below system ground, the voltage difference between
VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 13).
spacing
V IN + VOUT £ V IN max
(13)
spacing
spacing
10uF
2.2µH
(3 .. 12)V
VIN
SW
EN
10uF
VOS
TPS62170
GND
PG
PGND
FB
100k
680k
22uF
130k
-5V
Figure 41. -5V Inverting Power Supply
spacing
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22µF is recommended. A detailed design example is given in SLVA469.
spacing
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Product Folder Links: TPS62170 TPS62171 TPS62172 TPS62173
TPS62170, TPS62171
TPS62172, TPS62173
www.ti.com
SLVSAT8C – NOVEMBER 2011 – REVISED SEPTEMBER 2013
REVISION HISTORY
Changes from Original (November 2011) to Revision A
Page
•
Changed the ORDERING INFORMATION package markings ............................................................................................ 2
•
Changed Table 1 ................................................................................................................................................................ 17
Changes from Revision A (April 2012) to Revision B
Page
•
Changed 50mV/s to 50mV/µs in Enable / Shutdown (EN) section .................................................................................... 15
•
Changed 1A to 0.5A in Figure 34 to Figure 40 figure titles ................................................................................................ 22
•
Added diode to Figure 41 ................................................................................................................................................... 24
Changes from Revision B (August 2013) to Revision C
•
Page
Changed 50mV/µs to 50mV/s in Enable / Shutdown (EN) section .................................................................................... 15
Copyright © 2011–2013, Texas Instruments Incorporated
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Product Folder Links: TPS62170 TPS62171 TPS62172 TPS62173
25
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS62170DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUE
TPS62170DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUE
TPS62171DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUF
TPS62171DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUF
TPS62172DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUG
TPS62172DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUG
TPS62173DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUH
TPS62173DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-May-2014
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS62170 :
• Automotive: TPS62170-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS62170DSGR
WSON
DSG
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TPS62170DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TPS62171DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TPS62171DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TPS62172DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TPS62172DSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jul-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS62170DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
TPS62170DSGT
WSON
DSG
8
250
210.0
185.0
35.0
TPS62171DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
TPS62171DSGT
WSON
DSG
8
250
210.0
185.0
35.0
TPS62172DSGR
WSON
DSG
8
3000
210.0
185.0
35.0
TPS62172DSGT
WSON
DSG
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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