X9118
®
Dual Supply/Low Power/1024-Tap/2-Wire Bus
Data Sheet
PRELIMINARY
March 25, 2005
Single Digitally-Controlled (XDCP™)
Potentiometer
FN8161.1
FEATURES
• 1024 Resistor Taps – 10-Bit Resolution
• 2-Wire Serial Interface for write, read, and transfer
operations of the potentiometer
DESCRIPTION
The X9118 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
• Wiper Resistance, 40Ω Typical @ 5V
The digital controlled potentiometer is implemented
using 1023 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. The potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and a four non-volatile Data Registers that can
be directly written to and read by the user. The
contents of the WCR controls the position of the wiper
on the resistor array though the switches. Powerup
recalls the contents of the default data register (DR0)
to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
• Four Non-Volatile Data Registers for Each
Potentiometer
• Non-Volatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on Power
Up.
• Standby Current < 3µA Max
• System VCC: - 2.7V to 5.5V Operation
• Analog V+/V-: -5V to +5V
• 100kΩ End to End Resistance
• Endurance: 100, 000 Data changes per bit per register
• 100 yr. Data Retention
• 14-Lead TSSOP
• Low power CMOS
FUNCTIONAL DIAGRAM
VCC
2-Wire
Bus
Interface
Address
Data
Status
Bus
Interface &
Control
RH
Write
Read
Transfer
Control
VSS
1
NC
Power On Recall
100kΩ
1024-taps
POT
Wiper Counter
Register (WCR)
Wiper
Data Registers
(DR0-DR3)
NC
V+
RW
RL
V-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9118
DETAILED FUNCTIONAL DIAGRAM
VCC
V+
Power On
Recall
DR0
SCL
Interface
and
Control
Circuitry
SDA
A1
A0
DR1
Data
DR2
DR3
RH
Wiper
Counter
Register
(WCR)
100kΩ
1024-taps
RL
Control
RW
WP
VSS
V-
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent systems
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
2
FN8161.1
March 25, 2005
X9118
resistor. For selecting typical values, refer to the
guidelines for calculating typical values on the bus
pull-up resistors graph.
PIN CONFIGURATION
TSSOP
V+
NC
14
1
13
2
3
12
4 X9118 11
5
10
6
9
8
7
A0
SCL
WP
SDA
VSS
VCC
RL
SERIAL CLOCK (SCL)
RH
RW
This input is used by 2-wire master to supply 2-wire
serial clock to the X9118.
NC
A1
V-
DEVICE ADDRESS (A1–A0)
PIN ASSIGNMENTS
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9118. A maximum of 4 XDCP devices may
occupy the 2-wire serial bus.
PIN
(TSSOP)
SYMBOL
1
V+
Analog Supply Voltage
HARDWARE WRITE PROTECT INPUT (WP)
2
NC
No Connect
3
A0
Device Address for 2-wire bus
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
4
SCL
Serial Clock for 2-wire bus
Potentiometer Pins
5
WP
Hardware Write Protect
RH, RL
6
SDA
Serial Data Input/Output for 2-wire
bus
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
7
VSS
System Ground
8
V-
Analog Supply Voltage
9
A1
Device Address for 2-wire bus
10
NC
No Connect
11
RW
Wiper terminal of the Potentiometer
12
RH
High terminal of the Potentiometer
13
RL
Low terminal of the Potentiometer
14
VCC
FUNCTION
System Supply Voltage
RW
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system or digital supply voltage.
The VSS pin is the system ground.
PIN DESCRIPTIONS
ANALOG SUPPLY VOLTAGES (V+ AND V-)
Bus Interface Pins
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper
switches while the V- supply is used to bias the
switches and the internal P+ substrate of the
integrated circuit. Both of these supplies set the
voltage limits of the potentiometer.
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin
for a 2-wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs.
An open drain output requires the use of a pull-up
3
Other Pins
NO CONNECT
No connect pins should be left open. These pins are
used for Intersil manufacturing and testing purposes.
FN8161.1
March 25, 2005
X9118
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL
inputs).
PRINCIPLES OF OPERATION
The X9118 is an integrated microcircuit incorporating
a resistor array and their its registers and counters and
the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometer. This section provides detail
description of the following:
At both ends of each array and between each resistor
segment is a CMOS switch (transmission gate)
connected to the wiper (RW) output. Within each
individual array only one switch may be turned on at a
time. These switches are controlled by the Wiper
Counter Register (WCR). The 10-bits of the WCR
(WCR[9:0]) are decoded to select, and enable, one of
1024 switches.
– Resistor Array Description
– Serial Interface Description
– Instruction and Register Description
The WCR may be written directly. The Data Registers
and the WCR can be read and written by the host
system.
Resistor Array Description
The X9118 is comprised of a resistor array. The array
contains 1023, in effect, discrete resistive segments
that are connected in series (see Figure 1). The
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
RH
Serial
Bus
Input
From Interface
Circuitry
Register 0
(DR0)
Register 1
(DR1)
10
Register 2
(DR2)
10
Register 3
(DR3)
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then RW = RL
If WCR = 3FF[HEX] then RW = RH
RL
R
W
Serial Interface Description
CLOCK AND DATA CONVENTIONS
SERIAL INTERFACE – 2-WIRE
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.
The X9118 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9118 will be considered a
slave device in all applications.
4
START CONDITION
All commands to the X9118 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9118 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 3.
FN8161.1
March 25, 2005
X9118
STOP CONDITION
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 3.
ACKNOWLEDGE
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9118 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9118 will respond with a final acknowledge.
See Figure 2.
Figure 2. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
ACKNOWLEDGE
ACKNOWLEDGE POLLING
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9118
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9118 is still busy with the write operation no ACK
will be returned. If the X9118 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
5
FN8161.1
March 25, 2005
X9118
FLOW 1. ACK Polling Sequence
INSTRUCTION AND REGISTER DESCRIPTION
DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND
A)
Nonvolatile Write
Command Completed
EnterACK Polling
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier. The ID[3:0] bits is the device id for the
X9118; this is fixed as 0101[B] (refer to Table 1).
Issue
START
Issue Slave
Address
The A[1:0] bits in the ID byte are the internal slave
address. The physical device address is defined by the
state of the A1-A0 input pins. The slave address is
externally specified by the user. The X9118 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9118 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1-A0 inputs can
Instruction and Register Description
Issue STOP
ACK
Returned?
No
Yes
Further
Operation?
No
be actively driven by CMOS input signals or tied to
VCC or VSS. The R/W bit is the LSB and is used to set
the device for read or write operations.
Yes
Issue
Instruction
Issue STOP
INSTRUCTION BYTE AND REGISTER SELECTION
Proceed
The next byte sent to the X9118 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[2:0]). The RB and RA bits point to one of the
four registers. The format is shown below in Table 2.
Proceed
Table 3 provides a complete summary of the
instruction set opcodes.
Table 1. Identification Byte Format
Device Type
Identifies
Internal Slave
Address
Set to 0
for Proper
Operation
ID3
ID2
ID1
ID0
0
1
0
1
0
0
A0
(MSB)
Read or
Write Bit
R/W
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
I2
Register
Selection
Set to 0
for Proper
Operation
I1
I0
(MSB)
0
RB
Set to 0 for
Proper Operation
RA
0
0
(LSB)
6
FN8161.1
March 25, 2005
X9118
Register Selected
RB
RA
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Table 3. Instruction Set
Instruction Set
Instruction
R/W
I2
I1
I0
0
RB
RA
0
0
Read Wiper Counter
Register
1
1
0
0
0
0
0
0
0
Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register
0
1
0
1
0
0
0
0
0
Write new value to the Wiper Counter
Register
Read Data Register
1
1
0
1
0
1/0
1/0
0
0
Read the contents of the Data Register
pointed to RB-RA.
Write Data Register
0
1
1
0
0
1/0
1/0
0
0
Write new value to the Data Register
pointed to RB-RA.
XFR Data Register to
Wiper Counter Register
1
1
1
0
0
1/0
1/0
0
0
Transfer the contents of the Data Register
pointed to by RB-RA to the Wiper Counter
Register
XFR Wiper Counter
Register to Data Register
0
1
1
1
0
1/0
1/0
0
0
Transfer the contents of the Wiper Counter
Register to the Data Register
pointed to by RB-RA.
Note:
Operation
(1) 1/o = data is one or zero.
DEVICE ADDRESSING
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR .
WIPER COUNTER REGISTER (WCR)
DATA REGISTERS (DR)
The X9118 contains a Wiper Counter Register (see
Table 4) for the XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 1024
switches along its resistor array. The contents of the
WCR can be altered in one of three ways: (1) it may be
written directly by the host via the write Wiper Counter
Register instruction (serial load); (2) it may be written
indirectly by transferring the contents of one of four
associated Data Registers via the XFR Data register;
(3) it is loaded with the contents of its Data Register
zero (R0) upon power-up.
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four data registers and the Wiper Counter Register. All
operations changing data in one of the Data Registers
is a nonvolatile operation and will take a maximum of
10ms.
Instruction and Register Description
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9118 is powereddown. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
7
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bit 9–Bit 0 are used to store one of the 1024 wiper
position (0 ~1023).
FN8161.1
March 25, 2005
X9118
Table 4. Wiper Control Register, WCR (10-bit), WCR9–WCR0: Used to store the current wiper position (Volatile, V)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
Table 5. Data Register, DR (10-bit), Bit 9–Bit 0: Used to store wiper positions or data (Non-Volatile, NV)
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
Four of the six instructions are four bytes in length.
These instructions are:
Two instructions (see Figure 4) require a two-byte
sequence to complete. These instructions transfer
data between the host and the X9118; either between
the host and one of the Data Registers or directly
between the host and the Wiper Counter Register.
These instructions are:
– Read Wiper Counter Register – read the current
wiper position of the potentiometer,
– Write Wiper Counter Register – change current
wiper position of the potentiometer,
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the Wiper Counter Register.
– Read Data Register – read the contents of the
selected Data Register;
– Write Data Register – write a new value to the
selected Data Register.
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified Data Register.
The basic sequence of the four byte instructions is
illustrated in Figure 3. These four-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between the potentiometer and one of its associated
registers.
See Instruction format for more details.
Other
POWER UP AND DOWN REQUIREMENTS
At all times, the V+ voltage must be greater than or
equal to the voltage at RH or RL, and the voltage at RH
or RL must be greater than or equal to the voltage at
V-. During power up and power down, VCC, V+, and
V- must reach their final values with 1msec of each
other.
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
0
1
0
1
S ID3 ID2 ID1 ID0
T
A
Device ID
R
T
8
0
A1
A0 R/W
Internal
Address
A
C
K
I2
I1
I0
Instruction
Opcode
0
0
0
RB RA 0
Register
Address
0
A
C
K
S
T
O
P
FN8161.1
March 25, 2005
X9118
Figure 4. Four-Byte Instruction Sequence (Write or Read for WCR or Data Registers)
SCL
0
SDA
S
T
A
R
T
1
0
1
0
0
0 X
ID3 ID2 ID1 ID0 0 A1 A0 R/W A I2 I1 I0
C
K Instruction
Internal
Device ID
Opcode
Address
0
X 0
X X
A
C
K
0 RB RA 0
Register
Address
X X
X X
W
C
R
9
W A W W
C C C C
R K R R
8
7 6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W A
C C
R K
0
S
T
O
P
Wiper or Data
Position
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device
Addresses
0 A1 A0
R/W=1
Device Type
S
Identifier
T
A
R 0 1 0 1
T
Instruction
Opcode
S
A
C
K 1 0 0 0
Wiper Position
(Sent by Slave on SDA)
S
A
W W
C
C
0 K X X X X X X C R
R
9 8
Register
Addresses
0
0
0
Wiper Position
(Sent by Slave on SDA)
M
A
W W W W W W W W
C
C C C C C C C C
K R R R R R R R R
7 6 5 4 3 2 1 0
M
A
C
K
S
T
O
P
Wiper Position
(Sent by Master on SDA)
S
A
C W W W W W W W W
K C C C C C C C C
R R R R R R R R
7 6 5 4 3 2 1 0
S
A
C
K
S
T
O
P
wiper position or data
(Sent by Slave on SDA)
M
A
W C W W W W W W W W
C K C C C C C C C C
R
R R R R R R R R
8
7 6 5 4 3 2 1 0
M
A
C
K
S
T
O
P
Write Wiper Counter Register (WCR)
Device Type
Identifier
0
1
0
1
Device
Addresses
0
A1 A0
R/W=0
S
T
A
R
T
Instruction
Opcode
S
A
C
K
1
0
1
0
Register
Addresses
0
0
0
0
Wiper Position
(Sent by Master on SDA)
S
A
W W
C
K X X X X X X C C
R R
9
8
Read Data Register (DR)
Instruction
Opcode
R/W=1
Device Type
Device
S
Identifier
Addresses
T
A
R
T 0 1 0 1 0 A1 A0
9
S
A
C
K 1
0
1
0
Register
Addresses
RB
RA
0
Wiper Position
(Sent by Slave on SDA)
S
A
W
C
C
0 K X X X X X X R
9
FN8161.1
March 25, 2005
X9118
S
A
C
K
Instruction
Opcode
Register
Addresses
1 1 0 0 RB RA 0 0
S
A
C
K
Wiper Position or Data
(Sent by Master on SDA)
Wiper Position or Data
(Sent by Master on SDA)
S
A
W W C W W W W W W W W
C C K C C C C C C C C
X X X X X X R R
R R R R R R R R
9 8
7 6 5 4 3 2 1 0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Device
Device
Type
Addresses
S
Identifier
T
A
R
T 0 1 0 1 0 A1 A0
R/W=0
Write Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device
Addresses
Instruction
Opcode
R/W=0
Device Type
S
Identifier
T
A
R
0 1 0 1
T
0 A1 A0
S
A
C
K 1
1
1
Register
Addresses
0 RB RA 0
S
A
C
0 K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device
Addresses
0
A1 A0
R/W=1
Device Type
S
Identifier
T
A
R 0 1 0 1
T
Instruction
Register
Opcode
Addresses
S S
S
A T
A
C O
C
K 1 1 0 0 RB RA 0 0 K P
Notes: (1) “A1 ~ A0”: stand for the device addresses sent by the master.
(2) WCRx refers to wiper position data in the Wiper Counter Register
10
FN8161.1
March 25, 2005
X9118
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias..................... -65°C to +135°C
Storage temperature.......................... -65°C to +150°C
Voltage on SCL, SDA, or any address input
with respect to VSS ................................. -1V to +7V
Voltage on V+ (referenced to VSS)(4) ....................10V
Voltage on V- (referenced to VSS)(4) ....................-10V
(V+) – (V-) ..............................................................12V
Any Voltage on RH / RL............................................V+
Any Voltage on RL/ RH ............................................. VLead temperature (soldering, 10 seconds) ........ 300°C
IW (10 seconds)..................................................±6mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Supply Voltage (VCC) Limits(4)
5V ±10%
2.7V to 5.5V
Device
X9118
X9118-2.7
ANALOG CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
RTOTAL
Parameter
Min.
End to End Resistance
Typ.
Max.
100
Units
Test Conditions
kΩ
End to End Resistance Tolerance
±20
%
Power Rating
50
mW
IW
Wiper Current
±3
mA
RW
Wiper Resistance
150
500
Ω
Wiper Current = ± 3mA, VCC = 3V
RW
Wiper Resistance
40
100
Ω
IW = ± 3mA, VCC = 5V
Vv+
Voltage on V+ pin
+4.5
+5.5
V
X9118(4)
+2.7
+5.5
-5.5
-4.5
-5.5
-2.7
V-
V+
Vv-
VTERM
Voltage on V- pin
Voltage on any RH or RL Pin
Noise
Resolution
11
V
%
VSS = 0V
Ref: 1V
±1
MI(3)
Rw(n)(actual) – Rw(n)(expected),
where n=8 to 1006
±1.5
MI(3)
Rw(n)(actual) – Rw(n)(expected)(5)
±0.5
MI(3)
Rw(m + 1) – [Rw(m) + MI], where
m=8 to 1006
±1
MI(3)
Rw(m + 1) – [Rw(m) + MI](5)
±300
ppm/°C
20
10/10/25
X9118
X9118-2.7
0.1
Ratiometric Temp. Coefficient
CH/CL/CW Potentiometer Capacitancies
V
dBV
Relative Linearity(2)
Temperature Coefficient of RTOTAL
X9118-2.7(4)
-120
Absolute Linearity(1)
25°C, each pot
ppm/°C
pF
See Macro model
FN8161.1
March 25, 2005
X9118
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 1023 or (RH – RL) / 1023, single pot
(4) VCC, V+, V- must reach their final values within 1 msec of each other.
(5) n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
VCC supply current
(active)
3
mA
fSCL = 400kHz; VCC = +5.5V;
SDA = Open; (for 2-wire, Active, Read and
Volatile Write States only)
ICC2
VCC supply current
(nonvolatile write)
5
mA
fSCL = 400kHz; VCC = +5.5V;
SDA = Open; (for 2-wire, Active,
Non-volatile Write State only)
ISB
VCC current
(standby)
3
µA
VCC = +5.5V; VIN = VSS or VCC; SDA = VCC;
(for 2-wire, Standby State only)
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage
current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW voltage
-1
VCC x 0.3
V
VOL
Output LOW voltage
0.4
V
VOH
Output HIGH voltage
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Minimum Endurance
100,000
Data changes per bit per register
Data Retention
100
years
CAPACITANCE
Symbol
CIN/OUT(6)
CIN(6)
Test
Max.
Units
Test Conditions
Input/Output capacitance (SI)
8
pF
VOUT = 0V
Input capacitance (SCL, WP, A2, A1 and A0)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tr VCC(6)
tPUR(7)
tPUW(7)
Parameter
Min.
Max.
Units
0.2
50
V/ms
Power-up to Initiation of read operation
1
ms
Power-up to Initiation of write operation
50
ms
VCC Power-up Rate
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be issued.
These parameters are periodically sampled and not 100% tested.
12
FN8161.1
March 25, 2005
X9118
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
EQUIVALENT A.C. LOAD CIRCUIT
5V
3V
1533Ω
SPICE Macromodel
867Ω
RTOTAL
RL
RH
SDA OUTPUT
SDA OUTPUT
100pF
CW
CL
10pF
100pF
CL
10pF
25pF
RW
AC TIMINGHIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Min.
Max.
Units
400
kHz
fSCL
Clock Frequency
tCYC
Clock Cycle Time
2500
ns
tHIGH
Clock High Time
600
ns
tLOW
Clock Low Time
1300
ns
tSU:STA
Start Setup Time
600
ns
tHD:STA
Start Hold Time
600
ns
tSU:STO
Stop Setup Time
600
ns
tSU:DAT
SDA Data Input Setup Time
100
ns
tHD:DAT
SDA Data Input Hold Time
0
ns
tR
SCL and SDA Rise Time
300
ns
tF
SCL and SDA Fall Time
300
ns
tAA
SCL Low to SDA Data Output Valid Time
tDH
250
ns
SDA Data Output Hold Time
0
ns
TI
Noise Suppression Time Constant at SCL and SDA inputs
50
ns
tBUF
Bus Free Time (Prior to Any Transmission)
1300
ns
tSU:WPA
A0, A1 Setup Time
0
ns
tHD:WPA
A0, A1 Hold Time
0
ns
13
FN8161.1
March 25, 2005
X9118
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
tWR
High-voltage write cycle time (store instructions)
Typ.
Max.
Units
5
10
ms
XDCP TIMING
Symbol
Parameter
Min.
Max.
Units
tWRPO
Wiper response time after the third (last) power supply is stable
5
10
µs
Wiper response time after instruction issued (all load
instructions)
5
10
µs
tWRL
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Start and Stop Timing
(START)
(STOP)
tR
tF
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
14
FN8161.1
March 25, 2005
X9118
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tDH
tAA
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
RW
Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
15
FN8161.1
March 25, 2005
X9118
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable
Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V
(1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
VO
100kΩ
–
VO
+
}
}
TL072
R1
R2
10kΩ
10kΩ
+12V
10κΩ
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
16
FN8161.1
March 25, 2005
X9118
Application Circuits (Continued)
Attenuator
Filter
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
VO = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
}
Inverting Amplifier
Equivalent L-R Circuit
VS
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s
Leq
(R1 + R3) >> R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
17
FN8161.1
March 25, 2005
X9118
XX-ball BGA (X9118xxxxxxx)
a
a
l
j
m
k
b
b
f
Top View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
d
= Die Orientation mark
c
e
Side View (Bump Side Down)
Millimeters
Symbol
Package Body Dimension X
a
Package Body Dimension Y
b
Package Height
c
Package Body Thickness
d
Ball Height
e
Ball Diameter
f
Total Ball Count
g
Ball Count X Axis
h
Ball Count Y Axis
i
Pins Pitch XAxis
j
Pins Pitch Y Axis
k
Edge to Ball Center (Corner)
Distance Along X
l
Edge to Ball Center (Corner)
Distance Along Y
m
18
Min
Nom.
Inches
Max
Min
Nom.
Max
FN8161.1
March 25, 2005
X9118
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8 °
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
19
FN8161.1
March 25, 2005
X9118
ORDERING INFORMATION
X9118
Y
P
T
V
VCC Limits
Blank = 5V ±10%
-2.7 = 2.7 to 5.5V
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Package
V14 = 14-Lead TSSOP
Potentiometer Organization
Pot
T=
100kΩ
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN8161.1
March 25, 2005