X9409WV24IZ-2.7

DATASHEET
Low Noise/Low Power/2-Wire Bus Quad Digitally
Controlled Potentiometers (XDCP™)
X9409
Features
The X9409 integrates 4 digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated microcircuit.
• Four potentiometers per package
The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled by
the user through the 2-wire bus interface. Each potentiometer
has associated with it a volatile Wiper Counter Register (WCR)
and 4 nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of DR0 to
the WCR.
• 2-wire serial interface for write, read and transfer operations
of the potentiometer
The XDCP can be used as a three-terminal potentiometer or as
a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments and
signal processing.
• 100 year data retention
• 64 resistor taps
• 50Ω wiper resistance, typical at 5V
• Four nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on power-up
standby current < 1µA typical
• System VCC: 2.7V operation
• 10kΩ end-to-end resistance
• Endurance: 100,000 data changes per bit per register
• Low power CMOS
• 24 Ld TSSOP
• Pb-free (RoHS compliant)
POT 0
VCC
VSS
WP
R0
R1
R2
R3
WIPER
COUNTER
REGISTER
(WCR)
SCL
SDA
A0
A1
A2
INTERFACE
AND
CONTROL
CIRCUITRY
A3
VH0/RHO
R0
R1
VL0/
RLO
R2
R3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 2
VH2/RH2
VL2/RL2
VW0/
RWO
VW2/RW2
VW1/
RW1
VW3/RW3
8
DATA
R0
R2
R1
R3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 1
VH1/
RH1
R0
VL1/RL1
R2
R1
R3
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
Pot 3
VH3/RH3
VL3/RL3
FIGURE 1. BLOCK DIAGRAM
September 3, 2015
FN8192.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005-2006, 2015. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9409
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
POTENTIOMETER
ORGANIZATION
TEMP
(kΩ)
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
PART
MARKING
VCC LIMITS
(V)
X9409WV24IZ (No longer available,
X9409WV ZI
recommended replacement: X9409WV24IZ-2.7)
2.7 to 5.5
10
-40 to +85
24 Ld TSSOP (4.4mm)
M24.173
X9409WV24IZ-2.7
2.7 to 5.5
10
-40 to +85
24 Ld TSSOP (4.4mm)
M24.173
X9409WV24Z (No longer available,
X9409WV Z
recommended replacement: X9409WV24IZ-2.7)
2.7 to 5.5
10
-40 to +85
24 Ld TSSOP (4.4mm)
M24.173
X9409WV24Z-2.7 (No longer available,
X9409WV ZF
recommended replacement: X9409WV24IZ-2.7)
2.7 to 5.5
10
0 to +70
24 Ld TSSOP (4.4mm)
M24.173
X9409WV ZG
NOTES:
1. Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for X9409. For more information on MSL, please see tech brief TB363.
Pin Configuration
X9409
(24 LD TSSOP)
TOP VIEW
SDA
1
24
WP
A1
2
23
A2
VL1/RL1
3
22
VW0/RW0
VH1/RH1
4
21
VH0/RH0
VW1/RW1
5
20
VL0/RL0
VSS
6
19
VCC
NC
7
18
NC
VW2/RW2
8
17
VL3/RL3
VH2/RH2
9
16
VH3/RH3
VL2/RL2
10
15
VW3/RW3
SCL
11
14
A0
A3
12
13
NC
Pin Descriptions
PIN #
SYMBOL
DESCRIPTION
11
SCL
Serial Clock
1
SDA
Serial Data
14, 2, 23, 12
21, 4, 9, 16, 20, 3, 10, 17
22, 5, 8, 15
A0, A1, A2, A3
Device Address
VH0/RH0, VH1/RH1, VH2/RH2, VH3/RH3, VL0/RL0, VL1/RL1,
VL2/RL2, VL3/RL3
Potentiometer Pin (terminal equivalent)
VW0/RW0, VW1/RW1, VW2/RW2, VW3/RW3
Potentiometer Pin (wiper equivalent)
24
WP
Hardware Write Protection
19
VCC
System Supply Voltage
6
VSS
System Ground (Digital)
7, 13, 18
NC
No Connection
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FN8192.6
September 3, 2015
X9409
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the X9409.
SERIAL DATA (SDA)
The SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-O Red
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
DEVICE ADDRESS (A0, A2, A3)
The address inputs are used to set the least significant 4 bits of
the 8-bit slave address. A match in the slave address serial data
stream must be made with the address input in order to initiate
communication with the X9409. A maximum of 16 devices may
occupy the 2-wire serial bus.
Potentiometer Pins
VH0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3
The VH/RH and VL/RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
VW0/RW0 - VW3/RW3
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when low prevents nonvolatile writes to the Data
Registers.
PRINCIPLES OF OPERATION
The X9409 is a highly integrated microcircuit incorporating four
resistor arrays and their associated registers and counters and the
serial interface logic providing direct communication between the
host and the XDCP potentiometers.
Serial Interface
The X9409 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9409 will be considered a slave
device in all applications.
START CONDITION
All commands to the X9409 are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH
(tHIGH). The X9409 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command until
this condition is met.
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA while SCL is HIGH.
ACKNOWLEDGE
Acknowledge is a software convention used to provide a positive
handshake between the master and slave devices on the bus to
indicate the successful receipt of data. The transmitting device,
either the master or the slave, will release the SDA bus after
transmitting eight bits. The master generates a ninth clock cycle
and during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits of data.
The X9409 will respond with an acknowledge after recognition of
a start condition and its slave address and once again after
successful receipt of the command byte. If the command is
followed by a data byte the X9409 will respond with a final
acknowledge.
ARRAY DESCRIPTION
The X9409 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected in
series. The physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (VH/RH and VL/RL
inputs).
At both ends of each array and between each resistor segment is
a CMOS switch connected to the wiper (VW/RW) output. Within
each individual array only one switch may be turned on at a time.
These switches are controlled by the Wiper Counter Register
(WCR). The 6 bits of the WCR are decoded to select and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR can
be read and written by the host system.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods (tLOW). The SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions.
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FN8192.6
September 3, 2015
X9409
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Guidelines for Calculating
Typical Values of Bus Pull-Up
Resistors
120
100
RESISTANCE (k)
Symbol Table
RMIN =
80
RMAX =
60
VCC MAX
I OL MIN
= 1.8kΩ
tR
CBUS
MAX.
RESISTANCE
40
20
MIN.
RESISTANCE
0
0
20
40
60
80
100
120
BUS CAPACITANCE (pF)
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X9409
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SDA, SCL or any address input with respect to VSS .-1V to +7V
 V = |VH - VL | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . 4kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . 300V
Thermal Resistance
JA (°C/W) JC (°C/W)
24 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . .
71
19
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is taken at the package top center.
Analog Characteristics
SYMBOL
Across the recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
End-to-end Resistance Tolerance
Power Rating
+25°C, each pot at 5V, 2.5k
IW
Wiper Current
RW
Wiper Resistance
IW = ±3mA, VCC = 3V to 5V
Voltage On Any VH/RH or VL/RL pin
VSS = 0V
Noise
Ref: 1kHz
V TERM
-3
50
VSS
Resolution (Note 10)
Absolute Linearity (Note 7)
Vw(n)(actual) - Vw(n)(expected)
Relative Linearity (Note 8)
Vw(n + 1) - [Vw(n) + MI]
MAX
(Note 6)
UNITS
±20
%
15
mW
+3
mA
150
Ω
VCC
V
-
dBV
1.6
%
-1
+1
MI (Note 9)
-0.2
+0.2
MI (Note 9)
ppm/°C
30
Temperature Coefficient Of RTOTAL
Ratiometric Temp. Coefficient
ppm/°C
20
CH/CL/CW
Potentiometer Capacitances
See macro model
10/
IAL
RH, RL, RW Leakage Current
VIN = VSS to VCC. Device is in stand-by mode.
0.1
pF
10
µA
D.C. OPERATING CHARACTERISTICS
ICC1
VCC Supply Current (Active)
fSCL = 400kHz, SDA = open, other inputs = VSS
100
µA
ICC2
VCC Supply Current (Nonvolatile Write)
fSCL = 400kHz, SDA = open, other inputs = VSS
1
mA
ISB
VCC Current (Standby)
SCL = SDA = VCC, addr. = VSS
3
µA
ILI
Input Leakage Current
VIN = VSS to VCC
10
µA
ILO
Output Leakage Current
VOUT = VSS to VCC
10
µA
VIH
Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW Voltage
-0.5
VCC x 0.1
V
VOL
Output LOW Voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Minimum Endurance
Data Retention
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100,000
100
5
Data
changes per
bit per
register
Years
FN8192.6
September 3, 2015
X9409
Analog Characteristics
SYMBOL
Across the recommended operating conditions unless otherwise specified.
PARAMETER
MIN
(Note 6)
TEST CONDITIONS
TYP
MAX
(Note 6)
UNITS
CAPACITANCE
CI/O
(Note 10)
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
CIN
(Note 10)
Input Capacitance (A0, A1, A2, A3 and SCL)
VIN = 0V
6
pF
50
V/ms
POWER-UP TIMING
tr VCC
(Note 11)
VCC Power-Up Rate
0.2
A.C. TEST CONDITIONS
VCC x 0.1 to
VCC x 0.9
Input Pulse Levels
Input Rise and Fall Times
10ns
Input and Output Timing Level
VCC x 0.5
5V
RTOTAL
1533Ω
RH
CL
CH
SDA Output
CW
10pF
100pF
RL
10pF
25pF
RW
FIGURE 3. CIRCUIT #3 SPICE MACRO MODEL
FIGURE 2. EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING
Across recommended operating conditions.
SYMBOL
PARAMETER
MIN
(Note 6)
MAX
(Note 6)
UNITS
400
kHz
fSCL
Clock Frequency
tCYC
Clock Cycle Time
2500
ns
tHIGH
Clock High Time
600
ns
tLOW
Clock Low Time
1300
ns
tSU:STA
Start Setup Time
600
ns
tHD:STA
Start Hold Time
600
ns
tSU:STO
Stop Setup Time
600
ns
tSU:DAT
SDA Data Input Setup Time
100
ns
tHD:DAT
SDA Data Input Hold Time (Note 12)
30
ns
tR
SCL and SDA Rise Time
300
ns
tF
SCL and SDA Fall Time
300
ns
tAA
SCL Low to SDA Data Output Valid Time
900
ns
tDH
SDA Data Output Hold Time
50
ns
Noise Suppression Time Constant At SCL and SDA Inputs
50
ns
1300
ns
TI
tBUF
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Bus Free Time (Prior To Any Transmission)
6
FN8192.6
September 3, 2015
X9409
AC TIMING
Across recommended operating conditions. (Continued)
SYMBOL
tSU:WPA
WP, A0, A1, A2 and A3 Setup Time
tHD:WPA
WP, A0, A1, A2 and A3 Hold Time
MAX
(Note 6)
MIN
(Note 6)
PARAMETER
UNITS
0
ns
0
HIGH-VOLTAGE WRITE CYCLE TIMING
SYMBOL
tWR
PARAMETER
High-Voltage Write Cycle Time (Store Instructions)
TYP
MAX
(Note 6)
UNIT
5
10
ms
XDCP TIMING
SYMBOL
PARAMETER
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
tWRPO
Wiper Response Time After The Third (Last) Power Supply Is Stable
2
10
µs
tWRL
Wiper Response Time After Instruction Issued (All Load Instructions)
2
10
µs
tWRID
Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement Instruction)
2
10
µs
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
8. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a
measure of the error in step size.
9. MI = RTOT/63 or (VH - VL)/63, single pot.
10. This parameter is periodically sampled and not 100% tested.
11. Sample tested only.
12. A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
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X9409
TIMING DIAGRAMS
START and STOP Timing
(START)
(STOP)
tR
tF
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
Output Timing
SCL
SDA
tDH
tAA
Power-up Requirements
(Power-up sequencing can affect correct recall of the wiper
registers)
The preferred power-on sequence is as follows: First VCC, then
the potentiometer pins, RH, RL and RW. The VCC ramp rate
specification should be met and any glitches or slope changes in
the VCC line should be held to <100mV if possible. If VCC powers
down, it should be held below 0.1V for more than 1 second
before powering up again in order for proper wiper register recall.
Also, VCC should not reverse polarity by more than 0.5V. Recall of
wiper position will not be complete until VCC reaches its final
value.
Device Addressing
Following a start condition the master must output the address
of the slave it is accessing. The most significant four bits of the
slave address are the device type identifier (see Figure 4). For the
X9409 this is fixed as 0101[B].
DEVICE TYPE
IDENTIFIER
0
1
0
1
A3
A2
A1
A0
DEVICE ADDRESS
FIGURE 4. SLAVE ADDRESS
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X9409
The next 4 bits of the slave address are the device address. The
physical device address is defined by the state of the A0 through
A3 inputs. The X9409 compares the serial data stream with the
address input state; a successful compare of all four address bits
is required for the X9409 to respond with an acknowledge. The
A0 through A3 inputs can be actively driven by CMOS input
signals or tied to VCC or VSS.
The disabling of the inputs, during the internal nonvolatile write
operation, can be used to take advantage of the typical
nonvolatile write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command the X9409
initiates the internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition followed by
the device slave address. If the X9409 is still busy with the write
operation no ACK will be returned. If the X9409 has completed
the write operation an ACK will be returned and the master can
then proceed with the next operation.
ISSUE
START
ISSUE SLAVE
ADDRESS
ISSUE STOP
NO
YES
NO
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
FIGURE 5. ACK POLLING SEQUENCE
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I2
I1
I0
R1
R0
P1
P0
POT SELECT
FIGURE 6. INSTRUCTION BYTE FORMAT
Instruction Structure
The next byte sent to the X9409 contains the instruction and
register pointer information. The format is shown in Figure 6.
The four high order bits define the instruction. The next 2 bits (R1
and R0) select one of the four registers that is to be acted upon
when a register oriented instruction is issued. The last bits (P1,
P0) select, which one of the four potentiometers is to be affected
by the instruction.
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in Figure 7.
These two-byte instructions exchange data between the Wiper
Counter Register and one of the data registers. A transfer from a
Data Register to a Wiper Counter Register is essentially a write to
a static RAM.
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
FURTHER
OPERATION?
I3
INSTRUCTIONS
Acknowledge Polling
ACK
RETURNED?
REGISTER
SELECT
9
The response of the wiper to this action will be delayed tWRL. A
transfer from the Wiper Counter Register (current wiper position),
to a Data Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur between
one of the four potentiometers and one of its associated
registers; or it may occur globally, wherein the transfer occurs
between all of the potentiometers and one of their associated
registers.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9409; either between the host and one of the data registers or
directly between the host and the Wiper Counter Register. These
instructions are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper Counter Register
(change current wiper position of the selected pot), Read Data
Register (read the contents of the selected nonvolatile register)
and Write Data Register (write a new value to the selected Data
Register). The sequence of operations is shown in Table 1.
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9409 has
responded with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each SCL clock
pulse (tHIGH) while SDA is HIGH, the selected wiper will move one
resistor segment towards the VH/RH terminal. Similarly, for each
SCL clock pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the VL/RL terminal. A detailed
illustration of the sequence and timing for this operation are
shown in Figures 9 and 10 respectively.
FN8192.6
September 3, 2015
X9409
TABLE 1. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I3
I2
I1
I0
R1
R0
P1
P0
OPERATION
Read Wiper Counter
Register
1
0
0
1
0
0
P1
P0
Read the contents of the Wiper Counter Register pointed to by
P1 - P0
Write Wiper Counter
Register
1
0
1
0
0
0
P1
P0
Write new value to the Wiper Counter Register pointed to by P1 P0
Read Data Register
1
0
1
1
R1
R0
P1
P0
Read the contents of the Data Register pointed to by P1 - P0 and
R1 - R0
Write Data Register
1
1
0
0
R1
R0
P1
P0
Write new value to the Data Register pointed to by P1 - P0 and
R1 - R0
XFR Data Register to
Wiper Counter Register
1
1
0
1
R1
R0
P1
P0
Transfer the contents of the Data Register pointed to by P1 - P0
and R1 - R0 to its associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1
1
1
0
R1
R0
P1
P0
Transfer the contents of the Wiper Counter Register pointed to
by P1 - P0 to the Data Register pointed to by R1 - R0
Global XFR Data Registers
to Wiper Counter
Registers
0
0
0
1
R1
R0
0
0
Transfer the contents of the Data Registers pointed to by
R1 - R0 of all four pots to their respective Wiper Counter
Registers
Global XFR Wiper Counter
Registers to Data Register
1
0
0
0
R1
R0
0
0
Transfer the contents of both Wiper Counter Registers to their
respective Data Registers pointed to by R1 - R0 of all four pots
Increment/Decrement
Wiper Counter Register
0
0
1
0
0
0
P1
P0
Enable Increment/decrement of the WCR Latch pointed to by
P1 - P0
NOTE:
13. 1/0 = data is one or zero
SCL
SDA
0
S
T
A
R
T
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
0
0
P1
P0
A
C
K
S
T
O
P
FIGURE 7. 2-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
R1 R0 P1 P0
A
C
K
D5 D4
D3 D2
D1 D0
A
C
K
S
T
O
P
FIGURE 8. 10-BYTE INSTRUCTION SEQUENCE
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FN8192.6
September 3, 2015
X9409
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
P1
P0
A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
FIGURE 9. INCREMENT/ DECREMENT INSTRUCTION SEQUENCE
INC/DEC
CMD
ISSUED
tWRID
SCL
SDA
VOLTAGE OUT
VW/RW
FIGURE 10. INCREMENT/ DECREMENT TIMING LIMITS
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 11. ACKNOWLEDGE RESPONSE FROM RECEIVER
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X9409
SERIAL DATA PATH
SERIAL
BUS
INPUT
FROM INTERFACE
CIRCUITRY
REGISTER 0
C
O
U
N
T
E
R
REGISTER 1
8
REGISTER 2
VH/RH
6
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
REGISTER 3
D
E
C
O
D
E
INC/DEC
LOGIC
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
UP/DN
MODIFIED SCL
UP/DN
VL/RL
CLK
VW/RW
FIGURE 12. DETAILED POTENTIOMETER BLOCK DIAGRAM
Detailed Operation
All XDCP potentiometers share the serial interface and share a
common architecture. Each potentiometer has a Wiper Counter
Register and 4 Data Registers. A detailed discussion of the register
organization and array operation follows.
Wiper Counter Register
The X9409 contains four Wiper Counter Registers, one for each
XDCP potentiometer. The Wiper Counter Register can be envisioned
as a 6-bit parallel and serial load counter with its outputs decoded to
select one of sixty-four switches along its resistor array. The contents
of the WCR can be altered in four ways: it may be written directly by
the host via the Write Wiper Counter Register instruction (serial
load); it may be written indirectly by transferring the contents of one
of the four associated Data Registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a time by
the Increment/ Decrement instruction. Finally, it is loaded with the
contents of its Data Register zero (DR0) upon power-up.
The WCR is a volatile register; that is, its contents are lost when the
X9409 is powered down. Although the register is automatically
loaded with the value in DR0 upon power-up, it should be noted this
may be different from the value present at power-down.
Data Registers
Each potentiometer has four nonvolatile Data Registers. These
can be read or written directly by the host and data can be
transferred between any of the four Data Registers and the Wiper
Counter Register. It should be noted all operations changing data
in one of these registers is a nonvolatile operation and will take a
maximum of 10ms.
Register Descriptions
TABLE 2. DATA REGISTERS, (6-BIT), NONVOLATILE
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
(MSB)
(LSB)
Four 6-bit Data Registers for each XDCP. (sixteen 6-bit registers in
total).
{D5~D0}: These bits are for general purpose not volatile data
storage or for storage of up to four different wiper values. The
contents of Data Register 0 are automatically moved to the wiper
counter register on power-up.
TABLE 3. WIPER COUNTER REGISTER, (6-BIT), VOLATILE
WP5
WP4
WP3
WP2
WP1
WP0
V
V
V
V
V
V
(MSB)
(LSB)
One 6-bit Wiper Counter Register for each XDCP. (Four 6-bit registers
in total).
{D5~D0}: These bits specify the wiper position of the respective
XDCP. The Wiper Counter Register is loaded on power-up by the
value in Data Register R0. The contents of the WCR can be loaded
from any of the other Data Register or directly by command. The
contents of the WCR can be saved in a DR.
If the application does not require storage of multiple settings for
the potentiometer, these registers can be used as regular memory
locations that could possibly store system parameters or user
preference data.
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12
FN8192.6
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X9409
Read Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
DEVICE
ADDRESSES
0
1
A3
A2
A1
INSTRUCTION
OPCODE
S
A
C
K
A0
1
0
WCR
ADDRESSES
0
1
0
0
P1
WIPER POSITION
(SENT BY SLAVE ON SDA)
S
A
C
K
P0
0
W
P5
0
W
P4
W
P3
W
P2
W
P1
W
P0
M
A
C
K
S
T
O
P
W
P0
S
A
C
K
S
T
O
P
W
P0
M
A
C
K
S
T
O
P
Write Wiper Counter Register (WCR)
DEVICE TYPE
IDENTIFIER
S
T
A
R
T
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
INSTRUCTION
OPCODE
S
A
C
K
A0
1
0
1
WCR
ADDRESSES
0
0
0
P1
S
A
C
K
P0
WIPER POSITION
(SENT BY MASTER ON SDA)
0
W
P5
0
W
P4
W
P3
W
P2
W
P1
Read Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
DEVICE
ADDRESSES
0
1
A3
A2 A1
S
A
C
K
A0
INSTRUCTION
OPCODE
1
0
1
DR AND WCR
ADDRESSES
1
R1
R0
P1
WIPER POSITION
(SENT BY SLAVE ON SDA)
S
A
C
K
P0
0
W
P5
0
W
P4
W
P3
W
P2
W
P1
Write Data Register (DR)
S
T
A
R
T
INSTRUCTION
S
OPCODE
A
C
A3 A2 A1 A0 K 1 1 0 0
DEVICE TYPE
IDENTIFIER
0
1
0
1
WIPER POSITION
(SENT BY MASTER ON SDA)
DR AND WCR
ADDRESSES
DEVICE
ADDRESSES
S
A
C
R1 R0 P1 P0 K
0
W W W W W
P5 P4 P3 P2 P1
0
W
P0
S S
A T
C O
K P
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
INSTRUCTION
OPCODE
S
A
C
K
A0
1
1
0
DR AND WCR
ADDRESSES
1
R1
R0
P1
P0
S
A
C
K
S
T
O
P
Write Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
INSTRUCTION
OPCODE
S
A
C
K
A0
1
1
1
DR AND WCR
ADDRESSES
0
R1
R0
P1
P0
S
T
O
P
S
A
C
K
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3 A2 A1 A0
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13
S
A
C
K
INSTRUCTION
OPCODE
0
0
1
WCR
ADDRESSES
0
0
0
P1 P0
S
A
C
K
INCREMENT/DECREMENT
(SENT BY MASTER ON SDA)
I/D I/D
.
.
.
.
I/D I/D
S
T
O
P
FN8192.6
September 3, 2015
X9409
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
DEVICE TYPE
IDENTIFIER
S
T
A
R
T
0
1
DEVICE
ADDRESSES
0
1
A3
A2
A1
A0
INSTRUCTION
OPCODE
S
A
C
K
0
0
DR
ADDRESSES
0
1
R1
R0
0
0
S
A
C
K
S
T
O
P
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0
1
0
DEVICE
ADDRESSES
1
A3
A2
A1
A0
S
A
C
K
INSTRUCTION
OPCODE
1
0
0
DR
ADDRESSES
0
R1
R0
0
0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Instruction Format
NOTES:
14. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
15. “A3 ~ A0”: stands for the device addresses sent by the master.
16. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
17. “I”: stands for the increment operation, SDA held high during active SCL phase (high).
18. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
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X9409
Applications Information
Basic Configurations of Electronic Potentiometers
VR
+VR
VW/RW
I
FIGURE 13. THREE TERMINAL POTENTIOMETER; VARIABLE
VOLTAGE DIVIDER
FIGURE 14. TWO TERMINAL VARIABLE RESISTOR; VARIABLE
CURRENT
Application Circuits
VS
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
FIGURE 15. NONINVERTING AMPLIFIER
R1
FIGURE 16. VOLTAGE REGULATOR
R2
VS
VS
–
+
VO
100kΩ
–
VO
+
10kΩ
VS
FIGURE 17. OFFSET VOLTAGE ADJUSTMENT
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15
}
10kΩ
}
TL072
10kΩ
R1
R2
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
FIGURE 18. COMPARATOR WITH HYSTERESIS
FN8192.6
September 3, 2015
X9409
Application Circuits (Continued)
C
VS
+
R2
R1
VS
R
VO
+
VO
–
–
R3
R4
R2
All RS = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2RC)
VO = G VS
-1/2  G  +1/2
FIGURE 20. FILTER
FIGURE 19. ATTENUATOR
R2
C1
R2
VS
}
VS
}
R1
+
–
–
VO
+
R1
ZIN
R3
VO = G VS
G = - R2/R1
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FIGURE 22. EQUIVALENT L-R CIRCUIT
FIGURE 21. INVERTING AMPLIFIER
C
R2
–
R1
–
+
+
} RA
} RB
frequency  R1, R2, C
amplitude  RA, RB
FIGURE 23. FUNCTION GENERATOR
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X9409
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
VWx
XDCP Timing (for Increment/Decrement Instruction)
SCL
SDA
WIPER REGISTER ADDRESS
INC/DEC
INC/DEC
tWRID
VW/RW
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(ANY INSTRUCTION)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
A2, A3
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X9409
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
September 3, 2015
FN8192.6
Updated Ordering Information table on page 2.
April 20, 2015
FN8192.5
Updated Template.
Added revision history.
Removed part numbers X9409WS24I-2.7 and X9409WS24IZ-2.7 from ordering information table.
Analog Characteristics table on page 5, in ISB section: Changed max value from 1µ to 3µ.
Removed 24 Ld SOIC throughout the document.
Removed POD M24.3.
About Intersil
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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FN8192.6
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X9409
Package Outline Drawing
M24.173
24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
A
1
3
7.80 ±0.10
SEE DETAIL "X"
13
24
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
12
0.15 +0.05
-0.06
B
0.65
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
C
0.90 +0.15
-0.10
1.20 MAX
GAUGE
PLANE
SEATING PLANE
0.25 +0.05
-0.06
0.10 M C B A
0.10 C
5
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60± 0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
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FN8192.6
September 3, 2015