PCA85133 Automotive LCD driver for low multiplex rates Rev. 3 — 4 July 2014 Product data sheet 1. General description The PCA85133 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 80 segments and can easily be cascaded for larger LCD applications. The PCA85133 is compatible with most microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremental addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). For a selection of NXP LCD segment drivers, see Table 27 on page 46. 2. Features and benefits 1. AEC-Q100 compliant for automotive applications Single-chip LCD controller and driver Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing Selectable display bias configuration: static, 1⁄2, or 1⁄3 Selectable frame frequency: 82 Hz or 110 Hz Internal LCD bias generation with voltage-follower buffers 80 segment drives: Up to 40 7-segment alphanumeric characters Up to 20 14-segment alphanumeric characters Any graphics of up to 320 elements 80 4 bit RAM for display data storage Auto-incremental display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide logic LCD supply range: From 2.5 V for low-threshold LCDs Up to 8.0 V for guest-host LCDs and high-threshold twisted nematic LCDs Low power consumption 400 kHz I2C-bus interface Extended temperature range up to 95 C May be cascaded for large LCD applications (up to 5120 segments possible) The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20. PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates No external components needed Compatible with Chip-On-Glass (COG) technology Manufactured using silicon gate CMOS process 3. Ordering information Table 1. Ordering information Type number Package PCA85133U Name Description Version bare die 110 bumps; 4.16 1.07 0.40 mm PCA85133 3.1 Ordering options Table 2. Ordering options Product type number Orderable part number Sales item (12NC) Delivery form[1] IC revision PCA85133U/2DA/Q1 PCA85133U/2DA/Q1Z 935290456033 chip with hard bumps in tray 1 PCA85133U/2DB/Q1 PCA85133U/2DB/Q1Z 935290457033 chip with soft bumps in tray 1 [1] Bump hardness, see Table 24 on page 43. 4. Marking Table 3. PCA85133 Product data sheet Marking codes Type number Marking code PCA85133U/2DA/Q1 PC85133-1 PCA85133U/2DB/Q1 PC85133-1 All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 5. Block diagram 6WR6 %3 %3 %3 %3 9/&' %$&.3/$1( 2873876 /&' 92/7$*( 6(/(&725 ',63/$<6(*0(172873876 ',63/$<5(*,67(5 287387%$1.6(/(&7 $1'%/,1.&21752/ ',63/$< &21752/ /&'%,$6 *(1(5$725 966 3&$ &/. 6<1& &/2&.6(/(&7 $1'7,0,1* %/,1.(5 7,0(%$6( 26&,//$725 32:(521 5(6(7 26& )) 6&/ ,1387 ),/7(56 6'$ :5,7('$7$ &21752/ ,&%86 &21752//(5 6$ Fig 1. &200$1' '(&2'( ',63/$< 5$0 '$7$32,17(5$1' $872,1&5(0(17 68%$''5(66 &2817(5 6'$$&. 9'' $ $ $ DDD Block diagram of PCA85133 PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 3 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 6. Pinning information ' 6 ' ' 6 ' 6.1 Pinning \ [ 6 ' %3 %3 6 9/&' 966 26& )) $ $ $ 6$ 6<1& 9'' &/. 6&/ 6'$ 6 %3 %3 6'$$&. ' 6 3&$ DDD Viewed from active side. For mechanical details, see Figure 25. Fig 2. Pin configuration for PCA85133 6.2 Pin description Table 4. Pin description overview Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified. Symbol Pin Description SDAACK 1 to 3 I2C-bus acknowledge output SDA 4 to 6 I2C-bus serial data input SCL 7 to 9 I2C-bus serial clock input CLK 10 clock input and output VDD 11 to 13 supply voltage SYNC 14 cascade synchronization input and output OSC 15 oscillator select FF 16 frame frequency select A0, A1, and A2 17 to 19 subaddress input SA0 20 I2C-bus slave address input VSS[1] 21 to 23 ground supply voltage VLCD 24 to 26 LCD supply voltage BP2, BP0, BP3, and BP1 27, 28, 109 and 110 LCD backplane output S0 to S79 29 to 108 LCD segment output D1 to D9 - dummy pins [1] PCA85133 Product data sheet The substrate (rear side of the die) is at VSS potential and should be electrically isolated. All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 4 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 7. Functional description The PCA85133 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 80 segments. The display configurations possible with the PCA85133 depend on the required number of active backplane outputs. A selection of display configurations is given in Table 5. All of the display configurations given in Table 5 can be implemented in a typical system as shown in Figure 4. GRWPDWUL[ VHJPHQWZLWKGRW VHJPHQWZLWKGRWDQGDFFHQW DDD Fig 3. Example of displays suitable for PCA85133 Table 5. Selection of possible display configurations Number of Backplanes PCA85133 Product data sheet Icons Digits/Characters 7-segment[1] 14-segment[2] Dot matrix/ Elements 4 320 40 20 320 (4 80) 3 240 30 15 240 (3 80) 2 160 20 10 160 (2 80) 1 80 10 5 80 (1 80) [1] 7 segment display has 8 elements including the decimal point. [2] 14 segment display has 16 elements including decimal point and accent dot. All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 5 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 9'' 9/&' 5 WU &E 9'' 9/&' 6'$$&. VHJPHQWGULYHV 6'$ +267 0,&52 &21752//(5 /&'3$1(/ XSWR HOHPHQWV 3&$ 6&/ )) EDFNSODQHV 26& $ $ $ 6$ 966 966 DDD Fig 4. Typical system configuration The host microcontroller maintains the 2-line I2C-bus communication channel with the PCA85133. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are the power supplies (VDD, VSS, and VLCD) and the LCD panel chosen for the application. 7.1 Power-on reset At power-on the PCA85133 resets to the following starting conditions: • • • • • • • All backplane and segment outputs are set to VLCD The selected drive mode is 1:4 multiplex with 1⁄3 bias Blinking is switched off Input and output bank selectors are reset The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) The display is disabled (bit E = 0, see Table 12) Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider of three impedances connected between pins VLCD and VSS. The center impedance is bypassed by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is selected. 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 6 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates VLCD and the resulting discrimination ratios (D) are given in Table 6. Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast. Table 6. Biasing characteristics LCD drive mode Number of: LCD bias Backplanes Levels configuration V off RMS ------------------------V LCD V on RMS -----------------------V LCD V on RMS D = -----------------------V off RMS static 1 2 static 0 1 1:2 multiplex 2 3 1⁄ 2 0.354 0.791 2.236 1:2 multiplex 2 4 1⁄ 3 0.333 0.745 2.236 1:3 multiplex 3 4 1⁄ 3 0.333 0.638 1.915 4 1⁄ 3 0.333 0.577 1.732 1:4 multiplex 4 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth(off). Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------- , where the values for a are 1+a a = 1 for 1⁄2 bias a = 2 for 1⁄3 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on RMS = V LCD a 2 + 2a + n -----------------------------2 n 1 + a (1) where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off RMS = V LCD a 2 – 2a + n -----------------------------2 n 1 + a (2) Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on RMS D = ---------------------- = V off RMS PCA85133 Product data sheet 2 a + 2a + n --------------------------2 a – 2a + n All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 (3) © NXP Semiconductors N.V. 2014. All rights reserved. 7 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1⁄ 2 bias is 1⁄ 2 21 bias is ---------- = 1.528 . 3 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: • 1:3 multiplex (1⁄2 bias): V LCD = 6 V off RMS = 2.449V off RMS 4 3 - = 2.309V off RMS • 1:4 multiplex (1⁄2 bias): V LCD = --------------------3 These compare with V LCD = 3V off RMS when 1⁄3 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. 7.3.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see Figure 5. For a good contrast performance, the following rules should be followed: V on RMS V th on (4) V off RMS V th off (5) Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection of a, n (see Equation 1 to Equation 3) and the VLCD voltage. Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation voltage Vsat. It is important to match the module properties to those of the driver in order to achieve optimum performance. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 8 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 5HODWLYH7UDQVPLVVLRQ 9WKRII 2)) 6(*0(17 9WKRQ *5(< 6(*0(17 9506>9@ 21 6(*0(17 DDD Fig 5. PCA85133 Product data sheet Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 9 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 6. 7IU /&'VHJPHQWV 9/&' %3 966 VWDWH RQ 9/&' VWDWH RII 6Q 966 9/&' 6Q 966 D:DYHIRUPVDWGULYHU 9/&' VWDWH 9 9/&' 9/&' VWDWH 9 9/&' E5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn + 1)(t) VBP0(t). Voff(RMS) = 0 V. Fig 6. PCA85133 Product data sheet Static drive mode waveforms All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 10 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA85133 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 7 and Figure 8. 7IU 9/&' %3 /&'VHJPHQWV 9/&' 966 VWDWH 9/&' %3 VWDWH 9/&' 966 9/&' 6Q 966 9/&' 6Q 966 D:DYHIRUPVDWGULYHU 9/&' 9/&' VWDWH 9 9/&' 9/&' 9/&' 9/&' VWDWH 9 9/&' 9/&' E5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.354VLCD. Fig 7. PCA85133 Product data sheet Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 11 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 7IU 9/&' %3 %3 /&'VHJPHQWV 9/&' 9/&' 966 VWDWH 9/&' 9/&' VWDWH 9/&' 966 9/&' 6Q 9/&' 9/&' 966 9/&' 6Q 9/&' 9/&' 966 D:DYHIRUPVDWGULYHU 9/&' 9/&' VWDWH 9/&' 9 9/&' 9/&' 9/&' 9/&' 9/&' 9/&' VWDWH 9 9/&' 9/&' 9/&' E5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.333VLCD. Fig 8. PCA85133 Product data sheet Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 12 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 9. 7IU %3 9/&' 9/&' /&'VHJPHQWV 9/&' 966 VWDWH 9/&' %3 %3 6Q 6Q 6Q VWDWH 9/&' 9/&' 966 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' 966 D:DYHIRUPVDWGULYHU 9/&' 9/&' 9/&' VWDWH 9 9/&' 9/&' 9/&' 9/&' 9/&' 9/&' VWDWH 9 9/&' 9/&' 9/&' E5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.333VLCD. Fig 9. PCA85133 Product data sheet Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 13 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 10. 7IU %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 VWDWH 9/&' 9/&' 9/&' 9 9/&' 9/&' 9/&' VWDWH 9/&' 9/&' 9/&' 9 9/&' 9/&' 9/&' /&'VHJPHQWV VWDWH VWDWH D:DYHIRUPVDWGULYHU E5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.333VLCD. Fig 10. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 14 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCA85133 are timed by a frequency fclk which either is derived from the built-in oscillator frequency fosc: f osc f clk = ------64 (6) or equals an external clock frequency fclk(ext): (7) f clk = f clk ext 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to VSS. In this case the output from pin CLK provides the clock signal for any cascaded PCA85133 in the system. 7.5.2 External clock Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the external clock input. Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 7.6 Timing and frame frequency The clock frequency fclk determines the LCD frame frequency ffr and is calculated as follows: f clk f fr = ------24 (8) The internal clock frequency fclk can be selected using pin FF. As a result 2 frame frequencies are available: 82 Hz or 110 Hz (typical), see Table 7. Table 7. LCD frame frequencies Pin FF tied to[1] Typical clock frequency (Hz) LCD frame frequency (Hz) VDD 1970 82 VSS 2640 110 [1] FF has no effect when an external clock is used but must not be left floating. The timing of the PCA85133 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between all the PCA85133 in the system. 7.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 15 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 7.8 Segment outputs The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display register. When less than 80 segment outputs are required the unused segment outputs must be left open-circuit. 7.9 Backplane outputs The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated in accordance with the selected LCD drive mode. • In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD. If less than four backplane outputs are required the unused outputs can be left open-circuit. • In 1:3 multiplex drive mode: BP3 carries the same signal as BP1; therefore, these two adjacent outputs can be tied together to give enhanced drive capabilities. • In 1:2 multiplex drive mode: BP0 and BP2, respectively, BP1 and BP3 carry the same signals and can also be paired to increase the drive capabilities. • In static drive mode: The same signal is carried by all four backplane outputs; and they can be connected in parallel for very high drive requirements. 7.10 Display RAM The display RAM is a static 80 4 bit RAM which stores LCD data. There is a one-to-one correspondence between • the bits in the RAM bitmap and the LCD elements • the RAM columns and the segment outputs • the RAM rows and the backplane outputs. A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. The display RAM bit map, Figure 11, shows rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 16 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates FROXPQV GLVSOD\5$0DGGUHVVHVVHJPHQWRXWSXWV6 URZV GLVSOD\5$0URZV EDFNSODQHRXWSXWV %3 DDD The display RAM bitmap shows the direct relationship between the display RAM addresses and the segment outputs and between the bits in a RAM word and the backplane outputs. Fig 11. Display RAM bitmap When display data is transmitted to the PCA85133, the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and depending on the current multiplex drive mode the bits are stored singularly, in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment display showing all drive modes is given in Figure 12; the RAM filling organization depicted applies equally to other LCD types. The following applies to Figure 12: • In static drive mode the eight transmitted data bits are placed into row 0 as one byte. • In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as four successive 2-bit RAM words. • In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address, but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted (see Section 7.10.3). • In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 as two successive 4-bit RAM words. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 17 of 54 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx /&'VHJPHQWV 6Q 6Q VWDWLF E F URZV GLVSOD\5$0 URZVEDFNSODQH RXWSXWV%3 '3 D 6Q %3 F 6Q '3 G 6Q D E 6Q %3 F E %3 J H %3 F G Q Q F [ [ [ E [ [ [ D [ [ [ I [ [ [ J [ [ [ H [ [ [ G [ [ [ '3 [ [ [ 06% /6% F E D I J H G '3 URZV GLVSOD\5$0 URZVEDFNSODQH RXWSXWV%3 Q Q Q Q D E [ [ I J [ [ H F [ [ G '3 [ [ 06% D E /6% I J H F G '3 Q URZV GLVSOD\5$0 E URZVEDFNSODQH '3 RXWSXWV%3 F [ Q Q D G J [ I H [ [ 06% /6% E '3 F D G J I H '3 %3 Q URZV GLVSOD\5$0 D URZVEDFNSODQH F %3 RXWSXWV%3 E '3 Q I H J G 06% D F E '3 I /6% H J G DDM x = data bit unchanged Fig 12. Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus PCA85133 18 of 54 © NXP Semiconductors N.V. 2014. All rights reserved. I PXOWLSOH[ Q FROXPQV GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWVV E\WH E\WH E\WH E\WH E\WH D 6Q 6Q %3 '3 G Q FROXPQV GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWVV E\WH E\WH E\WH J H Q %3 I PXOWLSOH[ Q Automotive LCD driver for low multiplex rates Rev. 3 — 4 July 2014 All information provided in this document is subject to legal disclaimers. E H Q FROXPQV GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWVV E\WH E\WH J 6Q Q %3 I PXOWLSOH[ %3 6Q 6Q G 6Q 6Q 6Q J H WUDQVPLWWHGGLVSOD\E\WH FROXPQV GLVSOD\5$0DGGUHVVVHJPHQWRXWSXWVV E\WH I 6Q GLVSOD\5$0ILOOLQJRUGHU D 6Q 6Q /&'EDFNSODQHV NXP Semiconductors PCA85133 Product data sheet GULYHPRGH PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 7.10.1 Data pointer The addressing mechanism for the display RAM is realized using a data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Table 13). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 12. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: • • • • In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two If an I2C-bus data access is terminated early then the state of the data pointer is unknown. Consequently, the data pointer must be rewritten prior to further RAM accesses. 7.10.2 Subaddress counter The storage of display data is determined by the content of the subaddress counter. Storage is allowed only when the content of the subaddress counter match with the hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined by the device-select command (see Table 14). If the content of the subaddress counter and the hardware subaddress do not match, then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCA85133 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character. The hardware subaddress must not be changed whilst the device is being accessed on the I2C-bus interface. 7.10.3 RAM writing in 1:3 multiplex drive mode In 1:3 multiplex drive mode, the RAM is written as shown in Table 8 (see Figure 12 as well). Table 8. Standard RAM filling in 1:3 multiplex drive mode Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display. PCA85133 Product data sheet Display RAM bits (rows)/ backplane outputs (BPn) Display RAM addresses (columns)/segment outputs (Sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 : 1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 : 2 a5 a2 - b5 b2 - c5 c2 - d5 : 3 - - - - - - - - - - : All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 19 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates If the bit at position BP2/S2 would be written by a second byte transmitted, then the mapping of the segment bits would change as illustrated in Table 9. Table 9. Entire RAM filling by rewriting in 1:3 multiplex drive mode Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display. Display RAM bits (rows)/ backplane outputs (BPn) Display RAM addresses (columns)/segment outputs (Sn) 0 1 2 0 a7 a4 a1/b7 b4 b1/c7 c4 1 a6 a3 a0/b6 b3 2 a5 a2 b5 b2 3 - - - - 3 4 5 6 7 8 9 : c1/d7 d4 d1/e7 e4 : b0/c6 c3 c0/d6 d3 d0/e6 e3 : c5 c2 d5 d2 e5 e2 : - - - - - - : In the case described in Table 9 the RAM has to be written entirely and BP2/S2, BP2/S5, BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a combination of writing and rewriting the RAM like follows: • In the first write to the RAM, bits a7 to a0 are written. • In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7 and b6. • In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and c6. Depending on the method of writing to the RAM (standard or entire filling by rewriting), some elements remain unused or can be used, but it has to be considered in the module layout process as well as in the driver software design. 7.10.4 Writing over the RAM address boundary In all multiplex drive modes, depending on the setting of the data pointer, it is possible to fill the RAM over the RAM address boundary. If the PCA85133 is part of a cascade the additional bits fall into the next device that also generates the acknowledge signal. If the PCA85133 is a single device or the last device in a cascade the additional bits will be discarded and no acknowledge signal will be generated. 7.10.5 Output bank selector The output bank selector (see Table 15) selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the selected LCD drive mode in operation and on the instant in the multiplex sequence. • In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3 • In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially • In 1:2 multiplex mode, rows 0 and 1 are selected • In static mode, row 0 is selected The PCA85133 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 20 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.10.6 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see Table 15). The input bank selector functions independently to the output bank selector. 7.11 Blinking The display blink capabilities of the PCA85133 are very versatile. The whole display can blink at frequencies selected by the blink-select command (see Table 16). The blink frequencies are derived from the clock frequency. The ratios between the clock and blink frequencies depend on the blink mode selected (see Table 10). Table 10. Blink frequencies Blink mode Operating mode ratio Blink frequency with respect to fclk (typical) Unit fclk = 1.970 kHz fclk = 2.640 kHz off - blinking off blinking off Hz 1 f clk -------768 2.5 3.5 Hz 2 f clk ----------1536 1.3 1.7 Hz 3 f clk ----------3072 0.6 0.9 Hz An additional feature is for an arbitrary selection of LCD segments to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command. In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can blink by selectively changing the display RAM data at fixed time intervals. If the entire display can blink at a frequency other then the typical blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 12). 7.12 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. The commands available to the PCA85133 are defined in Table 11. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 21 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates Table 11. Definition of commands Command Operation code Reference Bit 7 6 5 4 3 2 1 mode-set 1 1 0 0 E B M[1:0] load-data-pointer 0 P[6:0] device-select 1 1 1 0 0 A[2:0] bank-select 1 1 1 1 1 0 I blink-select 1 1 1 1 0 AB BF[1:0] Mode-set command bit description Bit Symbol Value Description 7 to 4 - 1100 fixed value 3 E Table 14 O Table 15 Table 16 display status[1] 0 disabled (blank)[2] 1 enabled LCD bias configuration[3] B 1 to 0 Table 12 Table 13 Table 12. 2 0 0 1⁄ 3 bias 1 1⁄ 2 bias M[1:0] LCD drive mode selection 01 static; 1 backplane 10 1:2 multiplex; 2 backplanes 11 1:3 multiplex; 3 backplanes 00 1:4 multiplex; 4 backplanes [1] The possibility to disable the display allows implementation of blinking under external control. [2] The display is disabled by setting all backplane and segment outputs to VLCD. [3] Not applicable for static drive mode. Table 13. Load-data-pointer command bit description See Section 7.10.1. Bit Symbol Value Description 7 - 0 fixed value 6 to 0 P[6:0] 0000000 to 1001111 data pointer 7-bit binary value of 0 to 79, transferred to the data pointer to define one of 80 display RAM addresses Table 14. Device-select command bit description See Section 7.10.2. Bit Symbol Value Description 7 to 3 - 11100 fixed value 2 to 0 A[2:0] 000 to 111 device selection 3-bit binary value of 0 to 7, transferred to the subaddress counter to define one of 8 hardware subaddresses PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 22 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates Table 15. Bank-select command bit description[1] See Section 7.10.5 and Section 7.10.6. Bit Symbol Value Description 7 to 2 - 111110 fixed value 1 I Static input bank selection: storage of arriving display data 0 1 0 [1] 1:2 multiplex O RAM row 0 RAM rows 0 and 1 RAM row 2 RAM rows 2 and 3 output bank selection: retrieval of LCD display data 0 RAM row 0 RAM rows 0 and 1 1 RAM row 2 RAM rows 2 and 3 The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes. Table 16. Blink-select command bit description See Section 7.11. Bit Symbol Value Description 7 to 3 - 11110 fixed value 2 AB 1 to 0 blink mode selection[1] 0 normal blinking 1 blinking by alternating display RAM banks blink frequency selection[2] BF[1:0] 00 off 01 1 10 2 11 3 [1] Normal blinking can only be selected in multiplex drive mode 1:3 or 1:4. [2] For the blink frequencies, see Table 10. 7.13 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers and coordinates their effects. The display controller also loads the display data into the display RAM as required by the storage order. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 23 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 8. Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. By connecting pin SDAACK to pin SDA on the PCA85133, the SDA line becomes fully I2C-bus compatible. In COG applications where the track resistance from the SDAACK pin to the system SDA line can be significant, possibly a voltage divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a consequence it may be possible that the acknowledge generated by the PCA85133 can’t be interpreted as logic 0 by the master. In COG applications where the acknowledge cycle is required, it is therefore necessary to minimize the track resistance from the SDAACK pin to the system SDA line to guarantee a valid LOW level. By separating the acknowledge output from the serial data line (having the SDAACK open circuit) design efforts to generate a valid acknowledge level can be avoided. However, in that case the I2C-bus master has to be set up in such a way that it ignores the acknowledge cycle.2 The following definition assumes SDA and SDAACK are connected and refers to the pair as SDA. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 13). 6'$ 6&/ GDWDOLQH VWDEOH GDWDYDOLG FKDQJH RIGDWD DOORZHG PED Fig 13. Bit transfer 8.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P). 2. For further information, please consider the NXP application note: Ref. 1 “AN10170”. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 24 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates The START and STOP conditions are shown in Figure 14. 6'$ 6'$ 6&/ 6&/ 6 3 67$57FRQGLWLRQ 6723FRQGLWLRQ PEF Fig 14. Definition of START and STOP conditions 8.3 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 15. 0$67(5 75$160,77(5 5(&(,9(5 6/$9( 5(&(,9(5 6/$9( 75$160,77(5 5(&(,9(5 0$67(5 75$160,77(5 0$67(5 75$160,77(5 5(&(,9(5 6'$ 6&/ PJD Fig 15. System configuration 8.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is shown in Figure 16. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 25 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates GDWDRXWSXW E\WUDQVPLWWHU QRWDFNQRZOHGJH GDWDRXWSXW E\UHFHLYHU DFNQRZOHGJH 6&/IURP PDVWHU 6 FORFNSXOVHIRU DFNQRZOHGJHPHQW 67$57 FRQGLWLRQ PEF Fig 16. Acknowledgement on the I2C-bus 8.5 I2C-bus controller The PCA85133 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCA85133 are the acknowledge signals from the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data, and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1, and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that no two devices with a common I2C-bus slave address have the same hardware subaddress. 8.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 8.7 I2C-bus protocol Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the PCA85133. The entire I2C-bus slave address byte is shown in Table 17. Table 17. I2C slave address byte Slave address Bit 7 6 5 4 3 2 1 MSB 0 0 LSB 1 1 1 0 0 SA0 R/W The PCA85133 is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte that a PCA85133 will respond to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1). Having two reserved slave addresses allows the following on the same I2C-bus: PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 26 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates • Up to 16 PCA85133 on the same I2C-bus for very large LCD applications • The use of two types of LCD multiplex drive modes on the same I2C-bus The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the available PCA85133 slave addresses. All PCA85133 with the same SA0 level acknowledge in parallel to the slave address. All PCA85133 with the alternative SA0 level ignore the whole I2C-bus transfer. 5: VODYHDGGUHVV FRQWUROE\WH 6 & 5 6 $ $ 2 6 5$0FRPPDQGE\WH / 6 3 % 0 $ 6 % (;$03/(6 DWUDQVPLWWZRE\WHVRI5$0GDWD 6 6 $ $ $ 5$0'$7$ $ $ &200$1' $ $ &200$1' $ 3 $ &200$1' $ $ 5$0'$7$ $ 5$0'$7$ $ 3 EWUDQVPLWWZRFRPPDQGE\WHV 6 6 $ $ FWUDQVPLWRQHFRPPDQGE\WHDQGWZR5$0GDWHE\WHV 6 6 $ $ 5$0'$7$ $ 3 PJO Fig 17. I2C-bus protocol After acknowledgement, the control byte is sent, defining if the next byte is a RAM or command information. The control byte also defines if the next byte is a control byte or further RAM or command data (see Figure 18 and Table 18). In this way it is possible to configure the device and then fill the display RAM with little overhead. 06% &2 56 /6% QRWUHOHYDQW PJO Fig 18. Control byte format PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 27 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates Table 18. Control byte description Bit Symbol 7 CO 6 Value Description continue bit 0 last control byte 1 control bytes continue RS register selection 0 command register 1 5 to 0 - data register not relevant The command bytes and control bytes are also acknowledged by all addressed PCA85133 connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated. The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed PCA85133. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be asserted to RESTART an I2C-bus access. 9. Internal circuitry 9'' 9'' 966 966 6$&/.6<1&26& ))$$$ 6&/6'$6'$$&. 966 9/&' 9/&' 966 966 %3%3%3 %36WR6 DDM Fig 19. Device protection diagram PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 28 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 10. Safety notes CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. CAUTION Semiconductors are light sensitive. Exposure to light sources can cause the IC to malfunction. The IC must be protected against light. The protection must be applied to all sides of the IC. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 29 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 11. Limiting values Table 19. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Max Unit +6.5 V 0.5 +9.0 V 0.5 +6.5 V 0.5 +9.0 V input current 10 +10 mA IO output current 10 +10 mA IDD supply current 50 +50 mA ISS ground supply current 50 +50 mA IDD(LCD) LCD supply current 50 +50 mA Ptot total power dissipation - 400 mW P/out power dissipation per output - 100 mW Human Body Model [2] - 4500 V Machine Model [3] - 250 V - 200 mA 65 +150 C 40 +95 C supply voltage VLCD LCD supply voltage Vi(n) voltage on any input VDD related inputs Vo(n) voltage on any output VLCD related outputs II electrostatic discharge voltage Ilu latch-up current [4] Tstg storage temperature [5] Tamb ambient temperature [1] Product data sheet Min 0.5 VDD VESD PCA85133 Conditions operating device Stresses above these values listed may cause permanent damage to the device. [2] Pass level; Human Body Model (HBM) according to Ref. 8 “JESD22-A114”. [3] Pass level; Machine Model (MM), according to Ref. 9 “JESD22-A115”. [4] Pass level; latch-up testing, according to Ref. 10 “JESD78” at maximum ambient temperature (Tamb(max)). [5] According to the store and transport requirements (see Ref. 13 “UM10569”) the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 30 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 12. Static characteristics Table 20. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +95 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies supply voltage VDD VLCD LCD supply voltage VPOR power-on reset voltage IDD supply current IDD(LCD) LCD supply current VLCD 6.5 V 1.8 - 5.5 V VLCD > 6.5 V 2.5 - 5.5 V VDD < 2.5 V 2.5 - 6.5 V VDD 2.5 V 2.5 - 8.0 V 1.0 1.3 1.6 V fclk(ext) = 1536 Hz; see Figure 20 [1] - 3 6 A fclk(ext) = 1536 Hz; see Figure 20 [1] - 22 45 A Logic VI input voltage VSS 0.5 - VDD + 0.5 V VIH HIGH-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, FF 0.7VDD - VDD V VIL LOW-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, FF VSS - 0.3VDD V VOH HIGH-level output voltage 0.8VDD - - V VOL LOW-level output voltage - - 0.2VDD V IOH HIGH-level output current on pin CLK; VOH = 4.6 V; VDD = 5 V +1 - - mA IOL LOW-level output current on pin CLK, SYNC; VOL = 0.4 V; VDD = 5 V - - 1 mA IL leakage current on pins OSC, CLK, SCL, SDA, A0 to A2, SA0, FF; VI = VDD or VSS 1 - +1 A CI input capacitance - - 7 pF [3] I2C-bus[2] Input on pins SDA and SCL VI input voltage VSS 0.5 - 5.5 V VIH HIGH-level input voltage 0.7VDD - 5.5 V VIL LOW-level input voltage VSS - 0.3VDD V - - 7 pF VOL = 0.4 V; VDD = 5 V +3 - - mA CI input capacitance IOL(SDA) LOW-level output current on pin SDA [3] LCD outputs VO output voltage variation on pins BP0 to BP3; Cbpl = 35 nF 100 - +100 mV on pins S0 to S79; Csgm = 5 nF 100 - +100 mV RO output resistance VLCD = 5 V on pins BP0 to BP3 [4] - 1.5 10 k on pins S0 to S79 [4] - 6.0 13.5 k [1] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [2] The I2C-bus interface of PCA85133 is 5 V tolerant. [3] Not tested, design specification only. [4] Outputs measured individually and sequentially. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 31 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates DDD ,'' $ ,''/&' $ IFONH[WN+] Conditions: VDD = 5.5 V; VLCD = 8 V; Tamb = 27 C; all RAM filled with 0. (1) IDD(LCD). (2) IDD. Fig 20. Current consumption with respect to external clock frequency PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 32 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 13. Dynamic characteristics Table 21. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +95 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Clock Internal: output pin CLK clock frequency fclk frame frequency ffr FF = VDD [1][2] 1440 1970 2640 Hz FF = VSS [1][2] 1920 2640 3600 Hz FF = VDD 60 82 110 Hz FF = VSS 80 110 150 Hz 800 - 5000 Hz External: input pin CLK [2] fclk(ext) external clock frequency tclk(H) HIGH-level clock time 90 - - s tclk(L) LOW-level clock time 90 - - s Synchronization: input pin SYNC tPD(SYNC_N) SYNC propagation delay - 30 - ns tSYNC_NL SYNC LOW time 1 - - s - - 30 s Outputs: pins BP0 to BP3 and S0 to S79 tPD(drv) I2C-bus: driver propagation delay VLCD = 5 V timing[3] Pin SCL fSCL SCL clock frequency - - 400 kHz tHIGH HIGH period of the SCL clock 0.6 - - s tLOW LOW period of the SCL clock 1.3 - - s tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 33 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates Table 21. Dynamic characteristics …continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +95 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - s tSU;STO set-up time for STOP condition 0.6 - - s tHD;STA hold time (repeated) START condition 0.6 - - s tSU;STA set-up time for a repeated START condition 0.6 - - s tr rise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 s fSCL < 125 kHz - - 1.0 s - - 0.3 s - - 400 pF - - 50 ns tf fall time of both SDA and SCL signals Cb capacitive load for each bus line tw(spike) spike pulse width on bus [1] Typical output duty cycle of 50 %. [2] The corresponding frame frequency is [3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. For I2C-bus timings see Figure 22. f clk f fr = -------. 24 I&/. WFON+ WFON/ 9'' &/. 9'' 9'' 6<1& 9'' W3'6<1&B1 W6<1&B1/ 9 %3WR%3 DQG6WR6 9'' 9 9 W3'GUY DDJ Fig 21. Driver timing waveforms PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 34 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 6'$ W%8) W/2: WI 6&/ W+'67$ WU W+''$7 W+,*+ W68'$7 6'$ W6867$ W68672 PJD Fig 22. I2C-bus timing waveforms PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 35 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 14. Application information 14.1 Cascaded operation In large display configurations up to 16 PCA85133 can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable I2C-bus slave address (SA0). Table 22. Addressing cascaded PCA85133 Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device 1 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 2 1 1 1 1 7 0 0 0 8 0 0 1 9 0 1 0 10 0 1 1 11 1 0 0 12 1 0 1 13 1 1 0 14 1 1 1 15 When cascaded PCA85133 are synchronized, they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCA85133 of the cascade contribute additional segment outputs. The backplanes can either be connected together to enhance the drive capability or some can be left open-circuit (such as the ones from the slave in Figure 23) or just some of the master and some of the slave will be taken to facilitate the layout of the display. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 36 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 6'$$&. 9'' 9/&' 6'$ VHJPHQWGULYHV 6&/ 6<1& 3&$ &/. %3WR%3 RSHQFLUFXLW 26& )) /&'3$1(/ $ $ $ 6$ 966 XSWR HOHPHQWV 9/&' 9'' 5 +267 0,&52 352&(6625 0,&52 &21752//(5 6'$$&. WU &E 9'' 9/&' VHJPHQWGULYHV 6'$ 6&/ 6<1& 3&$ &/. EDFNSODQHV %3WR%3 26& )) $ $ $ 966 6$ 966 DDD (1) Is master (OSC connected to VSS). (2) Is slave (OSC connected to VDD). Fig 23. Cascaded PCA85133 configuration For display sizes that are not multiple of 320 elements, a mixed cascaded system can be considered containing only devices like PCA85133 and PCA85132. Depending on the application, one must take care of the software command and pin connection compatibility. Only one master but multiple slaves are allowed in a cascade. All devices in the cascade have to use the same clock whether it is supplied externally or provided by the master. The SYNC line is provided to maintain the correct synchronization between all cascaded PCA85133. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by the definition of a multiplex drive mode when PCA85133 with different SA0 levels are cascaded). SYNC is organized as an input/output pin; The output selection is realized as an open-drain driver with an internal pull-up resistor. A PCA85133 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCA85133 to assert SYNC. The timing relationships between the backplane waveforms and the SYNC signal for the various drive modes of the PCA85133 are shown in Figure 24. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 37 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 7IU IIU %3 6<1& DVWDWLFGULYHPRGH %3 ELDV %3 ELDV 6<1& EPXOWLSOH[GULYHPRGH %3 ELDV 6<1& FPXOWLSOH[GULYHPRGH %3 ELDV 6<1& GPXOWLSOH[GULYHPRGH PJO Fig 24. Synchronization of the cascade for the various PCA85133 drive modes The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, then the device will not be able to synchronize properly. This is particularly applicable to COG applications. 15. Test information 15.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 38 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 16. Bare die outline %DUHGLHEXPSV[[PP 3&$ ' ; \ [ ( 3& < $ E $ H $ H / GHWDLO< GHWDLO; VFDOH 'LPHQVLRQV 8QLW PP PP $ $ $ E ' ( H H / PD[ QRP PLQ 1RWH 'LPHQVLRQQRWGUDZQWRVFDOH SFDBGR 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 3&$ (XURSHDQ SURMHFWLRQ ,VVXHGDWH Fig 25. Bare die outline of PCA85133 PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 39 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates Table 23. Bump locations All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 25. PCA85133 Product data sheet Symbol Bump X (m) SDAACK 1 1022.67 436.5 Y (m) Description SDAACK 2 968.67 436.5 SDAACK 3 914.67 436.5 SDA 4 712.17 436.5 SDA 5 658.17 436.5 SDA 6 604.17 436.5 SCL 7 433.17 436.5 SCL 8 379.17 436.5 SCL 9 325.17 436.5 CLK 10 173.52 436.5 clock input/output VDD 11 61.47 436.5 supply voltage VDD 12 7.47 436.5 VDD 13 46.53 436.5 SYNC 14 149.58 436.5 cascade synchronization input/output OSC 15 262.08 436.5 oscillator select [1] I2C-bus acknowledge output [1] I2C-bus serial data input I2C-bus serial clock input FF 16 345.78 436.5 frame frequency select A0 17 429.48 436.5 subaddress input A1 18 513.18 436.5 A2 19 596.88 436.5 SA0 20 680.58 436.5 I2C-bus slave address input; bit 0 VSS 21 765.63 436.5 ground supply voltage VSS 22 819.63 436.5 VSS 23 873.63 436.5 VLCD 24 979.83 436.5 VLCD 25 1033.83 436.5 VLCD 26 1087.83 436.5 BP2 27 1176.03 436.5 BP0 28 1230.03 436.5 S0 29 1284.03 436.5 S1 30 1338.03 436.5 S2 31 1392.03 436.5 S3 32 1446.03 436.5 S4 33 1500.03 436.5 S5 34 1554.03 436.5 S6 35 1608.03 436.5 S7 36 1662.03 436.5 S8 37 1716.03 436.5 S9 38 1770.03 436.5 LCD supply voltage LCD backplane output LCD segment output All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 40 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates Table 23. Bump locations All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 25. PCA85133 Product data sheet Symbol Bump X (m) Y (m) Description S10 39 1824.03 436.5 LCD segment output S11 40 1878.03 436.5 S12 41 1423.53 436.5 S13 42 1369.53 436.5 S14 43 1315.53 436.5 S15 44 1261.53 436.5 S16 45 1207.53 436.5 S17 46 1153.53 436.5 S18 47 1099.53 436.5 S19 48 1045.53 436.5 S20 49 991.53 436.5 S21 50 937.53 436.5 S22 51 883.53 436.5 S23 52 829.53 436.5 S24 53 714.06 436.5 S25 54 660.06 436.5 S26 55 606.06 436.5 S27 56 552.06 436.5 S28 57 498.06 436.5 S29 58 444.06 436.5 S30 59 390.06 436.5 S31 60 336.06 436.5 S32 61 282.06 436.5 S33 62 228.06 436.5 S34 63 112.59 436.5 S35 64 58.59 436.5 S36 65 4.59 436.5 S37 66 49.41 436.5 S38 67 103.41 436.5 S39 68 157.41 436.5 S40 69 211.41 436.5 S41 70 265.41 436.5 S42 71 319.41 436.5 S43 72 373.41 436.5 S44 73 427.41 436.5 S45 74 481.41 436.5 S46 75 596.88 436.5 S47 76 650.88 436.5 S48 77 704.88 436.5 All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 41 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates Table 23. Bump locations All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 25. PCA85133 Product data sheet Symbol Bump X (m) Y (m) Description S49 78 758.88 436.5 LCD segment output S50 79 812.88 436.5 S51 80 866.88 436.5 S52 81 920.88 436.5 S53 82 974.88 436.5 S54 83 1028.88 436.5 S55 84 1082.88 436.5 S56 85 1136.88 436.5 S57 86 1252.35 436.5 S58 87 1306.35 436.5 S59 88 1360.35 436.5 S60 89 1414.35 436.5 S61 90 1468.35 436.5 S62 91 1522.35 436.5 S63 92 1576.35 436.5 S64 93 1630.35 436.5 S65 94 1684.35 436.5 S66 95 1738.35 436.5 S67 96 1792.35 436.5 S68 97 1876.05 436.5 S69 98 1822.05 436.5 S70 99 1768.05 436.5 S71 100 1714.05 436.5 S72 101 1660.05 436.5 S73 102 1606.05 436.5 S74 103 1552.05 436.5 S75 104 1498.05 436.5 S76 105 1444.05 436.5 S77 106 1390.05 436.5 S78 107 1336.05 436.5 S79 108 1282.05 436.5 BP3 109 1228.05 436.5 BP1 110 1174.05 436.5 LCD backplane output All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 42 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates Table 23. Bump locations All x/y coordinates represent the position of the center of each bump with respect to the center (x/y = 0) of the chip; see Figure 25. Symbol Bump X (m) Y (m) D1 - 1932.03 436.5 D2 - 1909.53 436.5 D3 - 1801.53 436.5 D4 - 1693.53 436.5 D5 - 1585.53 436.5 D6 - 1477.53 436.5 D7 - 1846.35 436.5 D8 - 1953 D9 - 1930.05 436.5 Description [2] dummy pad dummy pad 436.5 [1] For most applications SDA and SDAACK are shorted together; see Section 8. [2] The dummy pads are connected to VSS but are not tested. Table 24. Gold bump hardness Type number Min Max Unit[1] PCA85133U/2DA/Q1 60 120 HV PCA85133U/2DB/Q1 35 80 HV [1] Pressure of diamond head: 10 g to 50 g. 5() 5() 6 & DDK The approximate positions of the alignment marks are shown in Figure 25. Fig 26. Alignment marks of PCA85133 Table 25. Alignment mark locations All x/y coordinates represent the position of the REF point (see Figure 26) with respect to the center (x/y = 0) of the chip; see Figure 25. PCA85133 Product data sheet Symbol Size (m) X (m) Y (m) S1 81 81 1916.1 45 C1 81 81 1855.8 45 All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 43 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 18. Packing information 18.1 Packing information on the tray - $ + % $ $ [ ; . ) GLH ( GHWDLO; ' \ \ * [ ) ( & 2 1 / 0 6(&7,21$$ < 'LPHQVLRQVLQPP GHWDLO< DDD Schematic drawing, not drawn to scale. Top side view. For dimensions, see Table 26. Tray has pockets on both, top side and bottom side. The IC is stored with the active side up. To get the active side down, turn the tray. Fig 27. Tray details of PCA85133U PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 44 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates Table 26. Specification of 3 inch tray details Tray details are shown in Figure 27. Nominal values without production tolerances. Tray details Dimensions A B C D E F G H J K L M N O Unit 6.0 2.5 4.26 1.17 76.0 68.0 60.0 6.75 8.0 62.5 4.2 2.6 3.2 0.48 mm Number of pockets x direction y direction 11 26 SLQ DDD The orientation of the IC in a pocket with active side up is indicated by the position of pin 1 with respect to the chamfer on the upper left corner of the tray. Fig 28. Die alignment in the tray PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 45 of 54 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCA85133 Product data sheet 19. Appendix 19.1 LCD segment driver selection Table 27. Selection of LCD segment drivers Type name Number of elements at MUX ffr (Hz) Interface Package AECQ100 PCA8553DTT 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256[1] N N 40 to 105 I2C / SPI TSSOP56 Y PCA8546ATT - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 95 I2C TSSOP56 Y PCA8546BTT - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 95 SPI TSSOP56 Y 1.8 to 5.5 2.5 to 9 60 to 300[1] Y 40 to 95 I2C TQFP64 Y 60 to 300[1] Y Y 40 to 95 SPI TQFP64 Y N N 40 to 85 I2C LQFP80 N N 40 to 95 I2C LQFP80 Y Y 40 to 105 I2C LQFP80 Y TSSOP56 N 88 - - - 44 88 176 - - - 1.8 to 5.5 2.5 to 9 PCF85134HL 60 120 180 240 - - - 1.8 to 5.5 2.5 to 6.5 82 PCA8543AHL 60 60 120 180 240 120 - 240 - - - 1.8 to 5.5 2.5 to 8 2.5 to 5.5 2.5 to 9 82 Y N 60 to 300[1] 300[1] Y PCF8545ATT - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to N N 40 to 85 I2C PCF8545BTT - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300[1] N N 40 to 85 SPI TSSOP56 N PCF8536AT - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 85 I2C TSSOP56 N 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 85 SPI TSSOP56 N 300[1] TSSOP56 Y PCF8536BT - - - 176 252 320 - - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to N N 40 to 95 PCA8536BT - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 95 SPI TSSOP56 Y PCF8537AH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] Y Y 40 to 85 I2C TQFP64 N 1.8 to 5.5 2.5 to 9 60 to 300[1] Y Y 40 to 85 SPI TQFP64 N 300[1] Y Y 40 to 95 I2C TQFP64 Y Y Y 40 to 95 SPI TQFP64 Y Y 40 to 105 I2C LQFP80 Y Y 40 to 105 I2C Bare die Y PCF8537BH 44 88 - 176 276 352 - 46 of 54 © NXP Semiconductors N.V. 2014. All rights reserved. PCA8537AH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to PCA8537BH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] 2.5 to 5.5 2.5 to 9 60 to 300[1] 60 to 300[1] PCA9620H PCA9620U 60 60 120 120 - 240 320 480 240 320 480 - 2.5 to 5.5 2.5 to 9 Y Y PCF8576DU 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 N N 40 to 85 I2C Bare die N PCF8576EUG 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 N N 40 to 85 I2C Bare die N N 40 to 105 I2C Bare die Y N 40 to 85 I2C Bare die N N 40 to 95 I2C Bare die Y PCA8576FUG PCF85133U PCA85133U 40 80 80 80 120 160 - 160 240 320 160 240 320 - - - 1.8 to 5.5 2.5 to 8 200 1.8 to 5.5 2.5 to 6.5 82, 110[2] 1.8 to 5.5 2.5 to 8 110[2] 82, N N N PCA85133 PCA8536AT I2C Automotive LCD driver for low multiplex rates Rev. 3 — 4 July 2014 All information provided in this document is subject to legal disclaimers. PCA8547BHT PCA85134H - 176 - 1:9 VLCD (V) VLCD (V) Tamb (C) charge temperature pump compensat. 1:2 1:3 44 1:6 1:8 VLCD (V) 1:1 PCA8547AHT 1:4 VDD (V) xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Selection of LCD segment drivers …continued Type name Number of elements at MUX ffr (Hz) VLCD (V) VLCD (V) Tamb (C) charge temperature pump compensat. AECQ100 PCA85233UG 80 160 240 320 - - - 1.8 to 5.5 2.5 to 8 150, 220[2] N N 40 to 105 I2C Bare die Y PCF85132U 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 60 to 90[1] N N 40 to 85 I2C Bare die N Y 40 to 105 I2C Bare die Y N 40 to 95 I2C Bare die Y N N 40 to 95 I2C Bare die Y Y Y 40 to 85 I2C / SPI Bare die N Y 40 to 105 I2C Bare die Y PCA85132U 408 - 160 320 480 640 - PCA85232U 160 320 480 640 - PCF8538UG 102 204 - PCA8538UG 102 204 - Software programmable. [2] Hardware selectable. - - 2.5 to 5.5 4 to 12 1.8 to 5.5 1.8 to 8 1.8 to 5.5 1.8 to 8 45 to 300[1] 60 to 90[1] 117 to 176[1] 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300[1] 408 612 816 918 2.5 to 5.5 4 to 12 300[1] 45 to Y N Y / SPI / SPI PCA85133 47 of 54 © NXP Semiconductors N.V. 2014. All rights reserved. Automotive LCD driver for low multiplex rates Rev. 3 — 4 July 2014 All information provided in this document is subject to legal disclaimers. [1] - 1:9 Interface Package 1:2 1:3 102 204 - 1:6 1:8 VLCD (V) 1:1 PCA8530DUG 1:4 VDD (V) NXP Semiconductors PCA85133 Product data sheet Table 27. PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 20. Abbreviations Table 28. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor COG Chip-On-Glass DC Direct Current HBM Human Body Model I2C Inter-Integrated Circuit IC Integrated Circuit ITO Indium Tin Oxide LCD Liquid Crystal Display MM Machine Model RAM Random Access Memory RC Resistance-Capacitance RMS Root Mean Square 21. References [1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers [2] AN10706 — Handling bare die [3] AN10853 — ESD and EMC sensitivity of IC [4] AN11267 — EMC and system level ESD design guidelines for LCD drivers [5] AN11494 — Cascading NXP LCD segment drivers [6] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [7] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [8] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [9] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [10] JESD78 — IC Latch-Up Test [11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [12] UM10204 — I2C-bus specification and user manual [13] UM10569 — Store and transport requirements PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 48 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 22. Revision history Table 29. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA85133 v.3 20140704 Product data sheet - PCA85133 v.2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • • • • Legal texts have been adapted to the new company name where appropriate. Adjusted IDD and IDD(LCD) values in Table 20 Added graph Figure 20 “Current consumption with respect to external clock frequency” Removed ITO resistance table in Section 14 Changed product type and ordering information (Section 3) Changed tray information (Section 18) Improved description of bit E PCA85133 v.2 20110704 Product data sheet - PCA85133_1 PCA85133_1 20091023 Product data sheet - - PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 49 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 23. Legal information 23.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 23.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 23.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCA85133 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 50 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 23.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 24. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 51 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 25. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin description overview . . . . . . . . . . . . . . . . . .4 Selection of possible display configurations . . . .5 Biasing characteristics . . . . . . . . . . . . . . . . . . . .7 LCD frame frequencies . . . . . . . . . . . . . . . . . .15 Standard RAM filling in 1:3 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Entire RAM filling by rewriting in 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . .20 Blink frequencies . . . . . . . . . . . . . . . . . . . . . . .21 Definition of commands . . . . . . . . . . . . . . . . . .22 Mode-set command bit description . . . . . . . . .22 Load-data-pointer command bit description . .22 Device-select command bit description . . . . . .22 Bank-select command bit description[1] . . . . . .23 Blink-select command bit description . . . . . . .23 I2C slave address byte . . . . . . . . . . . . . . . . . . .26 Control byte description . . . . . . . . . . . . . . . . . .28 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .30 Static characteristics . . . . . . . . . . . . . . . . . . . .31 Dynamic characteristics . . . . . . . . . . . . . . . . . .33 Addressing cascaded PCA85133 . . . . . . . . . .36 Bump locations . . . . . . . . . . . . . . . . . . . . . . . . .40 Gold bump hardness . . . . . . . . . . . . . . . . . . . .43 Alignment mark locations . . . . . . . . . . . . . . . .43 Specification of 3 inch tray details. . . . . . . . . . .45 Selection of LCD segment drivers . . . . . . . . . .46 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .48 Revision history . . . . . . . . . . . . . . . . . . . . . . . .49 PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 52 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 26. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Block diagram of PCA85133 . . . . . . . . . . . . . . . . .3 Pin configuration for PCA85133 . . . . . . . . . . . . . .4 Example of displays suitable for PCA85133 . . . . .5 Typical system configuration . . . . . . . . . . . . . . . . .6 Electro-optical characteristic: relative transmission curve of the liquid. . . . . . . . . . . . . . . . . . . . . . . . . .9 Static drive mode waveforms . . . . . . . . . . . . . . . .10 Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .17 Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus . . . . . . . . . . . . . . . .18 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Definition of START and STOP conditions. . . . . .25 System configuration . . . . . . . . . . . . . . . . . . . . . .25 Acknowledgement on the I2C-bus . . . . . . . . . . . .26 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .27 Control byte format . . . . . . . . . . . . . . . . . . . . . . .27 Device protection diagram . . . . . . . . . . . . . . . . . .28 Current consumption with respect to external clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . .32 Driver timing waveforms . . . . . . . . . . . . . . . . . . .34 I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .35 Cascaded PCA85133 configuration. . . . . . . . . . .37 Synchronization of the cascade for the various PCA85133 drive modes . . . . . . . . . . . . . . . . . . . .38 Bare die outline of PCA85133 . . . . . . . . . . . . . . .39 Alignment marks of PCA85133 . . . . . . . . . . . . . .43 Tray details of PCA85133U . . . . . . . . . . . . . . . . .44 Die alignment in the tray . . . . . . . . . . . . . . . . . . .45 PCA85133 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 53 of 54 PCA85133 NXP Semiconductors Automotive LCD driver for low multiplex rates 27. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 6 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7 7.3.1 Electro-optical performance . . . . . . . . . . . . . . . 8 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . 10 7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 10 7.4.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 11 7.4.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 13 7.4.4 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 14 7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 Timing and frame frequency . . . . . . . . . . . . . . 15 7.7 Display register . . . . . . . . . . . . . . . . . . . . . . . . 15 7.8 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16 7.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 16 7.10 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10.1 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10.2 Subaddress counter . . . . . . . . . . . . . . . . . . . . 19 7.10.3 RAM writing in 1:3 multiplex drive mode. . . . . 19 7.10.4 Writing over the RAM address boundary . . . . 20 7.10.5 Output bank selector . . . . . . . . . . . . . . . . . . . 20 7.10.6 Input bank selector . . . . . . . . . . . . . . . . . . . . . 21 7.11 Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12 Command decoder . . . . . . . . . . . . . . . . . . . . . 21 7.13 Display controller . . . . . . . . . . . . . . . . . . . . . . 23 8 Characteristics of the I2C-bus . . . . . . . . . . . . 24 8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 START and STOP conditions . . . . . . . . . . . . . 24 8.3 System configuration . . . . . . . . . . . . . . . . . . . 25 8.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.5 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 26 8.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.7 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 26 9 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 28 10 Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11 12 13 14 14.1 15 15.1 16 17 18 18.1 19 19.1 20 21 22 23 23.1 23.2 23.3 23.4 24 25 26 27 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Cascaded operation. . . . . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . Quality information . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Packing information on the tray . . . . . . . . . . . Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD segment driver selection . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 31 33 36 36 38 38 39 44 44 44 46 46 48 48 49 50 50 50 50 51 51 52 53 54 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 July 2014 Document identifier: PCA85133