HIP2106 Data Sheet August 1999 100V/1A Peak, Low Cost, High Frequency Half Bridge Driver • Drives N-Channel MOSFET Half Bridge • Space Saving SO8 Package • Bootstrap Supply Max Voltage to 116VDC • On-Chip 1Ω Bootstrap Diode • Fast Propagation Times Needed for Multi-MHz Circuits • Drives 1000pF Load at 500kHz with Rise and Fall Times of Typically 20ns • CMOS Input Thresholds for Improved Noise Immunity • Independent Inputs for Non-Half Bridge Topologies • No Start-Up Problems • Outputs Unaffected by Supply Glitches, HS Ringing Below Ground, or HS Slewing at High dv/dt Ordering Information TEMP. RANGE (oC) 4406.2 Features The HIP2106 is a high frequency, 100V Half Bridge N-Channel MOSFET driver IC, available in 8 lead plastic SOIC. The low-side and high-side gate drivers are independently controlled and matched to 8ns. This gives the user maximum flexibility in dead-time selection and driver protocol. Undervoltage protection on both the low-side and high-side supplies force the outputs low. An on-chip diode eliminates the discrete diode required with other driver ICs. A new levelshifter topology yields the low-power benefits of pulsed operation with the safety of DC operation. Unlike some competitors, the high-side output returns to its correct state after a momentary undervoltage of the high-side supply. PART NUMBER File Number PKG. NO. PACKAGE • Low Power Consumption HIP2106IB -40 to 85 8 Ld SOIC M8.15 • Wide Supply Range HIP2106IP -40 to 85 8 Ld PDIP E8.3 • Supply Undervoltage Protection • 3Ω Output Resistance Pinout Applications HIP2106 (SOIC, PDIP) TOP VIEW • Telecom Half Bridge Power Supplies VDD 1 8 LO HB 2 7 VSS HO 3 6 LI HS 4 5 HI • Avionic DC-DC Converters • Two-Switch Forward Converters • Active Clamp Forward Converters Application Block Diagram +12V +100V VDD HB SECONDARY CIRCUIT DRIVE HI PWM CONTROLLER LI CONTROL HI HS DRIVE LO HIP2106 VSS 1 HO LO REFERENCE AND ISOLATION CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HIP2106 Functional Block Diagram 2 HB VDD 1 UNDER VOLTAGE LEVEL SHIFT 3 HO 4 HS 8 LO DRIVER HI 5 UNDER VOLTAGE DRIVER LI 6 VSS 7 Other Applications +48V +12V PWM SECONDARY CIRCUIT HIP 2106 ISOLATION FIGURE 1. TWO-SWITCH FORWARD CONVERTER +48V SECONDARY CIRCUIT +12V PWM HIP 2106 ISOLATION FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP 2 HIP2106 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD, VHB-VHS . . . . . . . . . . . . . . . . . . . -0.3V to 18V LI and HI Voltages . . . . . . . . . . . . . . . . . . . . . . . . .-3V to VDD +0.3V Voltage on LO . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on HO . . . . . . . . . . . . . . . . . . . . . . VHS -0.3V to VHB +0.3V Voltage on HS (Continuous) . . . . . . . . . . . . . . . . . . . . . -1V to 110V Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V Average Current in VDD to HB Diode. . . . . . . . . . . . . . . . . . . 100mA ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV) Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 HS Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V/ns Maximum Power Dissipation at 25oC in Free Air . . . . . . . . . .780mW Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature Range . . . . . . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Recommended Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +9V to +16.5V Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V Voltage on HS . . . . . . . . . . . . . . . (Repetitive Transient) -5V to 105V Voltage on HB. . . VHS +8V to VHS +16.5V and VDD -1V to VDD +100V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. All Voltages Relative to Pin 4, VSS Unless Otherwise Specified. Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = -40oC TO 125oC TJ = 25oC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS 0.15 - 0.2 mA SUPPLY CURRENTS VDD Quiescent Current IDD LI = HI = 0V - 0.1 VDD Operating Current IDDO f = 500kHz - 1.5 2.5 - 3 mA Total HB Quiescent Current IHB LI = HI = 0V - 0.1 0.15 - 0.2 mA Total HB Operating Current IHBO f = 500kHz - 1.5 2.5 - 3 mA HB to VSS Current, Quiescent IHBS VHS = VHB = 116.5V - 0.05 1 - 10 µA HB to VSS Current, Operating IHBSO f = 500kHz - 0.7 - - - mA INPUT PINS Low Level Input Voltage Threshold VIL 4 5.4 - 3 - V High Level Input Voltage Threshold VIH - 5.8 8 - 9 V VIHYS - 0.4 - - - V RI - 200 - 100 500 kΩ VDD Rising Threshold VDDR 7 7.3 8 6.5 8.5 V V Input Voltage Hysteresis Input Pulldown Resistance UNDER VOLTAGE PROTECTION VDD Threshold Hysteresis VDDH - 0.5 - - - HB Rising Threshold VHBR 6.5 6.9 7.5 6 8 V HB Threshold Hysteresis VHBH - 0.4 - - - V BOOT STRAP DIODE Low-Current Forward Voltage VDL IVDD-HB = 100µA - 0.45 0.55 - 0.7 V High-Current Forward Voltage VDH IVDD-HB = 100mA - 0.7 0.8 - 1 V Dynamic Resistance RD IVDD-HB = 100mA - 0.8 1 - 1.5 Ω V LO GATE DRIVER Low Level Output Voltage VOLL ILO = 100mA - 0.25 0.3 - 0.4 High Level Output Voltage VOHL ILO = -100mA, VOHL = VDD-VLO - 0.25 0.3 - 0.4 V Peak Pullup Current IOHL VLO = 0V - 1 - - - A Peak Pulldown Current IOLL VLO = 12V - 1 - - - A V HO GATE DRIVER Low Level Output Voltage VOLH IHO = 100mA - 0.25 0.3 - 0.4 High Level Output Voltage VOHH IHO = -100mA, VOHH = VHB-VHO - 0.25 0.3 - 0.4 V Peak Pullup Current IOHH VHO = 0V - 1 - - - A 3 HIP2106 VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued) Electrical Specifications TJ = -40oC TO 125oC TJ = 25oC PARAMETER SYMBOL Peak Pulldown Current IOLH Switching Specifications TEST CONDITIONS VHO = 12V MIN TYP MAX MIN MAX UNITS - 1 - - - A VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TEST CONDITIONS TJ = - 40oC TO 125oC TJ = 25oC MIN TYP MAX MIN MAX UNITS Lower Turn-Off Propagation Delay (LI Falling to LO Falling) tLPHL - 40 70 - 90 ns Upper Turn-Off Propagation Delay (HI Falling to HO Falling) tHPHL - 40 70 - 90 ns Lower Turn-On Propagation Delay (LI Rising to LO Rising) tLPLH - 40 70 - 90 ns Upper Turn-On Propagation Delay (HI Rising to HO Rising) tHPLH - 40 70 - 90 ns Delay Matching: Lower Turn-On and Upper Turn-Off tMON - 4 16 - 20 ns PARAMETER SYMBOL Delay Matching: Lower Turn-Off and Upper Turn-On tMOFF Either Output Rise/Fall Time tRC , tFC - 4 16 - 20 ns CL = 1000pF - 20 - - - ns Either Output Rise/Fall Time (3V to 9V) tR , tF CL = 0.1µF - 1.0 1.2 - 1.6 us Either Output Rise Time Driving DMOS tRD CL = IRFR120 - 40 - - - ns Either Output Fall Time Driving DMOS tFD CL = IRFR120 - 20 - - - ns Minimum Input Pulse Width that Changes the Output tPW - - - - 100 ns Bootstrap Diode Turn-On or Turn-Off Time tBS - 20 - - - ns Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 VDD Positive Supply to lower gate drivers. De-couple this pin to VSS (Pin 7). Bootstrap diode connected to HB (pin 2). 2 HB High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. 3 HO High-Side Output. Connect to gate of High-Side power MOSFET. 4 HS High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 5 HI High-Side input. 6 LI Low-Side input. 7 VSS Chip negative supply, generally will be ground. 8 LO Low-Side Output. Connect to gate of Low-Side power MOSFET. Timing Diagrams LI HI, LI HI tHPLH , tLPLH tHPHL, tLPHL LO tMOFF tMON HO, LO HO FIGURE 3. 4 FIGURE 4. HIP2106 10 10 1 1 IHBSO (mA) IDDO , IHBO (mA) Typical Performance Curves T = 150oC T = 125oC T = 25oC T = -40oC 0.1 0.01 10 T = 150oC T = -40oC 0.1 T = 125oC 0.01 50 100 FREQUENCY (kHz) 10 500 FIGURE 5. OPERATING CURRENT vs FREQUENCY 400 VHB = VDD = 14V VOLL , VOLH (mV) VOHL, VOHH (mV) VHB = VDD = 9V VHB = VDD = 12V VHB = VDD = 16.5V 300 200 VHB = VDD = 12V VHB = VDD = 14V VHB = VDD = 16.5V 300 200 0 50 100 100 -50 150 0 TEMPERATURE (oC) 100 150 FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE 0.54 7.6 0.5 7.4 VDDR VHBH , VDDH (mV) VHBR , VDDR (mV) 50 TEMPERATURE (oC) FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE 7.2 7.0 VHBR 6.8 6.6 -50 1000 500 VHB = VDD = 9V 100 -50 100 FREQUENCY (kHz) FIGURE 6. LEVEL SHIFTER CURRENT vs FREQUENCY 500 400 T = 25oC VDDH 0.46 0.42 0.38 VHBH 0.34 0 50 TEMPERATURE (oC) 100 150 FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE 5 0.3 -50 0 50 TEMPERATURE (oC) 100 150 FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs TEMPERATURE HIP2106 Typical Performance Curves (Continued) 2.5 tHPHL 2.0 tHPLH tLPHL 50 tLPLH IHO , ILO (A) tLPLH , tLPHL, tHPLH , tHPHL (ns) 60 1.5 1.0 40 0.5 0 30 -50 0 50 TEMPERATURE (oC) 100 0 150 FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE 4 6 VHO , VLO (V) 8 10 12 FIGURE 12. PULLUP CURRENT vs OUTPUT VOLTAGE 2.5 1 0.1 FORWARD CURRENT (A) 2.0 ILO , IHO (A) 2 1.5 1.0 0.5 0.01 0.001 1•10-4 1•10-5 0 0 2 4 6 VLO , VHO (V) 8 10 1•10-6 0.3 12 FIGURE 13. PULLDOWN CURRENT vs OUTPUT VOLTAGE 0.4 50 IDD , IHB (µA) IHB vs VHB 40 IDD vs VDD 30 20 10 0 5 10 VDD, VHB (V) 15 FIGURE 15. BIAS CURRENT vs VOLTAGE 6 0.7 0.8 FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS 60 0 0.5 0.6 FORWARD VOLTAGE (V) HIP2106 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 7 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 8 0.355 10.16 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 10.92 3.81 8 5 6 7 4 9 Rev. 0 12/93 HIP2106 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA 0.25(0.010) M H B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- e α A1 B 0.25(0.010) M C C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.10(0.004) MILLIMETERS MIN H 0.050 BSC 1.27 BSC - 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 8 0o 8 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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