® PRELIMINARY February 1998 NS ESIG D NEW at OR F nt e r D e E C 2 D 8 por t EN /tsc P40 O M M S e e H I c a l S up r s i l . c o m C E i R .inte ech n N OT ur T o r w w w o t c RSIL ont a or c 8-INTE 1-88 HIP4084 80V, 0.50A Four Phase Driver Features Description • Independently Drives 8 N-Channel MOSFETs in Either Four Phase Bridge Configuration or Dual H-Bridge Configuration The HIP4084 is a Four Phase Bridge N-Channel MOSFET driver IC. • 1.25A Peak Turn-Off Current • Bootstrap Supply Max Voltage to 95VDC • Bias Supply Operation from 7V to 15V • User-Programmable Dead Time (0.25µs to 4.5µs) • Charge-Pump and Bootstrap Maintain Upper Bias Supplies • Drives 1000pF Load with Typical Rise Time of 20ns and Fall Time of 10ns • EN (Disable) Overrides Input Control • Input Logic Thresholds Compatible with 3V to 15V Logic Levels • Dead Time Disable Capability • Programmable Undervoltage Set Point Specifically targeted for PWM and stepper motor control applications, the HIP4084 makes bridge based designs simple and flexible. With operation up to 80V and undervoltage detection, the device is best suited to applications of moderate power levels. Like the HIP4081, the HIP4084 has a flexible input protocol for driving every possible switch combination. Like the HIP4082, the HIP4084 provides a typical drive currents of 0.5A and a programmable dead time from 0.25µs to 4.5µs. Like the HIP4086, the HIP4084 allows override of shootthrough protection for switched reluctance applications. The HIP4084 is suitable for applications requiring DC to 100kHz. Unlike other HIP4080 family products, the HIP4084 provides, from a single pin, a programmable undervoltage set point and an enable/disable function. Ordering Information Applications PART NUMBER • Brushless Motors TEMP. RANGE ( oC) PKG. NO. PACKAGE • AC Motor Drives HIP4084AB -40 to 105 28 Ld SOIC M28.3 • Stepper Motors HIP4084AP -40 to 105 28 Ld PDIP E28.6 • Switched Reluctance Motor Drives For additional information contact Ivars Lauzums at (407) 729-5531. Pinout Application Block Diagram HIP4084 (PDIP, SOIC) TOP VIEW 80V AHO 1 28 AHS AHB 2 27 BHB AHI 3 26 BHO ALI 4 25 BHS BHI 5 24 ALO BLI 6 23 BLO VSS 7 22 VDD RDEL 8 21 CLO 9 20 DLO CHI 10 19 CHS UVLO/EN CLI 11 18 CHO DHI 12 17 CHB DLI 13 16 DHS DHB 14 15 DHO 12V HIP4084 GND GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 File Number 4222.1 HIP4084 TRUTH TABLE INPUT OUTPUT ALI, BLI, CLI, DLI AHI, BHI, CHI, DHI UVLO/EN RDEL ALO, BLO, CLO, DLO AHO, BHO, CHO, DHO X X 0 X 0 0 1 X 1 >100mV 1 0 0 0 1 X 0 1 0 1 1 X 0 0 1 0 1 <100mV 1 1 NOTE: X signifies that input can be either a “1” or “0”. Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 2 27 17 14 AHB BHB CHB DHB (xHB) High-side Bootstrap supplies. One external bootstrap diode and one capacitor are required for each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB pin. 3 5 10 12 AHI BHI CHI DHI (xHI) High-Side Logic Level Inputs. Logic at these three pins controls the three high-side output drivers, AHO (Pin 1), BHO (Pin 26) and CHO (Pin 18) and DHO (Pin 15). When xHI is low, xHO is high. When xHI is high, xHO is low. Unless the dead time is disabled by connecting RDEL (Pin 8) to ground, the low side input of each phase will override the corresponding high side input on that phase. If RDEL is tied to ground, dead time is disabled and the outputs follow the inputs. Care must be taken to avoid shoot-through in this application. EN (Pin 9) also overrides the high side inputs. xHI can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold each xHI high if the pins are not driven. 4 6 11 13 ALI BLI CLI DLI (xLI) Low-Side Logic Level Inputs. Logic at these three pins controls the three low-side output drivers ALO (Pin 24), BLO (Pin 23) and CLO (Pin 21) and DLO (Pin 20). If the upper inputs are grounded then the lower inputs controls both xLO and xHO drivers, with the dead time set by the resistor at RDEL (Pin 8). EN (Pin 9) high level input overrides xLI, forcing all outputs low. xLI can be driven by signal levels of 0V to 15V (no greater than V DD). An internal 100µA pull-up to V DD will hold xLI high if these pins are not driven. Ground. Connect the sources of the low-side power MOSFETs to this pin. 7 VSS 8 RDEL Dead Time Setting. Connect resistor from this pin to V DD to set timing current that defines the dead time between drivers. All drivers turn-off with no adjustable delay, so the RDEL resistor guarantees no shoot-through by delaying the turn-on of all drivers. When R DEL is tied to VSS, both upper and lowers can be commanded on simultaneously. While not necessary in most applications, a decoupling capacitor of 0.1µF or smaller may be connected between R DEL and VSS. 9 RUV/EN A resistor can be connected between this pin and V SS to program the under voltage set point. With this pin not connected the undervoltage setpoint is typically 6.6V. When this pin is tied to VDD, the undervoltage setpoint is typically 6.2V. With this pin tied to VSS, all six outputs are taken low, overriding all other inputs. 1 26 18 15 AHO BHO CHO DHO (xHO) High-Side Outputs. Connect the gates of the high-side power MOSFETs to these pins. 28 25 19 16 AHS BHS CHS DHS (xHS) High-Side Source connection. Connect the sources of the high-side power MOSFETs to these pins. The negative side of the bootstrap capacitors should also be connected to these pins. 22 VDD Positive supply. De-couple this pin to VSS (Pin 7). 24 23 21 20 ALO BLO CLO DLO (xLO) Low-Side Outputs. Connect the gates of the low-side power MOSFETs to these pins. NOTE: x = A, B, C and D 2 HIP4084 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage, V DD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on xHS. . . . . . . . .-6V (Transient) to +85V (-40oC to 150oC) Voltage on xHB. . . . . . . . . . . . . . . . . . . . .VxHS -0.3V to VxHS +VDD Voltage on xLO . . . . . . . . . . . . . . . . . . . . . . VSS -0.3V to V DD +0.3V Voltage on xHO . . . . . . . . . . . . . . . . . . . .VxHS -0.3V to VxHB +0.3V Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75oC PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Operating Ambient Temperature Range . . . . . . . . . . -40oC to 105oC Operating Junction Temperature Range . . . . . . . . .-40oC to 105oC Supply Voltage, V DD . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V to +15V Voltage on V xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 80V Voltage on xHB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VxHS + VDD CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. All voltages are relative to VSS unless otherwise specified. 3. x = A, B, C, and D. For example, xHS refers to AHS, BHS, CHS, and DHS. Electrical Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 20K, UVLO/EN = ∞, Gate Capacitance (CGATE) = 1000pF TJ = -40oC TO 150oC TJ = 25oC PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX UNITS SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION VDD Quiescent Current xHI = 5V, xLI = 5V 3 4 5 2 6 mA VDD Operating Current f = 20kHz, 50% Duty Cycle 8 9.5 12 7 13 mA xHB On Quiescent Current xHI = 0V - 40 80 - 100 µA xHB Off Quiescent Current xHI = VDD 0.6 0.8 1.3 0.5 1.4 mA xHB Operating Current f = 20kHz, 50% Duty Cycle 0.7 0.9 1.3 2.0 mA QPUMP Output Voltage No Load 11.5 12.5 14 10.5 14.5 V QPUMP Output Current VxHB = 10V - 100 130 - 140 µA xHB, xHS Leakage Current VxHS = 80V, VxHB = 93V 7 24 45 - 50 µA VDD Rising Undervoltage Threshold RUV Open 6.2 7.1 8.0 6.1 8.1 V VDD Falling Undervoltage Threshold RUV Open 5.75 6.6 7.5 5.6 7.6 V Minimum Undervoltage Threshold RUV = VDD 5 6.2 6.8 4.9 6.9 V Low Level Input Voltage - - 1.0 - 0.8 V High Level Input Voltage 2.5 - - 2.7 - V Input Voltage Hysteresis - 35 - - - mV INPUT PINS: ALI, BLI, CLI, DLI, AHI, BHI, CHI, DHI, AND EN Low Level Input Current VIN = 0V 60 100 135 55 140 µA High Level Input Current VIN = 5V -1 - 1 -10 10 µA - 100 - - 200 mV 0.3 0.5 0.7 - 1.0 A GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, DLO, AHO, BHO, CHO, AND DHO Low Level Output Voltage (VOUT-VSS) ISINKING = 30mA Peak Pulse Pullup Current VOUT 0V to 5V 3 HIP4084 Electrical Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 20K, UVLO/EN = ∞, Gate Capacitance (CGATE) = 1000pF TJ = -40oC TO 150oC TJ = 25oC PARAMETER Peak Pulse Pulldown Current TEST CONDITIONS VOUT 12V to 4V MIN TYP MAX MIN MAX UNITS 0.7 1.1 1.5 0.5 1.7 A Switching Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 10K, Gate Capacitance (CGATE) = 1000pF TJ = -40oC TO 150oC TJ = 25oC MIN TYP MAX MIN MAX UNITS RDEL = 100K 3.8 4.5 6 3 7 µs RDEL = 10K 0.38 0.5 0.65 0.3 0.7 µs Dead Time Channel Matching RDEL = 10K - 7 15 - 20 % Lower Turn-Off Propagation Delay (xLI-xLO) No Load - 25 50 - 70 ns Upper Turn-Off Propagation Delay (xHI-xHO) No Load - 55 80 - 100 ns Lower Turn-On Propagation Delay (xLI-xLO) No Load - 40 85 - 100 ns Upper Turn-On Propagation Delay (xHI-xHO) No Load - 75 110 - 150 ns Rise Time CGATE = 1000pF - 20 40 - 50 ns Fall Time CGATE = 1000pF - 10 20 - 25 ns Turn-On Input Pulse Width 50 - - 50 - ns Turn-Off Input Pulse Width 50 - - 50 - ns Disable (EN) Turn-Off Propagation Delay (EN - xLO) - 50 80 90 ns Disable (EN) Turn-Off Propagation Delay (EN - xHO) - 75 100 - 125 ns Enable to Lower Turn-On Propagation Delay (EN - xLO) - 50 80 - 100 ns - 1.2 2 - 3 µs 375 580 900 350 950 µs PARAMETER TEST CONDITIONS TURN ON DELAY AND PROPAGATION DELAY Dead Time Enable to Upper Turn-On Propagation Delay (EN- xHO) RDEL = 10K Refresh Pulse Width (xLO) 4 HIP4084 Dual-In-Line Plastic Packages (PDIP) E28.6 (JEDEC MS-011-AB ISSUE B) N 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- A2 -C- SEATING PLANE e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.380 1.565 D1 0.005 - A L D1 MIN A E D MAX A1 -ABASE PLANE MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 39.7 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 35.1 28 28 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 5 HIP4084 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N INDEX AREA 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE 0.25(0.010) M H B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- h x 45o A D µα e A1 B 0.25(0.010) M C A M 0.10(0.004) B S MAX NOTES 0.0926 0.1043 2.35 2.65 - 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 0.05 BSC 0.394 0.419 1.27 BSC 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α NOTES: MIN A H C MILLIMETERS MAX A1 e -C- MIN 28 0o 28 7 8o Rev. 0 12/93 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 6