CD4018BMS CMOS Presettable Divide-By- “N” Counter November 1994 Features Description • High Voltage Type (20V Rating) CD4018BMS types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q5, Q4, Q3, Q2, Q1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions greater than 10 can be achieved by use of multiple CD4018BMS units. The counter is advanced one count at the positive clock-signal transition. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clears the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence. • Medium Speed Operation 10MHz (typ.) at VDD - VSS = 10V • Fully Static Operation • 100% Tested for Quiescent Current at 20V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range; - 100nA at 18V and 25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications The CD4018BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1F H6W • Fixed and Programmable Divided- By-10, 9, 8, 7, 6, 5, 4, 3, 2 Counters • Fixed and Programmable Counters Greater Than 10 Functional Diagram • Programmable Decade Counters VDD JAM INPUTS • Divide-By- “N” Counters/Frequency Synthesizers “1” • Counter Control/Timers 2 Pinout 16 VDD JAM 1 2 15 RESET JAM 2 3 14 CLOCK 7 “5” 9 12 16 5 14 4 1 6 DATA DATA 1 3 PRESET 10 ENABLE CLOCK CD4018BMS TOP VIEW “4” “3” RESET 15 Q1 Q2 Q3 11 Q4 13 Q2 4 13 Q5 Q1 5 12 JAM 5 Q3 6 JAM 3 7 VSS 8 BUFFERED OUT “2” • Frequency Division Q5 8 VSS 11 Q4 10 PRESET ENABLE 9 JAM 4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-350 File Number 3298 Specifications CD4018BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current SYMBOL IDD IIL CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND IIH LIMITS TEMPERATURE 10 µA µA -55oC - 10 µA 1 +25oC -100 - nA 2 +125o VDD = 18V, VIN = VDD or GND 3 VIN = VDD or GND VDD = 20 -1000 - nA 3 -55oC C -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA - 100 nA - 50 mV 3 -55oC Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 VDD = 18V UNITS 1000 +25 +125oC VIN = VDD or GND MAX - 1 VDD = 20 MIN - oC 2 VDD = 18V Input Leakage Current GROUP A SUBGROUPS - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA -2.8 -0.7 V 0.7 2.8 V N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B Functional F Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 7-351 V -55oC +25oC, NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs VOH > VOL < VDD/2 VDD/2 +125oC, -55oC - 1.5 V +25oC, +125oC, -55oC 3.5 - V 1, 2, 3 +25oC, +125oC, -55oC - 4 V 1, 2, 3 +25oC, +125oC, -55oC 11 - V 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4018BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock To Q Propagation Delay Preset To Q Propagation Delay Reset To Q SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPLH3 CONDITIONS (NOTE 1) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND LIMITS MIN MAX UNITS 9 +25oC - 400 ns 10, 11 +125oC, -55oC - 540 ns 9 +25oC - 550 ns 10, 11 +125oC, -55oC - 743 ns o 9 +25 C - 550 ns 10, 11 +125oC, -55oC - 743 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA 1, 2 -55oC, +25oC - 10 µA +125oC - 600 µA 1, 2 +25oC, +125oC, - 50 mV 1, 2 +25oC, +125oC, - 50 mV VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 -55oC Output Voltage VOL VDD = 10V, No Load -55oC Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V 1, 2 Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V Propagation Delay Clock To Q TPHL1 TPLH1 VDD = 10V 1, 2, 3 +25oC - 180 ns VDD = 15V 1, 2, 3 +25oC - 130 ns Propagation Delay Preset To Q TPHL2 TPLH2 VDD = 10V 1, 2, 3 +25oC - 250 ns VDD = 15V 1, 2, 3 +25oC - 180 ns Propagation Delay Reset to Q TPLH3 VDD = 10V 1, 2, 3 +25oC - 250 ns VDD = 15V 1, 2, 3 +25oC - 180 ns 7-352 Specifications CD4018BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Transition Time TTHL TTLH Maximum Clock Input Frequency FCL Minimum Data Setup Time TS Minimum Data Hold Time Minimum Clock Pulse Width Minimum Preset/Reset Removal Time Minimum Preset/Reset Pulse Width Input Capacitance TH TW TREM TW CIN CONDITIONS NOTES TEMPERATURE MIN MAX UNITS VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns VDD = 5V 1, 2, 3 +25oC 3 - MHz VDD = 10V 1, 2, 3 +25oC 7 - MHz VDD = 15V 1, 2, 3 +25oC 8.5 - MHz VDD = 5V 1, 2, 3 +25oC - 40 ns VDD = 10V 1, 2, 3 +25oC - 12 ns VDD = 15V 1, 2, 3 +25oC - 6 ns VDD = 5V 1, 2, 3 +25oC - 140 ns VDD = 10V 1, 2, 3 +25oC - 80 ns o VDD = 15V 1, 2, 3 +25 C - 60 ns VDD = 5V 1, 2, 3 +25oC - 160 ns VDD = 10V 1, 2, 3 +25oC - 70 ns VDD = 15V 1, 2, 3 +25oC - 50 ns VDD = 5V 1, 2, 3 +25oC - 80 ns VDD = 10V 1, 2, 3 +25oC - 30 ns VDD = 15V 1, 2, 3 +25oC - 20 ns VDD = 5V 1, 2, 3 +25oC - 160 ns VDD = 10V 1, 2, 3 +25oC - 70 ns VDD = 15V 1, 2, 3 +25oC - 50 ns 1, 2 +25oC - 7.5 pF Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage Delta ∆VTND VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTPD VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading 7-353 Specifications CD4018BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Output Current (Source) SYMBOL DELTA LIMIT ± 20% x Pre-Test Reading IOH5A TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 4 - 6, 11, 13 1 - 3, 7 - 9, 10, 12, 14, 15 16 Static Burn-In 2 Note 1 4 - 6, 11, 13 8 1 - 3, 7, 9, 10, 12, 14 - 16 Dynamic BurnIn Note 1 - 2, 8, 9, 15 1, 3, 12, 16 4 - 6, 11, 13 8 1 - 3, 7, 9, 10, 12, 14 - 16 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 4 - 6, 11, 13 7, 14 10 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-354 CD4018BMS Logic Diagram RESET * 15 R PRESET ENABLE * PE 10 PE R 1 CLOCK * R * 3 J1 DATA * * 2 R * 7 J2 R * 9 J3 R J4 12 * J5 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 CL Q1 CL Q2 CL Q3 CL Q4 CL Q5 PE PE PE PE PE PE PE PE PE PE 14 5 Q1 4 Q2 6 Q3 11 Q4 FIGURE 1. LOGIC DIAGRAM PE CL CL R JN CL CL p n DN CL VDD p n CL PE CL p n p n p n PE CL CL p n CL VSS CL *ALL INPUTS PROTECTED BY CMOS INPUT PROTECTION NETWORK FIGURE 2. QN DETAIL OF A TYPICAL STAGE 7-355 QN 13 Q5 CD4018BMS 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 -5 -10V PROPAGATION DELAY TIME (tPHL, tPLH) (ns) TRANSITION TIME (tTHL, tTLH) (ns) SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 20 -15 FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 200 0 0 -10 -15V AMBIENT TEMPERATURE (TA) = +25oC 50 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 150 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 0 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO Q) 7-356 CD4018BMS 4 AMBIENT TEMPERATURE (TA) = +25oC 2 POWER DISSIPATION (PD) (µW) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) Typical Performance Characteristics (Continued) 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 10 4 SUPPLY VOLTAGE (VDD) = 15V 8 6 4 10V 2 10V 103 8 6 4 2 102 5V CL = 50pF CL = 15pF 8 6 4 2 AMBIENT TEMPERATURE (TA) = +25oC 10 2 4 68 0 20 40 60 80 100 1 LOAD CAPACITANCE (CL) (pF) FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (RESET TO Q) 2 4 68 2 4 68 2 4 68 105 FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY Timing Diagram (“DATA” INPUT TIED TO Q5 FOR DECADE COUNTER CONFIGURATION) CLOCK RESET PRESET JAM 1 JAM 2 JAM 3 2 4 68 102 102 103 104 INPUT FREQUENCY (fCL) (HZ) DON’T CARE UNTIL PRESET “GOES HIGH” JAM 4 JAM 5 Q1 Q2 Q3 Q4 Q5 FIGURE 11. TIMING DIAGRAM 7-357 CD4018BMS EXTERNAL CONNECTIONS FOR DIVIDE BY 10, 9, 8, 7, 6, 5, 4, 3, OPERATION J1 J2 J3 J4 J5 CL No External Components DIVIDE BY 10 Q5 Connected Back To “Data” Required DIVIDE BY 8 Q4 Connected No External Components Back To “Data” Required DIVIDE BY 6 Q3 Connected No External Components Back To “Data” Required DIVIDE BY 4 Q2 Connected No External Components Back To “Data” Required DIVIDE BY 2 Q1 D R Q3 Q4 CL ÷ 7 FIGURE 13. EXAMPLE OF DIVIDE BY 7 DIVIDE BY 9 1/2 CD4011B Q4 CONNECTED BACK TO “DATA” (SKIPS “ALL-I’s” STATE) Q5 Chip Dimensions and Pad Layout DIVIDE BY 7 1/2 CD4011B Q3 CONNECTED BACK TO “DATA” (SKIPS “ALL-I’s” STATE) Q4 DIVIDE BY 5 1/2 CD4011B Q2 CONNECTED BACK TO “DATA” (SKIPS “ALL-I’s” STATE) Q3 DIVIDE BY 3 1/2 CD4011B Q1 CONNECTED BACK TO “DATA” (SKIPS “ALL-I’s” STATE) Q2 FIGURE 12. EXTERNAL CONNECTIONS FOR DIVIDE BY 10, 9, 8, 7, 6, 5, 4, 3, 2 OPERATION Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 358