CD4042BMS CMOS Quad Clocked “D” Latch December 1992 Features Pinout • High-Voltage Type (20V Rating) CD4042BMS TOP VIEW • Clock Polarity Control • Q and Q Outputs Q4 1 16 VDD • Common Clock Q1 2 15 Q4 • Low Power TTL Compatible Q1 3 14 D4 D1 4 13 D3 CLOCK 5 12 Q3 POLARITY 6 11 Q3 D2 7 10 Q2 VSS 8 9 Q2 • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • 5V, 10V and 15V Parametric Ratings • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” NC = NO CONNECTION Functional Diagram D1 4 Applications D2 7 2 Q1 3 Q1 10 Q2 9 Q2 11 Q3 12 Q3 1 Q4 15 Q4 • Buffer Storage • Holding Register D3 13 • General Digital Logic Description D4 14 CD4042BMS types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p- channel output devices is balanced and all outputs are electrically identical. Information present at the data input is transferred to outputs Q and Q during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the outputs until an opposite CLOCK transition occurs. CLOCK 5 CL POLARITY 6 VDD 16 VSS 8 The CD4042BMS is supplied in these 16 lead outline packages: Braze Seal DIP H4T Frit Seal DIP H1E Ceramic Flatpack H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-868 File Number 3310 Specifications CD4042BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP Package . . . . . . . . . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 GROUP A SUBGROUPS LIMITS TEMPERATURE MIN +25 - 2 µA +125oC - 200 µA 3 -55oC - 2 µA 1 +25o C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA - 100 nA - 50 mV - V 3 Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V UNITS 1 -55oC VDD = 18V MAX 2 oC 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA Output Current (Source) Output Current (Source) IOH5A IOH5B VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V N Threshold Voltage P Threshold Voltage Functional VNTH VPTH F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND. 2. Go/no go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 7-869 Specifications CD4042BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTES 1, 2) Propagation Delay (Note 2) Data in to Q TPHL1 TPLH1 VDD = 5V, VIN = VDD or GND Propagation Delay (Note 2) Data in to Q TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay (Note 2) Clock to Q TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND Propagation Delay (Note 2) Clock to Q TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND TTHL TTLH VDD = 5V, VIN = VDD or GND Transition Time (Note 2) GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 +25oC +125oC, -55oC +25oC o o LIMITS MIN MAX UNITS - 220 ns - 297 ns - 300 ns 10, 11 +125 C, -55 C - 405 ns 9 +25oC - 450 ns - 608 ns 10, 11 +125oC, -55oC 9 +25oC - 500 ns 10, 11 +125oC, -55oC - 675 ns 9 +25oC - 200 ns - 270 ns 10, 11 o o +125 C, -55 C NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K, input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 1 µA +125oC - 30 µA -55oC, +25oC - 2 µA +125oC - 60 µA -55oC, +25oC - 2 µA +125oC o VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 - 120 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25 C, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V 1, 2 +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V 7-870 Specifications CD4042BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS VDD = 10V 1, 2, 3 +25oC - 110 ns VDD = 15V 1, 2, 3 +25oC - 80 ns VDD = 10V 1, 2, 3 +25oC - 150 ns VDD = 15V 1, 2, 3 +25oC Propagation Delay Data in to Q TPHL1 TPLH1 Propagation Delay Data in to Q TPHL2 TPLH2 - 100 ns Propagation Delay Clock to Q TPHL3 TPLH3 VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25oC - 160 ns Propagation Delay Clock to Q TPLH4 TPHL4 VDD = 10V 1, 2, 3 +25oC - 230 ns VDD = 15V 1, 2, 3 +25oC - 180 ns TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns VDD = 5V 1, 2, 3 +25oC - * - VDD = 10V 1, 2, 3 +25oC - * - VDD = 15V 1, 2, 3 +25oC - * - VDD = 5V 1, 2, 3 +25oC - 50 ns VDD = 10V 1, 2, 3 +25oC - 30 ns VDD = 15V 1, 2, 3 +25oC - 25 ns VDD = 5V 1, 2, 3 +25oC - 120 ns VDD = 10V 1, 2, 3 +25oC - 60 ns VDD = 15V 1, 2, 3 +25oC - 50 ns VDD = 5V 1, 2, 3 +25oC - 200 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 60 ns 1, 2 +25oC - 7.5 pF Transition Time Clock Input Rise and Fall Time (Note 4) Minimum Data Setup Time TRCL TFCL TS Minimum Data Hold Time Minimum Clock Pulse Width TH TW Input Capacitance CIN Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K. 4. * Not sensitive TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES TEMPERATURE VDD = 20V, VIN = VDD or GND 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC MIN MAX UNITS - 7.5 µA -2.8 -0.2 V - ±1 V N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record 7-871 Specifications CD4042BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD ± 0.2µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas PDA (Note 1) Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 PDA (Note 1) Final Test Group A Group B Group D READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 1.5% parametric, 3% functional; cumulative for static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 READ AND RECORD METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 1 - 3, 9 - 12, 15 4 - 8, 13, 14 16 Static Burn-In 2 Note 1 1 - 3, 9 - 12, 15 8 4 - 7, 13, 14, 16 Dynamic BurnIn Note 1 - 8 6, 16 1 - 3, 9 - 12, 15 8 4 - 7, 13, 14, 16 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 1 - 3, 9 - 12, 15 5 4, 7, 13, 14 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-872 Specifications CD4042BMS Logic Diagram ONE OF FOUR LATCHES CL * D1 4 TG 2 Q1 3 Q1 CL CL TG *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK CL VDD CONTROL P * CLOCK 5 TG CL TG CL P VSS P * POLARITY 6 P P LOGIC BLOCK DIAGRAM TRUTH TABLE CLOCK POLARITY 0 0 D 0 LATCH 1 Q 1 D 1 LATCH All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 873 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CD4042BMS 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 -30 -5 -10V PROPAGATION DELAY TIME (tPHL, tPLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) 150 SUPPLY VOLTAGE (VDD) = 5V 125 100 10V 50 15V 25 20 30 40 50 60 70 80 -15 FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 10 -10 -15V 175 0 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 75 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 175 150 SUPPLY VOLTAGE (VDD) = 5V 125 100 10V 75 50 15V 25 0 90 100 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF) FIGURE 5. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE - DATA TO Q FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE - DATA TO Q 7-874 CD4042BMS (Continued) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) Typical Performance Characteristics 300 250 SUPPLY VOLTAGE (VDD) = 5V 200 150 10V 15V 100 50 AMBIENT TEMPERATURE (TA) = +25oC 0 20 40 60 100 80 120 300 250 SUPPLY VOLTAGE (VDD) = 5V 200 150 10V 15V 100 50 AMBIENT TEMPERATURE (TA) = +25oC 140 0 20 LOAD CAPACITANCE (CL) (pF) TRANSITION TIME (tTHL, tTLH) (ns) POWER DISSIPATION PER DEVICE (PD) (µW) SUPPLY VOLTAGE (VDD) = 15V 103 10V 10V 5V 10 100 120 140 AMBIENT TEMPERATURE (TA) = +25oC 105 102 80 FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE - CLOCK TO Q AMBIENT TEMPERATURE (TA) = +25oC 104 60 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE - CLOCK TO Q 106 40 CL = 50pF CL = 15pF 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 15V 50 1 103 104 105 106 107 0 0 INPUT FREQUENCY (fI) (kHz) FIGURE 9. TYPICAL POWER DISSIPATION vs FREQUENCY 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 10. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE Chip Dimensions and Pad Layout NOTE 1 CLOCK CL NOTE 2 DATA INPUT D Q OUTPUT LATCH LOW DATA tS tH LATCH HIGH DATA LOW DATA LATCHED tPHL, tPLH D TO Q OR Q HIGH DATA LATCHED tPHL, tPLH CL TO Q OR Q NOTES: 1. For positive clock edge, input data is latched when polarity is low. 2. For negative clock edge, input data is latched when polarity is high. Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated Grid graduations are in mils (10-3 inch). FIGURE 11. DYNAMIC TEST PARAMETERS 7-875