EVB-USB3503Q QFN Evaluation Board Schematic, PDF

5
4
3
2
USB Connectors
USB3503 32 QFN Evaluation Board
5V
J3
DNP
L1
DNP
3
R5 DNP
1
F-BEAD
VBAT
U1
1
D
ZERO
2
R4
10k
3
2
Power_Jack
R1
IN
OUT
GND
FB
ENA
BYP
6
1
DATA
5
C2
4
18pF
R2
51.0k
C1
ZERO
U.FL
2
3
D
J5
STROBE
4.7uF
1
U.FL
2
3
J4
TPS79301
C4
0.01uF
C3
0.1uF
R35
TP2
OSC
3.3V VBAT (200mA)
1
R3
30.1k
TP3
TP1
TP6
DNP
VBUS
VDD_PU
ZERO
U2
1
IN
2
R10
10k
3
OUT
GND
FB
ENA
BYP
6
R8
1.8V VCC_CORE (200mA)
5
C7
4
18pF
R6
14.3k
C5
ZERO
4.7uF
R9 DNP
C10
0.1uF
9
10
6
7
8
11
C16
4.7uF
VBAT
ZERO
ZERO
R7
30.1k
R24
10k
DNP
This portion of the schematic
shows the required components for
the Hub to operate properly
0.01uF
C
VBUS
DD+
ID
GND
R33
PORTPWR
VDD33_BYP
TPS79301
C8
J2
1
2
3
4
5
VBUS
DM
DP
SHLD1
SHLD2
MNT1
MNT2
MNT3
MNT4
MICRO-AB
C17
C
R25
0.1uF
VDD_PU
4
0.1uF
0.1uF
R12
2
GND
J1
2
4
6
8
10
VCC
1
3
5
7
9
OUT
3
ZERO
26.0 MHz
29
REFCLK
8
7
SCL
SDA
OUTA
OUTB
5V
R23
10k
DNP
7
6
FLAGA
FLAGB
8
5
1
2
3
4
2
3
150uF
R20
10k
R19
10k
R18
10k
DNP
R21
10k
R15
10k
R14
10k
SW1
SW2
U6
1
2
3
12
4
3
NC6
NC5
VDD33_BYP
2
2
SW3
3
HUB_CONNECT
5
1
USBDN1_DP
USBDN1_DM
RESET_N
32
MOM-ON
15
16
R31
OCSN
1
2
3
4
R32
PORTPWR
USBDN2_DP
USBDN2_DM
USBDN3_DP
USBDN3_DM
24
23
DN1_DP
DN1_DM
22
21
DN2_DP
DN2_DM
20
19
DN3_DP
DN3_DM
RBIAS
VDD33_BYP
4
1
3
14
27
31
R30
10k
DNP
R16
10k
R13
10k
R37
LED1
Grn
4
FLAG1
150uF
VDD33_BYP
1
4
5
6
SHLD1
SHLD2
R36
C12
C22
1.0uF
USB-A
12.0k
2.2uF
33
3930 East Ray Road
Suite 200
Phoenix, Arizona 85044
480-759-0200
MTH2
MTH1
MTH3
MTH4
USB3503_32QFN
SCHMITT TRIG
MH
1
MH
1
MH
1
MH
1
C21
C19
A
0.1uF
DNP
0.1uF
DNP
Title
SCH-7265AZ USB3503 Evaluation Board
Size
B
mtg250c140d mtg250c140d mtg250c140d mtg250c140d
5
VCC
DD+
GND
+C13
30
13
6
11
3
B
P2
1
2
3
4
26
SHLD1
SHLD2
2
330
3
R27
10k
1
R28
10k
DNP
NC1
NC2
NC3
NC4
2
R29
10k
DNP
5
VBAT
U5
A
VDD12_BYP
VDD12_BYP
VDD12_BYP
PRTPWR
OCS_N
5
6
USB-A
2
REF_SEL0
REF_SEL1
VCC
DD+
GND
+C9
150uF
1
PORTPWR
OCSN
SHLD1
SHLD2
P3
ZERO
18
17
INT_N
10
9
5
6
USB-A
DATA
STROBE
ZERO DNP
B
VCC
DD+
GND
+C15
IN
GND
C20
0.1uF MIC2026-1B
25
C6 10k
0.1uF
EN
28
R17
1k
VDD_CORE_REG
Digital Control
R22
1k
C18
Y1
1
R26
10k
C11
ENA
ENB
VBAT
R11
R34
10k
1
4
VBAT
R/ANGLE USB A CON
VDD_CORE
R/ANGLE USB A CON
ZERO
OSC
P1
R/ANGLE USB A CON
VDD_PU
U4
Date:
2
Document Number
Rev
A
SCH-7265AZ-A00
Monday, September 16, 2013
Sheet
1
1
of
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