MIC68220YML Evaluation Board User Guide

MIC68220 Evaluation Board
Dual 2A Sequencing LDO with Tracking
and Ramp Control™
General Description
Features
The MIC68220 Evaluation Board contains a
MIC68220 chip with built-in resistor dividers, delay
and ramp capacitors, and programmable jumpers to
allow a variety of Master/Slave configurations
including sequencing, tracking, and ratiometric
tracking.
The MIC68220 operates from a wide input range of
1.65V to 5.5V. The MIC68220 incorporates a delay
pin (Delay) for control of power on reset output (POR)
at turn-on and power-down delay at turn-off. In
addition there is a ramp control pin (RC) for either
tracking applications or output voltage slew rate
adjustment at turn-on. On board jumpers allow
selection of on board delay caps, tracking, or
sequencing mode.
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Stable with 4.7uF ceramic capacitor
Input voltage range: 1.65V to 5.5V
Adjustable output voltage down to 0.5V
2A maximum output current – peak start up
1A Continuous Operating Current
Tracking on turn-on and turn-off
Timing Controlled Sequencing
Programmable Ramp Control™
Power-on Reset (POR) supervisor with
programmable delay time
Master and Slave devices in one IC
Tiny 4mm x 5mm MLF® package
Terminal Description
PCB
Connections
Terminal
Name
Terminal Function
J1
VIN1
VIN1
J2
POR1
Power On Reset1 (Power Good Flag)
J3
GND
GND
J4
VO1
Output1
J5
GND
GND
J6
VIN2
VIN2
J7
POR2
Power On Reset2 (Power Good Flag)
J8
GND
GND
J9
VO2
Output – Device 2
MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
February 2007
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MIC68220
Schematic
Programming Jumpers
Jumper Number
Jumper Name
Jumper Function
JP1
U1 Adj Voltage
Select
[1:2] – 3.3V
JP2
RC1 Source
[1:2] – Use VO2 (Tracking);
JP3
Delay1 Source
[1:2] – Use C2 (on board delay);
[2:3] – NC (min delay)
JP4
EN1 Source
[1:2] – Use VIN1 (Fastest Turn-On);
[2:3] – Use POR2 (Sequencing)
[3:4] – 2.5V
[5:6] – 1.8V
No Jumper – 0.5V
[2:3] – Use C3 (on board ramp slope)
JP5
POR1 Source
[1:2] – Use VIN1;
JP6
U2 Adj Voltage
Select
[1:2] – 1.2V
JP7
RC2 Source
[1:2] – Use C7 (on board ramp slope);
JP8
Delay2 Source
[1:2] – NC (min delay);
JP9
EN2 Source
[1:2] – Use VIN2 (Fastest Turn-On);
JP10
POR2 Source
[1:2] – Use VIN2;
February 2007
[7:8] – 1.5V
[2:3] – Use VO1 (min Q Current)
[3:4] – 1.5V
[5:6] – 1.8V
No Jumper – 0.5V
[7:8] – 2.5V
[2:3] – Use VO1 (Tracking)
[2:3] – Use C6 (on board delay)
[2:3] – Use POR1 (Sequencing)
[2:3] – Use VO2 (min Q Current)
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MIC68220
Ordering Information
Part Number
Description
MIC68220YML EV
Evaluation board with MIC68220YML adjustable device.
NOTE: For additional voltage options, contact Micrel Marketing.
Applications Information
Typical Jumper Connections
Enable
Input
VIN1 & VIN2
J1 & J6
JP1
VO
1
JP2
RC
1
JP3
DLY
1
JP4
EN
1
JP5
POR
1
JP6
VO
2
JP7
RC
2
JP8
DLY
2
JP9
EN
2
JP10
POR2
2
Delayed Sequencing:
U1 Slave w/ VOUT = 1.8V
U2 Master w/ VOUT = 2.5V
JP9.2
3.3V
5:6
NC
1:2
2:3
1:2
7:8
NC
1:2
EXT
1:2
Windowed Sequencing:
U1 Master w/ VOUT = 2.5V
U2 Slave w/ VOUT = 1.8V
JP4.2
3.3V
3:4
NC
1:2
EXT
1:2
4:5
NC
1:2
2:3
1:2
Normal Tracking:
U1 Master w/ VOUT = 2.5 V
U2 Slave w/ VOUT = 1.8V
JP4.2
&
JP9.2
3.3V
3:4
2:3
1:2
EXT
1:2
4:5
2:3
1:2
EXT
1:2
Ratiometric Tracking:
U1 Master w/ VOUT = 2.5 V
U2 Slave w/ VOUT = 1.8V
JP4.2
&
JP9.2
3:4
1:2
*
1:2
EXT
1:2
4:5
2:3
*
1:2
EXT
1:2
Description
3.3V
External jumper between JP2.2 and JP7.2
Delayed Sequencing
February 2007
Normal Tracking
3
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MIC68220
Windowed Sequencing
February 2007
Ratiometric Tracking
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MIC68220
is:
Enable Input
The enable inputs are programmed via JP4
(Channel1) and JP9 (Channel2). Either device may
be enabled 3 ways:
1. From VIN (short pins 1 & 2),
2. From POR of adjacent device (short pins 2 &
3)
3. From External source (drive pin 2)
Voltage Adjustment
Target voltage for VO1 is controlled via JP1. Jumper
settings are:
1. Pins 1&2 – 3.3V
2. Pins 3&4 – 2.5V
3. Pins 5&6 – 1.8V
4. Pins 7&8 – 1.5V
Target voltage for VO2 is controlled via JP6. Jumper
settings are:
1. Pins 1&2 – 1.2V
2. Pins 3&4 – 1.5V
3. Pins 5&6 – 1.8V
4. Pins 7&8 – 2.5V
Other voltages are possible by changing resistor
values.
The formula for output voltage given
resistance R from device pin 18(U1) or 13(U2) to GND
February 2007
VOUT = 0.5 x ( 1 + ( 10.0K / R ) )
Power on Reset (POR)
POR may be observed via J2 (for Output1) or J7 (for
Output2). Jumpers JP5 (for Channel1) or JP10 (for
Channel2) allow the POR pullup resistor to be
supplied from either VIN or VOUT.
Delay Programming
The Delay is programmed via JP3 (for channel1) or
JP8 (for channel2). For channel1 delay can be either
minimum (Open, or Pins 2&3 shorted) or
approximately 1mSec (Pins 1&2 shorted).
For
channel2 delay can be either minimum (Open, or Pins
1&2 shorted) or approximately 2mSec (Pins 2&3
shorted).
Ramp Control
Ramp Control and Tracking is programmed via JP2
(for channel1) or JP7 (for channel2). Shorting Pins
2&3 sets the output turn-on slew time (time from turn
on to full output) to approximately 0.5mSec for
Channel1 or 1.0mSec for Channel2. Shorting Pins
1&2 of JP4 causes channel1 to track channel2.
Shorting Pins 2&3 of JP9 causes channel2 to track
channel1.
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MIC68220
Bill of Materials
Item
Part Number
Manufacturer
Description
C1, C5
C1608 X5R 0J 106M
TDK
10µF/6.3V X5R
2
GRM188R60J106M
muRATA
06036D106KAT
AVX
C1608 X5R 0J 475M
TDK
4.7uF/6.3V X5R
2
GRM188R60J475KE19D
muRATA
08056D475MAT
AVX
C4, C8
Qty.
C2
VJ0603A102KXQPW1BC
Vitramon
1nF/25V
1
C3,C6,
C7
VJ0603Y222KXXCW1BC
Vitramon
2.2nF/25V
3
R1, R6,
R8, R9,
R14
CRCW06031002FKEYE3
Vishay Dale
10K , 0603, 1/16W, 1%
4
R2, R12
CRCW06034991FKEYE3
Vishay Dale
4.99K , 0603, 1/16W, 1%
2
R3, R11
CRCW06033831FKEYE3
Vishay Dale
3.83K , 0603, 1/16W, 1%
2
R4, R10
CRCW06032491FKEYE3
Vishay Dale
2.49K , 0603, 1/16W, 1%
2
R5
CRCW06031781FKEYE3
Vishay Dale
1.78K , 0603, 1/16W, 1%
1
R7
CRCW0603249RFKEYE3
Vishay Dale
249 , 0603, 1/16W, 1%
1
R16
CRCW06031001FKEYE3
Vishay Dale
1.0K , 0603, 1/16W, 1%
2
R13
CRCW06037151FKEYE3
Vishay Dale
7.15K , 0603, 1/16W, 1%
1
R15
CRCW06033830FKEYE3
Vishay Dale
383 , 0603, 1/16W, 1%
1
U1
MIC68220YML
Micrel, Inc.
2A FPGA LDO Regulator
1
Notes:
1. AVX: www.avx.com
2. Murata: www.murata.com
3. TDK: www.tdk.com
4. Vishay: www.vishay.com
5. Vitramon: www.vitramon.com
6. Micrel Semiconductor: www.micrel.com
February 2007
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M9999-020807
(408) 955-1690
Micrel, Inc.
MIC68220
PCB Layout Artwork
TOP
BOTTOM
TOP SILKSCREEN
BOTTOM SILKSCREEN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for
its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2007 Micrel, Incorporated.
February 2007
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