CDP1826C CMOS 64-Word x 8-Bit Static RAM March 1997 Features Description • Ideal for Small, Low-Power RAM Memory Requirements in Microprocessor and Microcomputer Applications The CDP1826C is a general purpose, fully static, 64-word x 8-bit random-access memory, for use in CDP1800-series or other microprocessor systems where minimum component count and/or price performance and simplicity in use are desirable. • Interfaces with CDP1800-Series Microprocessors Without Additional Address Decoding • Daisy Chain Feature to Further Reduce External Decoding Needs • Multiple Chip-Select Inputs for Versatility • Single Voltage Supply • No Clock or Precharge Required. Ordering Information PACKAGE PDIP TEMP. RANGE PART NUMBER -40oC to +85oC CDP1826CE Pinout CDP1826C (PDIP) TOP VIEW BUS 0 1 22 VDD BUS 1 2 21 A0 BUS 2 3 20 CS/A5 BUS 3 4 19 A1 BUS 4 5 18 A2 BUS 5 6 17 A3 BUS 6 7 16 A4 BUS 7 8 15 TPA CS1 9 14 MRD CS2 10 13 MWR VSS 11 12 CEO PKG. NO. E22.4 The CDP1826C has 8 common data input and data-output terminals with three-state capability for direct connection to a standard bidirectional data bus. Two chip-select inputs - CS1 and CS2 - are provided to simplify memory-system expansion. An additional select pin, CS/A5, is provided to enable the CDP1826C to be selected directly from the CDP1800 multiplexed address bus without additional latching or decoding. In an 1800 system, the CS/A5 pin can be tied to any MA address line from the CDP1800 processor. A TPA input is provided to latch the high-order bit of this address line as a chip-select for the CDP1826C. If this CS/A5 input is latched high, and if CS = 1 and CS2 = 0 at the appropriate time in the memory cycle, the CDP1826C will be enabled for writing or reading. In a non-1800 system, the TPA pin can be tied high, and the CS/A5 pin can be used as a normal address input. The six input-address buffers are gated with the chip-select function to reduce standby current when the device is deselected, as well as to provide for a simplified power down mode by reducing address buffer sensitivity to long fall times from address drivers which are being powered down. Two memory control signals, MRD and MWR, are provided for reading from the writing to the CDP1826C. The logic is designed so that MWR overrides MRD, allowing the chip to be controlled from a single R/W. A CHIP ENABLE OUTPUT is provided for daisy-chaining to additional memories or I/O devices. This output is high whenever the chip-select function selects the CDP1826C, which deselects any other chip which has its CS input connected to the CDP1826C CEO output. The connected chip is selected when the CDP1826C is deselected and the MRD input is low. Thus, the CEO is only active for a read cycle and can be setup so that a CEO of another device can feed the MRD of the CDP1826C, which in turn selects a third chip in the daisy chain. The CDP1826C has a recommended operating voltage of 4.5V to 5.5V and is supplied in 22 lead dual-in-line plastic packages (E suffix). The CDP1826C is also available in chip form (H suffix). CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 6-47 File Number 1311.2 CDP1826C CLEAR WAIT N0 - N2 MRD ADDR BUS ADDR BUS TPA TPA TPB Q DATA CPU CDP1800 SERIES RAM CDP1826C ROM MRD MRD SCO SCI INTERRUPT DMA - IN DMA OUT MWR CEO EF1 - EF4 8-BIT BIDIRECTIONAL DATA BUS FIGURE 1. TYPICAL CDP1802 MICROPROCESSOR SYSTEM 6-48 I/O CONTROL CDP1826C Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1826C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Power Dissipation Per Package (PD) TA = -40oC to +60oC (Package Type E) . . . . . . . . . . . . . . 500mW TA = +60oC to +85oC (Package Type E). . . . . . Derate Linearly at 12mW/oC to 200mW TA = -55oC to +100oC (Package Type D) . . . . . . . . . . . . . 500mW TA = +100oC to +125oC (Package Type D). . . . Derate Linearly at 12mW/oC to 200mW Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 ±1/32 In. (1.59 ±0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC Recommended Operating Conditions At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: CDP1826C PARAMETER SYMBOL MIN MAX UNITS 4 6.5 V VSS VDD V - 10 µs DC Operating Voltage Range Input Voltage Range Input Signal Rise or Fall Time, VDD = 5V Static Electrical Specifications tR, tF At TA = -40oC to +85oC, VDD = 5V ±5%, Except as Noted: CONDITIONS LIMITS CDP1826C PARAMETER Quiescent Device Current Output Low (Sink) Current BUS SYMBOL VO (V) VIN (V) MIN (NOTE 1) TYP MAX UNITS IDD - 0, VDD - 5 50 µA IOL 0.4 0, VDD 1.6 3.2 - mA 0.4 0, VDD 0.8 1.6 - mA VDD -0.4 0, VDD -1.0 -1.5 - mA VDD -0.4 0, VDD -0.6 -1.0 - mA CEO Output High (Source) Current BUS IOH CEO Output Voltage Low-Level VOL - 0, VDD - 0 0.1 V Output Voltage High-Level VOH - 0, VDD VDD -0.1 VDD - V Input Low Voltage VIL - - - - 1.5 V Input High Voltage VIH - - 3.5 - - V Input Leakage Current IIN Any Input 0, VDD - ±0.1 ±1 µA IOPER - 0, VDD - 5 10 mA Three-State Output Leakage Current IOUT 0, VDD 0, VDD - ±0.1 ±1 µA Input Capacitance CIN - - - 5 7.5 pF COUT - 0, VDD - 10 15 pF Operating Device Current (Note 2) Output Capacitance NOTES: 1. Typical values are for TA = +25oC and nominal VDD. 2. Outputs open circuited; Cycle time = 1µs. 6-49 CDP1826C Signal Descriptions A0 - A4, CS/A5 (Address Inputs): These inputs must be stable prior to a write operation, but may change asynchronously during Read operations. In an 1800 system, the multiplexed high-order address bit at pin CS/A5 can be latched at the end of TPA. A high level will provide a valid chip select for the CDP1826C. The low-order address bit which appears after TPA is used for data word selection. In non-1800 systems, TPA can be tied high to disable the latch and allow the CS/A5 pin to function as a normal address input. BUS 0 - BUS 7: 8-bit three-state common input/output data bus. TPA: High-order address strobe input. The high-order address bit at input CS/A5 is latched on the high-to-low tran- sition of the TPA input. Tie TPA high to disable the CS/A5 latch feature. CS1, CS2 (Chip Selector): Either chip select (CS1 or CS2), when not valid, powers down the chip, disables READ and WRITE functions, and gates off the address and output buffers. MRD, MWR: Read and Write control signals. MWR overrides MRD, allowing the CDP1826C to be controlled from a single R/W line. CEO (Chip Enable Output): Allows daisy chaining to additional memories. CEO is high whenever the CDP1826C is selected. CEO is only active (low) for a Read cycle with the CDP1826C deselected and the MRD input low. VDD, VSS: Power supply connections. BUS 0 A0 BUS 1 A1 INPUT ADDRESS BUFFERS A2 A3 64 x 8 MATRIX XY DECODE A4 INPUT/OUTPUT DATA BUFFERS AND CONTROL BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 CS/A5 BUS 7 D TPA C Q CS1 CS2 MWR CEO MRD FIGURE 2. FUNCTIONAL DIAGRAM 6-50 CDP1826C 1800 CLOCK A5 TPA MRD CEO BUS VALID DATA VALID DATA RAM CYCLE (RAM SELECTED) ROM CYCLE (RAM DESELECTED) CS1 = 1, CS2 = 0 OPERATING MODES CDP1800 Mode Non-CDP1800 Mode (NOTE 1) CS/A5 CEO I I I I I I I I I I I I Deselect I X O X X I Deselect O X O X X O Deselect I X X O I Deselect O X X O O FUNCTION MRD MWR CS1 • CS2 Write X O Read O Deselect TPA Write X O I I X I Read O I I I X I Deselect I I I I X I Deselect I X O I X I Deselect O X O I X O NOTE: 1. For CDP1800 Mode, refers to high order memory address bit level at time when TPA place. transition takes FIGURE 3. CHIP ENABLE OUTPUT TIMING WAVEFORMS FOR CDP1800 BASED SYSTEMS 6-51 CDP1826C Dynamic Electrical Specifications At TA = -40 to +85oC, VDD = 5V ±5%, Input tR, tF = 10ns; CL = 50pF and 1 TTL Load LIMITS CDP1826C PARAMETER (NOTE 1) MIN (NOTE 2) TYP MAX UNITS READ - CYCLE TIMES (FIGURES 4 AND 5) Address to TPA Setup tASH 100 - - ns Address to TPA Hold tAH 100 - - ns Access from Address Change TAA - 500 1000 ns TPA Pulse Width tPAW 200 - - ns Output Valid from MRD tAM - 500 1000 ns Access from Chip Select tAC - 500 1000 ns tCA - 150 300 ns MRD to CEO Delay tMC 75 - - ns Output High Z from Invalid MRD tRHZ - - 125 ns Output High Z from Chip Deselect tSHZ - - 225 ns CEO Delay from TPA Edge NOTES: 1. Time required by a limit device to allow tor the indicated function. 2. Typical values are or TA = 25oC and nominal VDD. A0 - A5 HIGH ORDER ADDRESS BYTE tASH LOW ORDER ADDRESS BYTE tAA tAH TPA tPAW MRD tAC CS1 - CS2 tRHZ VALID CHIP SELECT tCA tSHZ CEO tMC BUS VALID DATA HIGH IMPEDANCE tAM FIGURE 4. TIMING WAVEFORMS FOR READ CYCLE 1 6-52 CDP1826C HIGH ORDER ADDRESS BYTE A0 - A5 LOW ORDER ADDRESS BYTE tAA MRD tAC CS1 • CS2 tRHZ VALID CHIP SELECT tSHZ HIGH IMPEDANCE BUS VALID DATA tAM FIGURE 5. TIMING WAVEFORMS FOR READ-CYCLE 2 (TPA HIGH) Dynamic Electrical Specifications At TA = -40 to +85oC, VDD = 5V ± 5%,Input tR, tF = 10ns; CL = 50pF and 1 TTL Load LIMITS CDP1826C PARAMETER (NOTE 1) MIN (NOTE 2) TYP MAX UNITS WRITE - CYCLE TIMES (FIGURES 6 AND 7) Address to TPA Setup, High Byte tASH 100 - - ns Address to TPA Hold tAH 100 - - ns Address Setup, Low Byte TASL 500 250 - ns TPA Pulse Width tPAW 200 - - ns Chip Select Setup tCS 700 350 - ns Write Pulse Width tWW 300 200 - ns Write Recovery tWR 100 - - ns Data Setup tDS 400 200 - ns Data Hold from End of MWR tDH1 100 50 - ns Data Hold from End of Chip Select tDH2 125 50 - ns NOTES: 1. Time required by a limit device to allow tor the indicated function. 2. Typical values are for TA = 25oC and nominal VDD. 6-53 CDP1826C A0 - A5 HIGH ORDER ADDRESS BYTE tASH LOW ORDER ADDRESS BYTE tAH tWR tASL TPA tPAW tWW MWR tCS CS1 • CS2 VALID CHIP SELECT tDS BUS tDH1, tDH2 DATA IN STABLE FIGURE 6. TIMING WAVEFORMS FOR WRITE-CYCLE 1 A0 - A5 HIGH ORDER ADDRESS BYTE LOW ORDER ADDRESS BYTE tASL tWR tWW MWR tCS CS1 • CS2 VALID CHIP SELECT tDS BUS DATA IN STABLE FIGURE 7. TIMING WAVEFORMS FOR WRITE-CYCLE 2 (TPA = HIGH) 6-54 tDH1, tDH2 CDP1826C Data Retention Specifications At TA = -40 to +85oC, see Figure 8 LIMITS TEST CONDITIONS PARAMETER Minimum Data Retention Voltage VDR Data Retention Quiescent Current tDD Chip Deselect to Data Retention Time tCDR Recovery to Normal Operation Time tRC VDD to VDR Rise and Fall Time tR, tF CDP1826C VDR (V) VDD (V) MIN (NOTE 1) TYP MAX UNITS - - - 2 2.5 V 2.5 - - 5 25 µA - 5 600 - - ns - 5 600 - - ns 2.5 5 1 - - µA NOTE: 1. Typical values are or TA = 25oC and nominal VDD. DATA RETENTION MODE VDD 0.95 VDD 0.95 VDD VDR tCDR tF tR tRC CS1 VIH VIH VIL VIL FIGURE 8. LOW VDD DATA RETENTION TIMING WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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