CDP1821C/3 High-Reliability CMOS 1024-Word x 1-Bit Static RAM March 1997 Features Description • Static CMOS Silicon-On-Sapphire Circuitry CD4000Series Compatible The CDP1821C/3 is a 1024-word x 1-bit CMOS silicon-on-sapphire (SOS), fully static, random-access memory designed for use in CDP1800 microprocessor systems. This device has a recommended operating voltage range of 4V to 6.5V. • Compatible with CDP1800-Series Microprocessors at Maximum Speed • Fast Access Time. . . . . . . . . . . 100ns Typ. at VDD = 5V • Single Voltage Supply • No Precharge or External Clocks Required • Low Quiescent and Operating Power • Separate Data Inputs and Outputs • High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD • Memory Retention for Standby Battery Voltage Down to 2V at +25oC The output state of the CDP1821C/3 is a function of the input address and chip-select states only. Valid data will appear at the output in one access time following the latest address change to a selected chip. After valid data appears, the address may be changed immediately. It is not necessary to clock the chip-select input or any other input terminal for fully static operation; therefore the chip-select input may be used as an additional address input. When the device is in an unselected state (CS = 1), the internal write circuitry and output sense amplifier are disabled. This feature allows the three-state data outputs from many arrays to be OR-tied to a common bus for easy memory expansion. • Latch-Up-Free Transient-Radiation Tolerance Ordering Information PACKAGE SBDIP TEMP. RANGE PART NUMBER -55oC to +125oC CDP1821CD3 PKG. NO. D16.3 Pinout CDP1821C/3 (SBDIP) TOP VIEW CS 1 16 VDD A0 2 15 DI A1 3 14 RD/WR A2 4 13 A9 A3 5 12 A8 A4 6 11 A7 DO 7 10 A6 VSS 8 9 A5 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 6-5 File Number 2983.1 CDP1821C/3 Functional Block Diagram CS R/W ROW BUFFERS a0 A0 COL. 0 ROW 0 1/16 ROW DECODER a3 A3 16 x 32 CELL ARRAY VDD ROW 15 CS • R/W • A4 DI COL. 31 COLUMN BUFFERS A4 A5 DO 1/32 COLUMN DECODER A9 A4 DI CS • R/W • A4 a0 COLUMN BUFFERS ROW 16 1/16 ROW DECODER 16 x 32 CELL ARRAY VSS a3 ROW 31 COL. 0 COL. 31 ROW BUFFERS OPERATIONAL MODES INPUTS OUTPUT READ/WRITE R/W CHIP-SELECT CS Standby X 1 High Impedance Write 0 0 High Impedance Read 1 0 Contents of Addressed Call MODE X = Don’t Care Logic 1 = High Logic 0 = Low 6-6 DATA OUTPUT DO CDP1821C/3 Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 75 20 Maximum Operating Temperature Range (TA) . . . .-55oC to +125oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Lead Temperature (During Soldering) . . . . . . . . . +265oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150oC Recommended Operating Conditions TA = Full Package-Temperature Range. For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges: CDP1821CD/3 PARAMETER MIN MAX UNITS 4 6.5 V VSS VDD V DC Operating Voltage Range Input Voltage Range Static Electrical Specifications VDD = 5V ±5% -55oC, +25oC PARAMETER SYMBOL CONDITIONS +125oC MIN MAX MIN MAX UNITS - 260 - 1000 µA Quiescent Device Current (Note 1) IDD VIN = 0V or VDD Output Low Drive (Sink) Current (Note 1) IOL VOUT = 0.4V 2.7 - 1.6 - mA Output High Drive (Source) Current (Note 1) IOH VOUT = VDD -0.4V -1.3 - -0.8 - mA Output Voltage Low-Level VOL - - 0.1 - 0.5 V Output Voltage High-Level VOH - VDD -0.1 - VDD -0.5 - V Input Low Voltage VIL - - 0.3 VDD - 0.3 VDD V Input High Voltage VIH - 0.7 VDD - 0.7 VDD - V Input Current (Note 1) IIN VIN = 0V or VDD - 2.6 - 10 µA Three-State Output Leakage Current (Note 1) IOUT VIN = 0V or VDD - 2.6 - 10 µA Operating Current (Note 2) IDD1 - - 5 - 10 mA Input Capacitance CIN - - 7.5 - 7.5 pF COUT - - 15 - 15 pF Output Capacitance NOTES: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing 2. Measured with 1µs read-cycle time and outputs floating. 6-7 CDP1821C/3 Read Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF -55oC, +25oC +125oC SYMBOL VDD (V) MIN MAX MIN MAX UNITS Data Access Time (Note 1) tDA 5 - 190 - 255 ns Read Cycle Time tRC 5 190 - 255 - ns Output Enable Time tEN 5 65 - 90 - ns Output Disable Time tDIS 5 - 65 - 90 ns PARAMETER NOTE: 1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing. CS A0 - A9 tDOA (NOTE 1) (NOTE 2) tRC (NOTE 4) R/W (NOTE 3) tDOH (NOTE 5) DATA OUT (NOTE 5) DATA OUT VALID tAA NOTES: 1. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device. 2. Chip-Select (CS) permitted to change from low to high level or remain low. 3. Read/Write (R/W) must be at a high level during all address transitions. 4. Don’t care. 5. Data-Out (DO) is a high impedance within tDIS ns after the falling edge of R/W or the rising edge of CS. FIGURE 1. READ CYCLE TIMING DIAGRAM 6-8 HIGH IMPEDANCE CDP1821C/3 Write Cycle Dynamic Electrical Specifications tR, tF = 10ns, CL = 50pF -55oC, +25oC +125oC SYMBOL VDD (V) MIN MAX MIN MAX UNITS Write Cycle Time tWC 5 300 - 420 - ns Address Setup Time (Note 1) tAS 5 60 - 84 - ns Address Hold Time (Note1) tAH 5 130 - 180 - ns Input Data Setup Time (Note 1) tDS 5 90 - 125 - ns Input Data Hold Time (Note 1) tDH 5 60 - 84 - ns Read/Write Pulse Width Low (Note 1) tWL 5 110 - 155 - ns PARAMETER NOTE: 1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing. CS (NOTE 1) (NOTE 2) A0 - A9 tWC tWL R/W (NOTE 3) tAS tAH tDS DI tDH (NOTE 3) (NOTE 3) NOTES: 1. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device. 2. Chip-Select (CS) permitted to change from low to high level or remain low. 3. Don’t care. FIGURE 2. WRITE CYCLE TIMING DIAGRAM 6-9 CDP1821C/3 Data Retention Specifications -55oC, +25oC TEST CONDITIONS +125oC SYMBOL VDR (V) VDD (V) MIN MAX MIN MAX UNITS Minimum Data Retention Voltage (Note 1) VDD - - - 2 - 2.5 V Data Retention Quiescent Current (Note 1) IDD 2 - - 50 - 200 µA Chip Deselect to Data Retention Time tCDR - 5 450 - 650 - ns Recovery to Normal Operation Time tRC - 5 450 - 650 - ns PARAMETER NOTE: 1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing DATA RETENTION MODE VDD 0.95 VDD 0.95 VDD VDR tCDR tF tR tRC CS VIH VIH VIL VIL FIGURE 3. LOW VDD DATA RETENTION WAVEFORMS AND TIMING DIAGRAM Burn-In Circuit R A11 A0 A1 A2 A3 R R R R R A4 0 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 R R R R R 2.2 5.0 6.6 7.2 10.0 O1 O1 0 A9 A8 A7 VDD A0 A6 0 R RI µs VDD A10 R VDD/2 1.6 VDD A5 VDD A1 R = 8.2kΩ 20% RI = 2kΩ 20% PACKAGE D 0 VDD TEMPERATURE 7V +125oC A1 - A11 ARE DIVISION BY 2 BASED ON A0 DURATION 160 Hrs. FIGURE 4. DYNAMIC/OPERATING BURN-IN CIRCUIT AND TIMING DIAGRAM 6-10 CDP1821C/3 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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