ISL78010 Data Sheet May 3, 2011 Automotive Grade TFT-LCD Power Supply Features The ISL78010 is a multiple output regulator for use in all TFT-LCD automotive applications. It features a single boost converter with an integrated 2A FET, two positive LDOs for VON and VLOGIC generation, and a single negative LDO for VOFF generation. The boost converter can be programmed to operate in either P-mode for optimal transient response or PI-mode for improved load regulation. • 2A current FET • 3V to 5V input • Up to 20V boost output • 1% regulation on boost output • VLOGIC-VBOOST-VOFF-VON or VLOGIC-VOFF-VBOOST-VON sequence control • Programmable sequence delay • Fully fault protected • Thermal shutdown • Internal soft-start The ISL78010 also includes an integrated start-up sequence for VLOGIC, VBOOST, VOFF, then VON or for VLOGIC, VOFF, VBOOST, and VON. The latter sequence requires a single external transistor. The timing of the start-up sequence is set using an external capacitor. • 32 Ld 5x5 TQFP packages The ISL78010 comes in a 32 Ld 5x5 TQFP package and is specified for operation over a -40°C to +105°C temperature range. It is both AEC-Q100 rated and fully TS16949 compliant. Applications • AEC-Q100 Tested • TS16949 Compliant • Pb-free (RoHS compliant) • All Automotive LCD Displays Pinout Ordering Information 1 CINT FBB SGND EN 1 32 31 30 29 28 27 26 25 24 NC 2 23 NC DELB 3 22 PGND NC 4 21 PGND LX 5 20 PGND NC 6 19 PGND DRVP 7 18 NC NC 8 17 9 10 11 12 13 14 15 16 FBP 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78010. For more information on MSL please see techbrief TB363. NC VREF FBN NC 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. DRVN 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. SGND Evaluation Board VDD ISL78010EVAL1Z Q32.5x5 PG 32 Ld 5x5 TQFP NC 78010 ANZ CDLY ISL78010ANZ PKG. DWG. # DRVL PACKAGE (Pb-free) NC PART MARKING NC PART NUMBER (Notes 1, 2, 3) ISL78010 (32 LD 5X5 TQFP) TOP VIEW FBL The ISL78010 includes fault protection for all four channels. Once a fault is detected on either the VBOOST, VON or VOFF channels, the device is latched off until the input supply or EN is cycled. If a fault is detected on the VLOGIC channel, the device is latched off until the input supply is cycled. The VLOGIC channel is not affected by the EN function. FN6501.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2007, 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL78010 Absolute Maximum Ratings (TA = +25°C) Thermal Information VDELB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V VDRVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V VDRVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V VLX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V VDRVL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Thermal Resistance (Typical) (Notes 4, 5) ΘJA (°C/W) ΘJC (°C/W) 32 Ld 5x5 TQFP. . . . . . . . . . . . . . . . . . 71 25 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation . . . . .see “Typical Performance Curves” (page 5) Maximum Continuous Junction Temperature . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Operating Temperature . . . . . . . . . . . . . . .-40°C to +105°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. ΘJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For ΘJC, the “case temp” location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA. Electrical Specifications PARAMETER VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, limits over -40°C to +105°C temperature range, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C. DESCRIPTION CONDITION MIN (Note 6) TYP MAX (Note 6) UNIT 5.5 V SUPPLY VS Supply Voltage IS Quiescent Current 3 Enabled, LX not switching 1.7 2.5 mA Disabled 750 900 µA 1000 1100 kHz 20 V CLOCK fOSC Oscillator Frequency 900 VBOOST Boost Output Range 5.5 VFBB Boost Feedback Voltage BOOST VF_FBB FBB Fault Trip Point VREF Reference Voltage TA = +25°C 1.205 1.218 V 1.188 1.205 1.222 V 0.9 TA = +25°C DMAX Maximum Duty Cycle ILXMAX Current Switch ILEAK Switch Leakage Current rDS(ON) Switch ON-Resistance Eff Boost Efficiency See “Typical Performance Curves” (page 5) I(VFBB) Feedback Input Bias Current Pl mode, VFBB = 1.35V ΔVBOOST/ΔVIN Line Regulation CINT = 4.7nF, IOUT = 100mA, VIN = 3V to 5.5V V 1.19 1.215 1.235 V 1.187 1.215 1.238 V 85 % 2.0 VLX = 16V ΔVBOOST/ΔIBOOST Load Regulation - “P” Mode CINT pin strapped to VDD, 50mA < ILOAD < 250mA ΔVBOOST/ΔIBOOST Load Regulation - “PI” Mode CINT = 4.7nF, 50mA < IO < 250mA 2 1.192 A 10 85 µA 320 mΩ 92 % 50 500 nA 0.05 %/V 3 % 0.1 % FN6501.1 May 3, 2011 ISL78010 Electrical Specifications PARAMETER VCINT_T VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, limits over -40°C to +105°C temperature range, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued) DESCRIPTION CONDITION MIN (Note 6) CINT Pl Mode Select Threshold TYP MAX (Note 6) UNIT 4.7 4.8 V VON LDO VFBP FBP Regulation Voltage IDRVP = 0.2mA, TA = +25°C 1.176 1.2 1.224 V IDRVP = 0.2mA 1.172 1.2 1.228 V 0.87 0.92 V 250 nA VF_FBP FBP Fault Trip Point VFBP falling 0.82 IFBP FBP Input Bias Current VFBP = 1.35V -250 GMP FBP Effective Transconductance VDRVP = 25V, IDRVP = 0.2mA to 2mA ΔVON/ΔI(VON) VON Load Regulation I(VON) = 0mA to 20mA IDRVP DRVP Sink Current Max VFBP = 1.1V, VDRVP = 25V IL_DRVP DRVP Leakage Current VFBP = 1.5V, VDRVP = 35V FBN Regulation Voltage IDRVN = 0.2mA, TA = +25°C 2 50 ms -0.5 % 4 mA 0.1 5 µA 0.173 0.203 0.233 V IDRVN = 0.2mA 0.171 0.203 0.235 V 0.43 0.48 V 250 nA VOFF LDO VFBN VF_FBN FNN Fault Trip Point VFBN falling 0.38 IFBN FBN Input Bias Current VFBN = 0.2V -250 GMN FBN Effective Transconductance VDRVN = -6V, IDRVN = 0.2mA to 2mA ΔVOFF/ ΔI(VOFF) VOFF Load Regulation I(VOFF) = 0mA to 20mA IDRVN DRVN Source Current Max VFBN = 0.3V, VDRVN = -6V IL_DRVN DRVN Leakage Current VFBN = 0V, VDRVN = -20V FBL Regulation Voltage IDRVL = 1mA, TA = +25°C 2 50 mS -0.5 % 4 mA 0.1 5 µA 1.176 1.2 1.224 V IDRVL = 1mA 1.174 1.2 1.226 V 0.87 0.92 V 500 nA VLOGIC LDO VFBL VF_FBL FBL Fault Trip Point VFBL falling 0.82 IFBL FBL Input Bias Current VFBL = 1.35V -500 GML FBL Effective Transconductance VDRVL = 2.5V, IDRVL = 1mA to 8mA 200 mS ΔVLOGIC/ ΔI(VLOGIC) VLOGIC Load Regulation I(VLOGIC) = 100mA to 500mA 0.5 % IDRVL DRVL Sink Current Max VFBL = 1.1V, VDRVL = 2.5V 16 mA IL_DRL IL_DRVL VFBL = 1.5V, VDRVL = 5.5V 0.1 tON Turn On Delay CDLY = 0.22µF 30 ms tSS Soft-start Time CDLY = 0.22µF 2 ms tDEL1 Delay Between AVDD and VOFF CDLY = 0.22µF 10 ms tDEL2 Delay Between VON and VOFF CDLY = 0.22µF 17 ms IDELB DELB Pull-down Current VDELB > 0.6V 50 µA VDELB < 0.6V 1.4 mA 8 5 µA SEQUENCING 3 FN6501.1 May 3, 2011 ISL78010 Electrical Specifications PARAMETER VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, limits over -40°C to +105°C temperature range, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued) DESCRIPTION MIN (Note 6) CONDITION TYP MAX (Note 6) UNIT FAULT DETECTION tFAULT Fault Time Out OT Over-temperature Threshold IPG PG Pull-down Current CDLY = 0.22µF 50 ms 140 °C VPG > 0.6V 15 µA VPG < 0.6V 1.7 mA LOGIC ENABLE VHI Logic High Threshold VLO Logic Low Threshold ILOW Logic Low Bias Current IHIGH Logic High Bias Current 2.3 at VEN = 5V 12 V 0.8 V 0.2 2 µA 18 24 µA NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Pin Descriptions PIN NAME PIN NUMBER DESCRIPTION 1, 2, 4, 6, 8, 10, 12, 16, 18, 23, 32 NC 3 DELB 5 LX 7 DRVP Positive LDO base drive; open drain of an internal N-Channel FET 9 FBP Positive LDO voltage feedback input pin; regulates to 1.2V nominal 11 DRVL Logic LDO base drive; open drain of an internal N-Channel FET 13 FBL Logic LDO voltage feedback input pin; regulates to 1.2V nominal 14, 27 SGND Low noise signal ground 15 DRVN Negative LDO base drive; open drain of an internal P-Channel FET 17 FBN Negative LDO voltage feedback input pin; regulates to 0.2V nominal 19, 20, 21, 22 PGND Power ground, connected to source of internal N-Channel boost FET 24 VREF Bandgap reference output voltage; bypass with a 0.1µF to SGND 25 CINT VBOOST integrator output; connect capacitor to SGND for PI-mode or connect to VDD for P-mode operation 26 FBB Boost regulator voltage feedback input pin; regulates to 1.2V nominal 28 EN Enable pin; High = Enable; Low or floating = Disable 29 VDD 30 PG 31 CDLY Not connected Open drain output for gate drive of optional VBOOST delay FET Drain of the internal N-Channel boost FET Positive supply Push-pull gate drive of optional fault protection FET; when chip is disabled or when a fault has been detected, this is high 4 A capacitor connected from this pin to SGND sets the delay time for start-up sequence and sets the fault timeout time FN6501.1 May 3, 2011 ISL78010 Typical Performance Curves TA = +25°C, unless otherwise specified. 100 100 AVDD = 9V 80 AVDD = 15V 60 AVDD = 12V 40 EFFICIENCY (%) EFFICIENCY (%) 80 20 0 AVDD = 15V 60 AVDD = 12V AVDD = 9V 40 20 0 100 200 300 0 400 0 200 400 600 800 IOUT (mA) IOUT (mA) FIGURE 1. VBOOST EFFICIENCY AT VIN = 3V (PI-MODE) FIGURE 2. VBOOST EFFICIENCY AT VIN = 5V (PI-MODE) 100 100 AVDD = 9V 80 AVDD = 15V 60 AVDD = 12V EFFICIENCY (%) EFFICIENCY (%) 80 40 20 0 AVDD = 15V 60 AVDD = 9V 40 20 0 100 200 300 400 0 500 0 200 600 800 FIGURE 4. VBOOST EFFICIENCY AT VIN = 5V (P-MODE) 0 0 -0.1 LOAD REGULATION (%) LOAD REGULATION (%) 400 IOUT (mA) IOUT (mA) FIGURE 3. VBOOST EFFICIENCY AT VIN = 3V (P-MODE) AVDD = 9V -0.2 -0.3 AVDD = 15V -0.4 -0.5 AVDD = 12V -0.6 -0.7 AVDD = 12V 0 100 200 300 400 IOUT (mA) FIGURE 5. VBOOST LOAD REGULATION AT VIN = 3V (PI-MODE) 5 -0.2 AVDD = 9V -0.4 AVDD = 12V -0.6 AVDD = 15V -0.8 -1.0 0 200 400 600 800 IOUT (mA) FIGURE 6. VBOOST LOAD REGULATION AT VIN = 5V (PI-MODE) FN6501.1 May 3, 2011 ISL78010 Typical Performance Curves TA = +25°C, unless otherwise specified. (Continued) 0 -0.5 LOAD REGULATION (%) LOAD REGULATION (%) 0 -1.0 -1.5 -2.0 AVDD = 9V -2.5 AVDD = 15V -3.0 -3.5 -4.0 AVDD = 12V 0 100 200 300 IOUT (mA) 400 -2 AVDD = 9V -3 AVDD = 12V -4 -5 500 AVDD = 15V 0 200 400 0 LINE REGULATION (%) 0.04 0.03 0.02 0.01 0 -0.01 -0.02 3.0 3.5 4.0 4.5 5.0 5.5 -0.5 -1.0 1.5 -2.0 -2.5 6.0 3.0 3.5 4.0 VIN (V) FIGURE 9. VBOOST LINE REGULATION (PI-MODE) 4.5 VIN (V) 5.0 5.5 6.0 FIGURE 10. VBOOST LINE REGULATION (P-MODE) 0 LOAD REGULATION (%) 0 LOAD REGULATION (%) 800 FIGURE 8. VBOOST LOAD REGULATION AT VIN = 5V (P-MODE) 0.05 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 600 IOUT (mA) FIGURE 7. VBOOST LOAD REGULATION AT VIN = 3V (P-MODE) LINE REGULATION (%) -1 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 0 20 40 60 IOUT (mA) FIGURE 11. VON LOAD REGULATION 6 80 0 20 40 60 80 100 IOUT (mA) FIGURE 12. VOFF LOAD REGULATION FN6501.1 May 3, 2011 ISL78010 Typical Performance Curves TA = +25°C, unless otherwise specified. (Continued) LOAD REGULATION (%) 0 -0.2 VCDLY -0.4 VREF -0.6 -0.8 VBOOST -1.0 VLOGIC -1.2 0 100 200 300 400 500 CDLY = 220nF 700 600 TIME (10ms/DIV) IOUT (mA) FIGURE 13. VLOGIC LOAD REGULATION FIGURE 14. START-UP SEQUENCE VBOOST VBOOST_DELAY VLOGIC VLOGIC VOFF VON VOFF CDLY = 220nF VON CDLY = 220nF TIME (10ms/DIV) TIME (10ms/DIV) FIGURE 15. START-UP SEQUENCE FIGURE 16. START-UP SEQUENCE VIN = 5V VOUT = 13V IOUT = 30mA VIN = 5V VOUT = 13V IOUT = 200mA TIME (400ns/DIV) TIME (400ns/DIV) FIGURE 17. LX WAVEFORM - DISCONTINUOUS MODE FIGURE 18. LX WAVEFORM - CONTINUOUS MODE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSIPATION (W) 1.8 1.5 1.408W 1.2 θ (5 m TQ m F x P 71 5m °C m /W ) JA = 0.9 0.6 0.3 0 0.282W 0 25 50 75 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 7 FN6501.1 May 3, 2011 ISL78010 Applications Information Boost Converter The ISL78010 provides a highly integrated multiple output power solution for TFT-LCD automotive applications. The system consists of one high efficiency boost converter and three linear-regulator controllers (VON, VOFF, and VLOGIC) with multiple protection functions. A block diagram is shown in Figure 20. Table 1 lists the recommended components. The main boost converter is a current mode PWM converter at a fixed frequency of 1MHz, which enables the use of low profile inductors and multi-layer ceramic capacitors. This results in a compact, low cost power system for LCD panel design. The ISL78010 integrates an N-Channel MOSFET boost converter to minimize external component count and cost. The AVDD, VON, VOFF, and VLOGIC output voltages are independently set using external resistors. VON, VOFF voltages require external charge pumps which are post regulated using the integrated LDO controllers. TABLE 1. RECOMMENDED TYPICAL APPLICATION DIAGRAM COMPONENTS DESIGNATION DESCRIPTION C1, C2, C3 10µF, 16V X7R ceramic capacitor (1206) TDK C3216X7RIC106M C20, C31 4.7µF, 25V X5R ceramic capacitor (1206) TDK C3216X5R1A475K D1 1A, 20V low leakage Schottky rectifier (CASE 457-04) ON SEMI MBRM120ET3 D11, D12, D21 200mA, 30V Schottky barrier diode (SOT-23) Fairchild BAT54S The ISL78010 is designed for continuous current mode, but it can also operate in discontinuous current mode at light load. In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by Equation 1: A VDD 1 ---------------- = -----------V IN 1–D (EQ. 1) where D is the duty cycle of the switching MOSFET. Figure 21 shows the block diagram of the boost regulator. It uses a summing amplifier architecture consisting of GM stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60kΩ is recommended. The boost converter output voltage is determined by Equation 2: L1 6.8µH, 1.3A Inductor TDK SLF6025T-6R8M1R3-PF Q1 -2.4, -20V P-Channel 1.8V specified PowerTrench MOSFET (SuperSOT-3) Fairchild FDN304P Q2 200mA, 40V NPN amplifier (SOT-23) Fairchild MMBT3904 Q3 200mA, 40V PNP amplifier (SOT-23) Fairchild MMBT3906 R1 + R2 A VDD = --------------------- × V REF R1 Q4 -2A, -30V single P-Channel logic level PowerTrench MOSFET (SuperSOT-3) Fairchild FDN360P The current through the MOSFET is limited to 2A peak. This restricts the maximum output current based on Equation 3: Q5 1A, 30V PNP low saturation amplifier (SOT-23) Fairchild FMMT549 ΔI L V IN I OMAX = ⎛ I LMT – --------⎞ × --------⎝ 2 ⎠ VO (EQ. 2) (EQ. 3) Where ΔIL is peak to peak inductor ripple current, and is set by Equation 4: V IN D ΔI L = --------- × ----L fS (EQ. 4) where fS is the switching frequency. 8 FN6501.1 May 3, 2011 ISL78010 EN REFERENCE GENERATOR VREF SGND OSCILLATOR SLOPE COMPENSATION COMP OSC PWM LOGIC CONTROLLER Σ LX BUFFER VOLTAGE AMPLIFIER FBB GM AMPLIFIER CINT CURRENT AMPLIFIER UVLO COMPARATOR EN VDD SHUTDOWN AND START-UP CONTROL PG THERMAL SHUTDOWN CURRENT REF CURRENT LIMIT COMPARATOR VREF + - DRVP BUFFER FBP UVLO COMPARATOR CDLY SS + - DRVN PGND 0.2V VREF DELB SS + - DRVL BUFFER BUFFER FBN FBL 0.4V UVLO COMPARATOR UVLO COMPARATOR FIGURE 20. BLOCK DIAGRAM 9 FN6501.1 May 3, 2011 ISL78010 CLOCK SHUTDOWN AND STARTUP CONTROL SLOPE COMPENSATION IFB IREF CURRENT AMPLIFIER PWM LX LOGIC BUFFER IFB FBB GM AMPLIFIER IREF VOLTAGE AMPLIFIER REFERENCE GENERATOR CINT PGND FIGURE 21. BLOCK DIAGRAM OF THE BOOST REGULATOR 10 FN6501.1 May 3, 2011 ISL78010 Table 2 gives typical values (margins are considered 10%, 3%, 20%, 10%, and 15%) on VIN, VO, L, fS, and IOMAX. TABLE 2. TYPICAL VIN, VO, L, fS, AND IOMAX VALUES capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. VIN (V) VO (V) L (µH) fS (MHz) IOMAX (A) 3.3 9 6.8 1 0.490686 NOTE: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. COUT in Equation 7 assumes the effective value of the capacitor at a particular voltage and not the manufacturer’s stated value, measured at zero volts. 3.3 12 6.8 1 0.307353 Compensation 3.3 15 6.8 1 0.197353 5 9 6.8 1 0.743464 5 12 6.8 1 0.465686 5 15 6.8 1 0.29902 Input Capacitor An input capacitor is used to supply the peak charging current to the converter. It is recommended that CIN be larger than 10µF. The reflected ripple voltage will be smaller with larger CIN. The voltage rating of the input capacitor should be larger than the maximum input voltage. Boost Inductor The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. Values of 3.3µH to 10µH are to match the internal slope compensation. The inductor must be able to handle the following average (Equation 5) and peak (Equation 6) current: IO I LAVG = ------------1–D (EQ. 5) ΔI L I LPK = I LAVG + -------2 (EQ. 6) Rectifier Diode A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The rectifier diode must meet the output current and peak inductor current requirements. Output Capacitor The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor (Equation 7). IO V O – V IN 1 V RIPPLE = I LPK × ESR + ------------------------ × ---------------- × ----f V C O OUT (EQ. 7) S For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output 11 The ISL78010 can operate in either P-mode or PI-mode. P-mode may be preferred in applications where excellent transient load performance is required but regulation is not critical. Connecting the CINT pin directly to VIN will enable P-mode; for better load regulation, use PI-mode with a 4.7nF capacitor in series with a 10k resistor between CINT and ground. This value may be reduced to improve transient performance; however, very low values will reduce loop stability. Figures 5 through 10 show a comparison of P-mode vs PI-mode performance. Boost Feedback Resistors As the boost output voltage, AVDD, is reduced below 12V, the effective voltage feedback in the IC increases the ratio of voltage to current feedback at the summing comparator because R2 decreases relative to R1. To maintain stable operation over the complete current range of the IC, the voltage feedback to the FBB pin should be reduced proportionally, as AVDD is reduced. This can be accomplished by means of a series resistor-capacitor network (R7 and C7; Equations 8 and 9) in parallel with R1, with a pole frequency (fp) set to approximately 10kHz for C2 (effective) = 10µF and 4kHz for C2 (effective) = 30µF. 1 1 –1 R 7 = ⎛ ⎛ ----------------------⎞ – -------⎞ ⎝ ⎝ 0.1 × R ⎠ R ⎠ 2 1 (EQ. 8) 1 C 7 = ------------------------------------------------2 × 3.142 × f p × R 7 (EQ. 9) PI-Mode CINT (C23) and RINT (R10) The IC is designed to operate with a minimum C23 capacitor of 4.7nF and a minimum C2 (effective) = 10µF. Note that, for high voltage AVDD, the voltage coefficient of ceramic capacitors (C2) reduces their effective capacitance greatly; a 16V, 10µF ceramic can drop to around 3µF at 15V. To improve the transient load response of AVDD in PI-mode, a resistor may be added in series with the C23 capacitor. The larger the resistor, the lower the overshoot, but at the expense of stability of the converter loop, especially at high currents. With L = 10µH, AVDD = 15V, and C23 = 4.7nF, C2 (effective) should have a capacitance of greater than 10µF. RINT (R7) can have values up to 5kΩ for C2 (effective) up to 20µF and up to 10k for C2 (effective) up to 30µF. FN6501.1 May 3, 2011 ISL78010 Larger values of RINT (R7) may be possible if maximum AVDD load currents less than the current limit are used. To ensure AVDD stability, the IC should be operated at the maximum desired current and then the transient load response of AVDD should be used to determine the maximum value of RINT. Operation of the DELB Output Function An open drain DELB output is provided to allow the boost output voltage, developed at C2 (see “Typical Application Diagram” on page 18), to be delayed via an external switch (Q4) to a time after the VBOOST supply and negative VOFF charge pump supply have achieved regulation during the start-up sequence shown in Figures 14 and 16. This then allows the AVDD and VON supplies to start-up from 0V instead of the normal offset voltage of VIN-VDIODE (D1) if Q4 were not present. When DELB is activated by the start-up sequencer, it sinks 50µA, allowing a controlled turn-on of Q4 and charge-up of C9. C16 can be used to control the turn-on time of Q4 to reduce in-rush current into C9. The potential divider formed by R9 and R8 can be used to limit the VGS voltage of Q4 if required by the voltage rating of this device. When the voltage at DELB falls to less than 0.6V, the sink current is increased to ~1.2mA to firmly pull DELB to 0V. The voltage at DELB is monitored by the fault protection circuit so that if the initial 50µA sink current fails to pull DELB below ~0.6V after the start-up sequencing has completed, then a fault condition will be detected and a fault time-out ramp will be initiated on the CDEL capacitor (C7). Operation of the PG Output Function The PG output consists of an internal pull-up PMOS device to VIN, to turn off the external Q1 protection switch, and a current-limited pull-down NMOS device which sinks ~15µA, allowing a controlled turn-on of Q1 gate capacitance. CO is used to control how fast Q1 turns on and limiting inrush current into C1. When the voltage at the PG pin falls to less than 0.6V, the PG sink current is increased to ~1.2mA to firmly pull the pin to 0V. The voltage at PG is monitored by the fault protection circuit so that if the initial 15µA sink current fails to pull PG below ~0.6V after the start-up sequencing has completed, then a fault condition will be detected, and a fault time-out ramp will be initiated on the CDEL capacitor (C7). Cascaded MOSFET Application A 20V N-Channel MOSFET is integrated in the boost regulator. For applications where the output voltage is greater than 20V, an external cascaded MOSFET is needed as shown in Figure 22. The voltage rating of the external MOSFET should be greater than VBOOST. 12 VBOOST VIN LX FB ISL78010 FIGURE 22. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS Linear-Regulator Controllers (VON, VLOGIC, and VOFF) The ISL78010 includes three independent linear-regulator controllers, in which two are positive output voltage (VON and VLOGIC) and one is negative. The VON, VOFF, and VLOGIC linear-regulator controller functional diagrams are shown in Figures 23, 24, and 25, respectively. Calculation of the Linear Regulator Base-Emitter Resistors (RBL, RBP and RBN) For the pass transistor of the linear regulator, low frequency gain (hFE) and unity gain frequency (fT) are usually specified in the datasheet. The pass transistor adds a pole to the loop transfer function at fp = fT/hFE. Therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high-frequency, low-gain switching transistor. Further improvement can be obtained by adding a base-emitter resistor RBE (RBP, RBL, RBN in the Functional Block Diagrams on page 13), which increase the pole frequency to fp = fT*(1+ hFE *re/RBE)/hFE, where re = KT/qIc. Choose the lowest value RBE in the design as long as there is still enough base current (IB) to support the maximum output current (IC). For example, if in the VLOGIC linear regulator, a Fairchild FMMT549 PNP transistor is used as the external pass transistor (Q5 in the application diagram), then for a maximum VLOGIC operating requirement of 500mA, the data sheet indicates hFE(min) = 100. The base-emitter saturation voltage is Vbe_max = 1.25V. Note that this is normally Vbe ~ 0.7V; however, for the Q5 transistor, an internal Darlington arrangement is used to increase its current gain, giving a “base-emitter” voltage of 2 x VBE. Note also that using a high current Darlington PNP transistor for Q5 requires that VIN > VLOGIC + 2V. Should a lower input voltage be required, then an ordinary high-gain PNP transistor should be selected for Q5 to allow a lower collector-emitter saturation voltage. FN6501.1 May 3, 2011 ISL78010 For the ISL78010, the minimum drive current is as shown in Equation 10: I DRVL ( min ) = 8mA (EQ. 10) VIN OR VPROT (3V TO 6V) PG_LDOL The minimum base-emitter resistor, RBL, can now be calculated as shown in Equation 11: LDO_LOG 0.9V RBL 500Ω + - Q5 R BL ( min ) = V BE ( max ) ⁄ ( I DRVL ( min ) – I C ⁄ h FE ( min ) ) = (EQ. 11) 1.25V ⁄ ( 8mA – 500mA ⁄ 100 ) = 417Ω RL1 This is the minimum value that can be used. Choose a convenient value greater than this minimum value; for example, 500Ω. Larger values may be used to reduce quiescent current; however, regulation may be adversely affected by supply noise if the value of RBL is too high. VBOOST 0.1µF PG_LDOP RBP 7kΩ 0.1µF Q3 VON (TO 35V) DRVP RP1 FBP CON RP2 20kΩ + GMP 1: Np FIGURE 23. VON FUNCTIONAL BLOCK DIAGRAM LX 0.1µF CP (TO -26V) LDO_OFF PG_LDON 0.4V VREF + FBN 1: Nn 0.1µF RN2 20kΩ RN1 VOFF (TO -20V) + GMN DRVN 36V ESD CLAMP RBN 3kΩ Q2 COFF FIGURE 24. VOFF FUNCTIONAL BLOCK DIAGRAM 13 FBL + GML RL2 20kΩ 1: N1 FIGURE 25. VLOGIC FUNCTIONAL BLOCK DIAGRAM CP (TO 36V) 36V ESD CLAMP + - CLOG 10µF LX LDO_ON 0.9V VLOGIC (1.3V TO 3.6V) DRVL The VON power supply is used to power the positive supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_ON). The LDO_ON regulator uses an external PNP transistor as the pass element. The on-board LDO controller is a wide band (>10MHz) transconductance amplifier capable of 4mA drive current, which is sufficient for up to 40mA or more output current under the low dropout condition (forced beta of 10). Typical VON voltage supported by the ISL78010 ranges from +15V to +36V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 25% below the 1.2V reference. The VOFF power supply is used to power the negative supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_OFF). The LDO_OFF regulator uses an external NPN transistor as the pass element. The on-board LDO controller is a wide band (>10MHz) transconductance amplifier capable of 4mA drive current, which is sufficient for up to 40mA or more output current under the low dropout condition (forced beta of 10). Typical VOFF voltage supported by the ISL78010 ranges from -5V to -20V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 200mV above the 0.2V reference level. The VLOGIC power supply is used to power the logic circuitry within the LCD panel. The DC/DC may be powered directly from the low voltage input, 3.3V or 5.0V, or it may be powered through the fault protection switch. The LDO_LOGIC regulator uses an external PNP transistor as the pass element. The on-board LDO controller is a wide band (>10MHz) transconductance amplifier capable of 16mA drive current, which is sufficient for up to 160mA or FN6501.1 May 3, 2011 ISL78010 more output current under the low dropout condition (forced beta of 10). Typical VLOGIC voltage supported by the ISL78010 ranges from +1.3V to VDD - 0.2V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 25% below the 1.2V reference. CHARGE PUMP VIN OUTPUT OR AVDD 7kΩ DRVP Set-Up Output Voltage As shown in the “Typical Application Diagram” on page 18, the output voltages of VON, VOFF, and VLOGIC are as determined by Equations 12, 13 and 14: R 12⎞ ⎛ V ON = V REF × ⎜ 1 + ----------⎟ R 11⎠ ⎝ (EQ. 12) R 22 V OFF = V REFN + ---------- × ( V REFN – V REF ) R 21 (EQ. 13) R 42⎞ ⎛ V LOGIC = V REF × ⎜ 1 + ----------⎟ R 41⎠ ⎝ (EQ. 14) NPN CASCODE TRANSISTOR Q3 VON ISL78010 FBP FIGURE 26. CASCODE NPN TRANSISTOR CONFIGURATION FOR HIGH CHARGE PUMP OUTPUT VOLTAGE (>36V) where VREF = 1.2V and VREFN = 0.2V. LX 0.1µF Resistor networks in the order of 250kΩ, 120kΩ and 10kΩ are recommended for VON, VOFF and VLOGIC, respectively. AVDD 0.1µF Charge Pump To generate an output voltage higher than VBOOST, single or multiple stages of charge pumps are needed. The number of stages is determined by the input and output voltage. Use Equation 15 to calculate positive charge pump stages: V OUT + V CE – V INPUT N POSITIVE ≥ -------------------------------------------------------------V INPUT – 2 × V F (EQ. 15) 7kΩ DRVP Q3 0.1µF 0.1µF VON 0.47µF ISL78010 (>36V) 0.1µF 0.22µF FBP where VCE is the dropout voltage of the pass component of the linear regulator. It ranges from 0.3V to 1V depending on the transistor. VF is the forward-voltage of the charge pump rectifier diode. The number of negative charge pump stages is given by Equation 16: V OUTPUT + V CE N NEGATIVE ≥ ------------------------------------------------V INPUT – 2 × V F (EQ. 16) To achieve high efficiency and low material cost, the lowest number of charge pump stages that can meet the above requirements is preferred. High Charge Pump Output Voltage (>36V) Applications In applications where the charge pump output voltage is over 36V, an external NPN transistor must be inserted between the DRVP pin and the base of pass transistor Q3 as shown in Figure 26, or the linear regulator can control only one stage charge pump and regulate the final charge pump output as shown in Figure 27. 14 FIGURE 27. THE LINEAR REGULATOR CONTROLS ONE STAGE OF CHARGE PUMP Discontinuous/Continuous Boost Operation and its Effect on the Charge Pumps The ISL78010 VON and VOFF architecture uses LX switching edges to drive diode charge pumps from which LDO regulators generate the VON and VOFF supplies. Should a regular supply of LX switching edges be interrupted - for example, during discontinuous operation at light AVDD boost load currents - it may affect the performance of VON and VOFF regulation, depending on their exact loading conditions at the time. To optimize VON/VOFF regulation, the boundary of discontinuous/continuous operation of the boost converter can be adjusted, by suitable choice of inductor (given VIN, VOUT, switching frequency and the AVDD current loading), to be in continuous operation. FN6501.1 May 3, 2011 ISL78010 Equation 17 gives the boundary between discontinuous and continuous boost operation. Continuous operation (LX switching every clock cycle) requires: I AVDD ( load ) > D × ( 1 – D ) × V IN --------------------------------------------------------------------------------------2 × L × f OSC (EQ. 17) where the duty cycle, D = (AVDD - VIN)/AVDD For example, with VIN = 5V, fOSC = 1.0MHz and AVDD = 12V, continuous operation of the boost converter can be guaranteed as shown in Equations 18, 19, and 20: output until the boost is enabled internally. The delayed output appears at AVDD. VBOOST soft-starts at the beginning of the third ramp. The soft-start ramp depends on the value of the CDLY capacitor. For CDLY of 220nF, the soft-start time is ~2ms. VREF and VLOGIC turn on when input voltage (VDD) exceeds 2.5V. When a fault is detected, the outputs and the input protection will turn off but VREF will stay on. VOFF turns on at the start of the fourth peak. At the fifth peak, the open drain o/p DELB goes low to turn on the external PMOS Q4 to generate a delayed VBOOST output. L = 10μH and I AVDD > 61mA (EQ. 18) L = 6.8μH and I AVDD > 89mA (EQ. 19) VON is enabled at the beginning of the sixth ramp. AVDD, PG, VOFF, DELB and VON are checked at end of this ramp. L = 3.3μH and I AVDD > 184mA (EQ. 20) Fault Protection Charge Pump Output Capacitors Ceramic capacitors with low ESR are recommended. With ceramic capacitors, the output ripple voltage is dominated by the capacitance value. The capacitance value can be calculated as shown in Equation 21: I OUT C OUT ≥ -----------------------------------------------------2 × V RIPPLE × f OSC (EQ. 21) where fOSC is the switching frequency. Start-Up Sequence Figure 28 shows a detailed start-up sequence waveform. For a successful power-up, there should be six peaks at VCDLY. When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled. When the input voltage is higher than 2.5V, an internal current source starts to charge CCDLY to an upper threshold using a fast ramp followed by a slow ramp. During the initial slow ramp, the device checks whether there is a fault condition. If no fault is found, CCDLY is discharged after the first peak, and VREF turns on. During the second ramp, the device checks the status of VREF and over-temperature. At the peak of the second ramp, PG output goes low and enables the input protection PMOS Q1. Q1 is a controlled FET used to prevent in-rush current into VBOOST before VBOOST is enabled internally. Its rate of turn-on is controlled by Co. When a fault is detected, M1 will turn off and disconnect the inductor from VIN. With the input protection FET on, NODE1 (see “Typical Application Diagram” on page 18) will rise to ~VIN. Initially the boost is not enabled, so VBOOST rises to VIN-VDIODE through the output diode. Hence, there is a step at VBOOST during this part of the start-up sequence. If this step is not desirable, an external P-MOSFET can be used to delay the 15 During the start-up sequence, prior to BOOST soft-start, VREF is checked to be within ±20% of its final value, and the device temperature is checked. If either of these is not within the expected range, the part is disabled until the power is recycled or EN is toggled. If CDELAY is shorted low, then the sequence will not start, while if CDELAY is shorted H, the first down ramp will not occur and the sequence will not complete. Once the start-up sequence is completed, the chip continuously monitors CDLY, DELB, FBP, FBL, FBN, VREF, FBB, and PG, and checks for faults. During this time, the voltage on the CDLY capacitor remains at 1.15V until either a fault is detected or the EN pin is pulled low. A fault on CDELAY, VREF, or temperature will shut down the chip immediately. If a fault on any other output is detected, CDELAY will ramp up linearly with a 5µA (typical) current to the upper fault threshold (typically 2.4V), at which point the chip is disabled until the power is recycled or EN is toggled. If the fault condition is removed prior to the end of the ramp, the voltage on the CDLY capacitor returns to 1.15V. Typical fault thresholds for FBP, FBL, FBN, and FBB are included in the “Electrical Specifications” table beginning on page 2. PG and DELB fault thresholds are typically 0.6V. CINT has an internal current-limited clamp to keep the voltage within its normal range. If CINT is shorted low, the boost regulator will attempt to regulate to 0V. If CINT is shorted H, the regulator switches to P mode. If any of the regulated outputs (VBOOST, VON, VOFF or VLOGIC) are driven above their target levels, the drive circuitry will switch off until the output returns to its expected value. FN6501.1 May 3, 2011 CHIP DISABLED FAULT DETECTED VON SOFT-START DELB ON VOFF ON AVDD SOFT-START PG ON VREF, VLOGIC ON ISL78010 VCDLY VIN EN VREF VBOOST tON tOS VLOGIC VOFF tDEL1 DELAYED VBOOST tDEL2 START-UP SEQUENCE TIMED BY CDLY FAULT PRESENT tDEL3 NORMAL OPERATION VON FIGURE 28. START-UP SEQUENCE 16 FN6501.1 May 3, 2011 ISL78010 If VBOOST is excessively loaded, the current limit will prevent damage to the chip. While in current limit, the part acts like a current source, and the regulated output will drop. If the output drops below the fault threshold, a ramp will be initiated on CDELAY and, provided the fault is sustained, the chip will be disabled upon completion of the ramp. In some circumstances (depending on ambient temperature and thermal design of the board), continuous operation at current limit may result in the over-temperature threshold being exceeded, which will cause the part to disable immediately. All I/O also has ESD protection, which in many cases will also provide overvoltage protection relative to either ground or VDD. However, these will not generally operate unless absolute maximum ratings are exceeded. Component Selection for Start-Up Sequencing and Fault Protection Protection” on page 17 to avoid problems during initial evaluation and prototype PCB generation. Over-Temperature Protection An internal temperature sensor continuously monitors the die temperature. If the die temperature exceeds the thermal trip point of +140°C, the device will shut down. Layout Recommendation Device performance, including efficiency, output noise, transient response and control loop stability, is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. Some general guidelines for layout include: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. The CREF capacitor is typically set at 220nF and is required to stabilize the VREF output. The range of CREF is from 22nF to 1µF and should not be more than five times the capacitor on CDEL to ensure correct start-up operation. 3. Minimize the length of traces carrying fast signals and high current. The CDEL capacitor is typically 220nF and has a usable range from 47nF minimum to several microfarads. It is limited only by leakage in the capacitor reaching µA levels. 4. All feedback networks should sense the output voltage directly from the point of load, and be as far away from LX node as possible. CDEL should be at least 1/5 of the value of CREF. Note that with 220nF on CDEL the fault time-out will typically be 50ms, and the use of a larger or smaller value will vary this time proportionally (e.g., 1µF will give a fault time-out period of typically 230ms). Fault Sequencing The ISL78010 has advanced fault detection systems which protect the IC from both adjacent pin shorts during operation and shorts on the output supplies. A high-quality layout and design of the PCB with respect to grounding and decoupling is necessary to avoid falsely triggering the fault detection scheme, especially during start-up. See “Layout Recommendation” on page 17 and “Component Selection for Start-Up Sequencing and Fault 17 2. Place VREF and VDD bypass capacitors close to the pins. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point near the main decoupling capacitors. 6. A signal ground plane, separate from the power ground plane, should be used for ground return connections for feedback resistor networks (R1, R11, R41) and the VREF capacitor, C22; the CDELAY capacitor, C7; and the integrator capacitor, C23. 7. Minimize feedback input track lengths to avoid switching noise pickup. 8. Connect all "NC" pins to the ground plane to improve thermal performance and switching noise immunity between pins. An evaluation board, ISL78010EVAL1Z, is available to illustrate the proper layout implementation. See “Ordering Information” on page 1. FN6501.1 May 3, 2011 ISL78010 Typical Application Diagram LX VIN C0 C1 1nF 10µF x2 D1 6.8µH LX CDELAY C10 C2-C3 R9 10µF 1MΩ X2 R7 OPEN R2 R1 5kΩ FBB AVDD (12V) Q4 46.5kΩ PG C7 C9 C16 0.1µF 22nF R8 C7 OPEN 10kΩ 0.22µF 4.7µF C41 NODE 1 DELB R6 10Ω C6 4.7µF R7 10kΩ VDD CINT R41 FBP R12 C11 0.1µF C13 0.1µF C14 0.1µF Q3 C12 D12 0.1µF D11 VON (15V) 230kΩ R11 C15 20kΩ 0.47µF * FBL C24 LX 0.1µF R23 5kΩ * 1nF 7kΩ * 5.4kΩ CP DRVP 0.1µF R42 LX 4.7nF R13 DRVL Q5 10kΩ VREF C22 500Ω R10 C 23 EN 0.1µF VREF R43 VLOGIC (2.5V) C 31 4.7µF L1 NODE 1 Q1 C25 3kΩ DRVN FBN SGND PGND 0.1µF D21 Q2 R22 104k R21 C20 20k 4.7µF VREF * VOFF (-5V) * NOTE: SGND should be connected to PGND at one point only. 18 FN6501.1 May 3, 2011 ISL78010 Thin Plastic Quad Flatpack Packages (TQFP) Q32.5x5 (JEDEC MS-026AAA ISSUE B) 32 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE D MILLIMETERS D1 SYMBOL -D- -B- -A- E E1 e PIN 1 SEATING A PLANE -H- 0.08 0.003 -C- MIN MAX NOTES A - 1.20 - A1 0.05 0.15 - A2 0.95 1.05 - b 0.17 0.27 6 b1 0.17 0.23 - D 6.90 7.10 3 D1 4.90 5.10 4, 5 E 6.90 7.10 3 E1 4.90 5.10 4, 5 L 0.45 0.75 - N 32 7 e 0.50 BSC Rev. 0 2/07 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 0.08 0.003 M D S C A-B S b 11o-13o 0.020 0.008 MIN b1 0o MIN A2 A1 GAGE PLANE 0o-7o 11o-13o 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 0.09/0.16 0.004/0.006 BASE METAL WITH PLATING L 0.25 0.010 3. Dimensions D and E to be determined at seating plane -C- . 7. “N” is the number of terminal positions. 0.09/0.20 0.004/0.008 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN6501.1 May 3, 2011