PN7120 Full NFC Forum-compliant controller with integrated firmware and NCI interface Rev. 3.1 — 8 October 2015 312431 Product data sheet COMPANY PUBLIC 1. Introduction This document describes the functionality and electrical specification of the NFC Controller PN7120. Additional documents describing the product functionality further are available for design-in support. Refer to the references listed in this document to get access to the full for full documentation provided by NXP. 2. General description PN7120, the best plug'n play full NFC solution - easy integration into any OS environment, with integrated firmware and NCI interface designed for contactless communication at 13.56 MHz. It is the ideal solution for rapidly integrating NFC technology in any application, especially those running OS environment like Linux and Android, reducing Bill of Material (BOM) size and cost, thanks to: • full NFC forum compliancy (see Ref. 11) with small form factor antenna • embedded NFC firmware providing all NFC protocols as pre-integrated feature • direct connection to the main host or microcontroller, by I2C-bus physical and NCI protocol • ultra-low power consumption in polling loop mode • Highly efficient integrated power management unit (PMU) allowing direct supply from a battery PN7120 embeds a new generation RF contactless front-end supporting various transmission modes according to NFCIP-1 and NFCIP-2, ISO/IEC14443, ISO/IEC 15693, ISO/IEC 18000-3, MIFARE and FeliCa specifications. It embeds an ARM Cortex-M0 microcontroller core loaded with the integrated firmware supporting the NCI 1.0 host communication. The contactless front-end design brings a major performance step-up with on one hand a higher sensitivity and on the other hand the capability to work in active load modulation communication enabling the support of small antenna form factor Supported transmission modes are listed in Figure 1. For contactless card functionality, the PN7120 can act autonomously if previously configured by the host in such a manner. PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware PN7120 integrated firmware provides an easy integration and validation cycle as all the NFC real-time constraints, protocols and device discovery (polling loop) are being taken care internally. In few NCI commands, host SW can configure the PN7120 to notify for card or peer detection and start communicating with them. NFC FORUM NFC-IP MODES READER (PCD - VCD) CARD (PICC) READER FOR NFC FORUM TAGS 1 TO 4 ISO/IEC 14443 A ISO/IEC 14443 A ISO/IEC 14443 B ISO/IEC 14443 B P2P ACTIVE 106 TO 424 kbps INITIATOR AND TARGET ISO/IEC 15693 MIFARE 1K / 4K P2P PASSIVE 106 TO 424 kbps INITIATOR AND TARGET MIFARE DESFire Sony FeliCa(1) aaa-015868 (1) According to ISO/IEC 18092 (Ecma 340) standard. Fig 1. PN7120 transmission modes 3. Features and benefits Includes NXP ISO/IEC14443-A, Innovatron ISO/IEC14443-B and NXP MIFARE Crypto 1 intellectual property licensing rights ARM Cortex-M0 microcontroller core Highly integrated demodulator and decoder Buffered output drivers to connect an antenna with minimum number of external components Integrated RF level detector Integrated Polling Loop for automatic device discovery RF protocols supported NFCIP-1, NFCIP-2 protocol (see Ref. 7 and Ref. 10) ISO/IEC 14443A, ISO/IEC 14443B PICC mode via host interface (see Ref. 2) ISO/IEC 14443A, ISO/IEC 14443B PCD designed according to NFC Forum digital protocol T4T platform and ISO-DEP (see Ref. 11) FeliCa PCD mode MIFARE PCD encryption mechanism (MIFARE 1K/4K) NFC Forum tag 1 to 4 (MIFARE Ultralight, Jewel, Open FeliCa tag, DESFire) (see Ref. 11) ISO/IEC 15693/ICODE VCD mode (see Ref. 8) Supported host interfaces NCI protocol interface according to NFC Forum standardization (see Ref. 1) I2C-bus High-speed mode (see Ref. 3) PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Integrated power management unit Direct connection to a battery (2.3 V to 5.5 V voltage supply range) Support different Hard Power-Down/Standby states activated by firmware Autonomous mode when host is shut down Automatic wake-up via RF field, internal timer and I2C-bus interface Integrated non-volatile memory to store data and executable code for customization 4. Applications All devices requiring NFC functionality especially those running in an Android or Linux environment TVs, set-top boxes, Blu-ray decoders, audio devices Home automation, gateways, wireless routers Home appliances Wearables, remote controls, healthcare, fitness Printers, IP phones, gaming consoles, accessories 5. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions VBAT battery supply voltage Card Emulation and Passive Target; VSS = 0 V [1] Reader, Active Initiator and Active Target; VSS = 0 V [1] VDD supply voltage internal supply voltage VDD(PAD) VDD(PAD) supply voltage supply voltage for host interface IBAT battery supply current PN7120 Product data sheet COMPANY PUBLIC output current on pin VDD(PAD) Max Unit 2.3 - 5.5 V 2.7 - 5.5 V [2] [2] 1.65 1.8 1.95 V 1.8 V host supply; VSS = 0 V [1] 1.65 1.8 1.95 V 3.3 V host supply; VSS = 0 V [1] 3.0 - 3.6 V in Hard Power Down state; VBAT = 3.6 V; T = 25 °C - 10 12 A in Standby state; VBAT = 3.6 V; T = 25 °C - - 20 A in Monitor state; VBAT = 2.75 V; T = 25 °C - - 12 A in low-power polling loop; VBAT = 3.6 V; T = 25 °C; loop time = 500 ms - 150 - A - - 170 mA - - 15 [3] PCD mode at typical 3 V IO(VDDPAD) Min Typ total current which can be pulled on VDD(PAD) referenced outputs All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 mA © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 1. Quick reference data …continued Symbol Parameter Conditions Ith(Ilim) current limit threshold current current limiter on VDD(TX) pin; VDD(TX) = 3.1 V Min Typ Max Unit - 180 - mA Ptot total power dissipation Reader; IVDD(TX) = 100 mA; VBAT = 5.5 V - - 0.5 W Tamb ambient temperature JEDEC PCB-0.5 30 +25 [3] [4] +85 C [1] VSS represents VSS, VSS1, VSS2, VSS3, VSS4, VSS(PAD) and VSS(TX). [2] The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must be taken into account). [3] The antenna shall be tuned not to exceed the maximum of IVBAT. [4] This is the threshold of a built-in protection done to limit the current out of VDD(TX) in case of any issue at antenna pins to avoid burning the device. It is not allowed in operational mode to have IVDD(TX) such that IVBAT maximum value is exceeded. 6. Ordering information Table 2. Ordering information Type number Package Name PN7120A0EV/C1xxxx Description Version VFBGA49 plastic very thin fine-pitch ball grid array package; 49 balls SOT1320-1 7. Marking aaa-007526 Fig 2. PN7120 Product data sheet COMPANY PUBLIC PN7120 package marking (top view) All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 3. Marking code Line number Marking code Line 1 product version identification Line 2 diffusion batch sequence number Line 3 manufacturing code including: • diffusion center code: – N: TSMC – s: Global Foundry • assembly center code: – S: APK – X: ASEN • RoHS compliancy indicator: – D: Dark Green; fully compliant RoHS and no halogen and antimony • manufacturing year and week, 3 digits: – Y: year – WW: week code • product life cycle status code: – X: means not qualified product – nothing means released product PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 8. Block diagram CLESS INTERFACE UNIT HOST INTERFACE CLESS UART RF DETECT SENSOR RX CODEC DEMOD ADC TX CODEC DRIVER TxCtrl PLL BG SIGNAL PROCESSING I2C-BUS ARM CORTEX M0 DATA MEMORY SRAM VMID EEPROM MEMORY CONTROL AHB to APB POWER MANAGEMENT UNIT BATTERY MONITOR 3V TX-LDO 1.8 V DSLDO MISCELLANEOUS CLOCK MGT UNIT TIMERS OSC 380 kHz OSC 20 MHz CRC COPROCESSOR FRACN PLL QUARTZ OSCILLATOR CODE MEMORY ROM EEPROM RANDOM NUMBER GENERATOR aaa-015869 Fig 3. PN7120 block diagram PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 9. Pinning information 9.1 Pinning G F E D C B A ball A1 index area Fig 4. Product data sheet COMPANY PUBLIC 2 3 4 5 6 7 aaa-007528 PN7120 pinning (bottom view) Table 4. PN7120 1 PN7120 pin description Symbol Pin Type[1] Refer Description i.c. A1 - - internally connected; must be connected to ground CLK_REQ A2 O VDD(PAD) clock request pin XTAL1 A3 I VDD PLL clock input. Oscillator input i.c. A4 - - internally connected; leave open i.c. A5 - - internally connected; leave open i.c. A6 - - internally connected; leave open i.c. A7 - - internally connected; leave open I2CSCL B1 I VDD(PAD) I2C-bus serial clock input I2CADR0 B2 I VDD(PAD) I2C-bus address bit 0 input i.c. B3 - - internally connected; leave open i.c. B4 - - internally connected; leave open i.c. B5 - - internally connected; must be connected to ground VSS1 B6 G n/a ground i.c. B7 - - internally connected; leave open I2CSDA C1 I/O VDD(PAD) I2C-bus serial data VSS(PAD) C2 G n/a pad ground XTAL2 C3 O VDD oscillator output VSS C4 G n/a ground n.c. C5 - - not connected VDD C6 P n/a LDO output supply voltage VBAT C7 P n/a battery supply voltage IRQ D1 O VDD(PAD) interrupt request output All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 7 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 4. PN7120 pin description …continued Symbol Pin Type[1] Refer Description BOOST_CTRL D2 O VDD(PAD) booster control, see Ref. 5 VDD(PAD) D3 P n/a pad supply voltage VSS2 D4 G n/a ground i.c. D5 - - internally connected; leave open VSS3 D6 G n/a ground i.c. D7 - - internally connected; leave open VEN E1 I VBAT reset pin. Set the device in Hard Power Down VSS(DC_DC) E2 G n/a ground n.c. E3 - - not connected n.c. E4 - - not connected n.c. E5 - - not connected n.c. E6 - - not connected VDD(TX) E7 P n/a contactless transmitter output supply voltage for decoupling i.c. F1 - - internally connected; leave open i.c. F2 - - internally connected; leave open VSS4 F3 G n/a ground i.c. F4 - - internally connected; leave open RXN F5 I VDD negative receiver input RXP F6 I VDD positive receiver input VDD(MID) F7 P n/a receiver reference input supply voltage VBAT2 G1 P n/a battery supply voltage; must be connected to VBAT VBAT1 G2 P n/a battery supply voltage; must be connected to VBAT TX1 G3 O VDD(TX) antenna driver output VSS(TX) G4 G n/a contactless transmitter ground TX2 G5 O VDD(TX) antenna driver output ANT2 G6 P n/a antenna connection for Listen mode ANT1 G7 P n/a antenna connection for Listen mode [1] P = power supply; G = ground; I = input, O = output; I/O = input/output. 10. Functional description PN7120 can be connected on a host controller through I2C-bus. The logical interface towards the host baseband is NCI-compliant Ref. 1 with additional command set for NXP-specific product features. This IC is fully user controllable by the firmware interface described in Ref. 4. Moreover, PN7120 provides flexible and integrated power management unit in order to preserve energy supporting Power Off mode. In the following chapters you will find also more details about PN7120 with references to very useful application note such as: PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 8 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware • PN7120 User Manual (Ref. 4): User Manual describes the software interfaces (API) based on the NFC forum NCI standard. It does give full description of all the NXP NCI extensions coming in addition to NCI standard (Ref. 1). • PN7120 Hardware Design Guide (Ref. 5): Hardware Design Guide provides an overview on the different hardware design options offered by the IC and provides guidelines on how to select the most appropriate ones for a given implementation. In particular, this document highlights the different chip power states and how to operate them in order to minimize the average NFC-related power consumption so to enhance the battery lifetime. • PN7120 Antenna and Tuning Design Guide (Ref. 6): Antenna and Tuning Design Guide provides some guidelines regarding the way to design an NFC antenna for the PN7120 chip. It also explains how to determine the tuning/matching network to place between this antenna and the PN7120. Standalone antenna performances evaluation and final RF system validation (PN7120 + tuning/matching network + NFC antenna within its final environment) are also covered by this document. • PN7120 Low-Power Mode Configuration (Ref. 9): Low-Power Mode Configuration documentation provides guidance on how PN7120 can be configured in order to reduce current consumption by using Low-power polling mode. BATTERY/PMU HOST CONTROLLER host interface control NFCC ANTENNA MATCHING aaa-016739 Fig 5. PN7120 connection 10.1 System modes 10.1.1 System power modes PN7120 is designed in order to enable the different power modes from the system. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 9 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 2 power modes are specified: Full power mode and Power Off mode. Table 5. System power modes description System power mode Description Full power mode the main supply (VBAT) as well as the host interface supply (VDD(PAD)) is available, all use cases can be executed Power Off mode the system is kept Hard Power Down (HPD) Full power mode [VBAT = On && VDD(PAD) = On VEN = On] [VBAT = Off || VEN = Off] Power Off mode [VEN = Off] Fig 6. aaa-015871 System power mode diagram Table 6 summarizes the system power mode of the PN7120 depending on the status of the external supplies available in the system: Table 6. System power modes configuration VBAT VEN Power mode Off X Power Off mode On Off Power Off mode On On Full power mode Depending on power modes, some application states are limited: Table 7. System power modes description System power mode Allowed communication modes Power Off mode no communication mode available Full power mode Reader/Writer, Card Emulation, P2P modes 10.1.2 PN7120 power states Next to system power modes defined by the status of the power supplies, the power states include the logical status of the system thus extend the power modes. 4 power states are specified: Monitor, Hard Power Down (HPD), Standby, Active. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 10 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 8. PN7120 power states Power state name Description Monitor The PN7120 is supplied by VBAT which voltage is below its programmable critical level, VEN voltage > 1.1 V and the Monitor state is enabled. The system power mode is Power Off mode. Hard Power Down The PN7120 is supplied by VBAT which voltage is above its programmable critical level when Monitor state is enabled and PN7120 is kept in Hard Power Down (VEN voltage is kept low by host or SW programming) to have the minimum power consumption. The system power mode is in Power Off. Standby The PN7120 is supplied by VBAT which voltage is above its programmable critical level when the Monitor state is enabled, VEN voltage is high (by host or SW programming) and minimum part of PN7120 is kept supplied to enable configured wake-up sources which allow to switch to Active state; RF field, Host interface. The system power mode is Full power mode. Active The PN7120 is supplied by VBAT which voltage is above its programmable critical level when Monitor state is enabled, VEN voltage is high (by host or SW programming) and the PN7120 internal blocks are supplied. 3 functional modes are defined: Idle, Listener and Poller. The system power mode is Full power mode. At application level, the PN7120 will continuously switch between different states to optimize the current consumption (polling loop mode). Refer to Table 1 for targeted current consumption in here described states. The PN7120 is designed to allow the host controller to have full control over its functional states, thus of the power consumption of the PN7120 based NFC solution and possibility to restrict parts of the PN7120 functionality. 10.1.2.1 Monitor state In Monitor state, the PN7120 will exit it only if the battery voltage recovers over the critical level. Battery voltage monitor thresholds show hysteresis behavior as defined in Table 26. PN7120 will autonomously shut-down internal PMU supply to protect the battery from deep discharge. 10.1.2.2 Hard Power Down (HPD) state The Hard Power Down state is entered when VDD(PAD) and VBAT are high by setting VEN voltage < 0.4 V. As these signals are under host control, the PN7120 has no influence on entering or exiting this state. 10.1.2.3 Standby state Active state is PN7120’s default state after boot sequence in order to allow a quick configuration of PN7120. It is recommended to change the default state to Standby state after first boot in order to save power. PN7120 can switch to Standby state autonomously (if configured by host). In this state PN7120 most blocks including CPU are no more supplied. Number of wake-up sources exist to put PN7120 into Active state: • I2C-bus interface wake-up event • Antenna RF level detector PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 11 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware • Internal timer event when using polling loop (380 kHz Low-power oscillator is enabled) If wake-up event occurs, PN7120 will switch to Active state. Any further operation depends on software configuration and/or wake-up source. 10.1.2.4 Active state Within the Active state, the system is acting as an NFC device. The device can be in 3 different functional modes: Idle, Poller and Target. Table 9. Functional modes in active state Functional modes Description Idle the PN7120 is active and host interface communication is on going. The RF interface is not activated. If Standby state is de-activated PN547/C2 stays in Idle mode even when no host communication. Listener the PN7120 is active and is listening to external device. The RF interface is activated. Poller the PN7120 is active and is in Poller mode. It polls external device. The RF interface is activated. Poller mode: In this mode, PN547/C2 is acting as Reader/Writer or NFC Initiator, searching for or communicating with passive tags or NFC target. Once RF communication has ended, PN547/C2 will switch to Idle mode or Standby state to save energy. Poller mode shall be used with 2.7 V < VBAT < 5.5 V and VEN voltage > 1.1 V. Poller mode shall not be used with VBAT < 2.7 V. PVDD is within its operational range (see Table 1). Listener mode: In this mode, PN547/C2 is acting as a card or as an NFC Target. Listener mode shall be used with 2.3 V < VBAT < 5.5 V and VEN voltage > 1.1 V. Once RF communication has ended, PN547/C2 will switch to Idle mode or Standby state to save energy. 10.1.2.5 Polling loop The polling loop will sequentially set PN7120 in different power states (Active or Standby). All RF technologies supported by PN7120 can be independently enabled within this polling loop. There are 2 main phases in the polling loop: • Listening phase. The PN7120 can be in Standby power state or Listener mode • Polling phase. The PN7120 is in Poller mode PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 12 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Listening phase Emulation Pause Type A Type B Type F @424 ISO15693 Type F @212 Polling phase aaa-016741 Fig 7. Polling loop: all phases enabled Listening phase uses Standby power state (when no RF field) and PN7120 goes to Listener mode when RF field is detected. When in Polling phase, PN7120 goes to Poller mode. To further decrease the power consumption when running the polling loop, PN7120 features a low-power RF polling. When PN7120 is in Polling phase instead of sending regularly RF command PN7120 senses with a short RF field duration if there is any NFC Target or card/tag present. If yes, then it goes back to standard polling loop. With 500 ms (configurable duration, see Ref. 4) listening phase duration, the average power consumption is around 150 A. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 13 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Listening phase Emulation Pause Polling phase aaa-016743 Fig 8. Polling loop: low-power RF polling Detailed description of polling loop configuration options is given in Ref. 4. 10.2 Microcontroller PN7120 is controlled via an embedded ARM Cortex-M0 microcontroller core. PN7120 features integrated in firmware are referenced in Ref. 4 10.3 Host interfaces PN7120 provides the support of an I2C-bus Slave Interface, up to 3.4 MBaud. The host interface is waken-up on I2C-bus address. To enable and ensure data flow control between PN7120 and host controller, additionally a dedicated interrupt line IRQ is provided which Active state is programmable. See Ref. 4 for more information. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 14 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 10.3.1 I2C-bus interface The I2C-bus interface implements a slave I2C-bus interface with integrated shift register, shift timing generation and slave address recognition. I2C-bus Standard mode (100 kHz SCL), Fast mode (400 kHz SCL) and High-speed mode (3.4 MHz SCL) are supported. The mains hardware characteristics of the I2C-bus module are: • • • • Support slave I2C-bus Standard, Fast and High-speed modes supported Wake-up of PN7120 on its address only Serial clock synchronization can be used by PN7120 as a handshake mechanism to suspend and resume serial transfer (clock stretching) The I2C-bus interface module meets the I2C-bus specification Ref. 3 except General call, 10-bit addressing and Fast mode Plus (Fm+). 10.3.1.1 I2C-bus configuration The I2C-bus interface shares four pins with I2C-bus interface also supported by PN7120. When I2C-bus is configured in EEPROM settings, functionality of interface pins changes to one described in Table 10. Table 10. Functionality for I2C-bus interface Pin name Functionality I2CADR0 I2C-bus address 0 I2CSDA I2C-bus data line I2CSCL I2C-bus clock line PN7120 supports 7-bit addressing mode. Selection of the I2C-bus address is done by 2-pin configurations on top of a fixed binary header: 0, 1, 0, 1, 0, 0, I2CADR0, R/W. Table 11. I2C-bus interface addressing I2CADR0 I2C-bus address (R/W = 0, write) I2C-bus address (R/W = 1, read) 0 0x50 0x51 1 0x52 0x53 10.4 PN7120 clock concept There are 4 different clock sources in PN7120: • 27.12 MHz clock coming either/or from: – Internal oscillator for 27.12 MHz crystal connection – Integrated PLL unit which includes a 1 GHz VCO • 13.56 MHz RF clock recovered from RF field • Low-power oscillator 20 MHz • Low-power oscillator 380 kHz PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 15 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 10.4.1 27.12 MHz quartz oscillator When enabled, the 27.12 MHz quartz oscillator applied to PN7120 is the time reference for the RF front end when PN7120 is behaving in Reader mode or NFCIP-1 initiator. Therefore stability of the clock frequency is an important factor for reliable operation. It is recommended to adopt the circuit shown in Figure 9. PN7120 XTAL1 XTAL2 c crystal 27.12 MHz c aaa-015872 Fig 9. 27.12 MHz crystal oscillator connection Table 12 describes the levels of accuracy and stability required on the crystal. Table 12. Crystal requirements Symbol Parameter Conditions Min Typ fxtal crystal frequency ISO/IEC and FCC compliancy - 27.12 - Max Unit fxtal crystal frequency accuracy full operating range [1] 100 - +100 ppm all VBAT range; T = 20 °C [1] 50 - +50 ppm all temperature range; VBAT = 3.6 V [1] 50 - +50 ppm MHz ESR equivalent series resistance - 50 100 CL load capacitance - 10 - pF Po(xtal) crystal output power - - 100 W [1] This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092, then 14 kHz apply. 10.4.2 Integrated PLL to make use of external clock When enabled, the PLL is designed to generate a low noise 27.12 MHz for an input clock 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz. The 27.12 MHz of the PLL is used as the time reference for the RF front end when PN7120 is behaving in Reader mode or NFC Initiator as well as in NFC Target when configured in Active communication mode. The input clock on XTAL1 shall comply with the.following phase noise requirements for the following input frequency: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz: PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 16 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware dBc/Hz -20dBc/Hz Input reference noise floor -140 dBc/Hz Hz Input reference noise corner 50 kHz aaa-007232 Fig 10. Input reference phase noise characteristics This phase noise is equivalent to an RMS jitter of 6.23 ps from 10 Hz to 1 MHz. For configuration of input frequency, refer to Ref. 8. There are 6 pre programmed and validated frequencies for the PLL: 13 MHz, 19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz and 52 MHz. Table 13. PLL input requirements Coupling: single-ended, AC coupling; Symbol Parameter clock frequency fclk fi(ref)acc n reference input frequency accuracy phase noise Conditions Min Typ Max Unit ISO/IEC and FCC compliancy - 13 - MHz - 19.2 - MHz - 24 - MHz - 26 - MHz - 38.4 - MHz - 52 - MHz full operating range; frequencies typical values: 13 MHz, 26 MHz and 52 MHz [1] 25 - +25 ppm full operating range; frequencies typical values: 19.2 MHz, 24 MHz and 38.4 MHz [1] 50 - +50 ppm 140 - - dB/ Hz input noise floor at 50 kHz Sinusoidal shape Vi(p-p) peak-to-peak input voltage 0.2 - 1.8 V Vi(clk) clock input voltage 0 - 1.8 V 0 - 1.8 10 % V Square shape Vi(clk) [1] clock input voltage This requirement is according to FCC regulations requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092, then 400 ppm limits apply. For detailed description of clock request mechanisms, refer to Ref. 4 and Ref. 5. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 17 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 10.4.3 Low-power 20 MHz oscillator Low-power 20 MHz oscillator is used as system clock of the system. 10.4.4 Low-power 380 kHz oscillator A Low Frequency Oscillator (LFO) is implemented to drive a counter (WUC) waking-up PN7120 from Standby state. This allows implementation of low-power reader polling loop at application level. Moreover, this 380 kHz is used as the reference clock for write access to EEPROM memory. 10.5 Power concept 10.5.1 PMU functional description The Power Management Unit of PN7120 generates internal supplies required by PN7120 out of VBAT input supply voltage: • VDD: internal supply voltage • VDD(TX): output supply voltage for the RF transmitter The Figure 11 describes the main blocks available in PMU: VBAT VDD VBAT1 and VBAT2 DSLDO BANDGAP VDD(TX) TXLDO NFCC aaa-016748 Fig 11. PMU functional diagram 10.5.2 DSLDO: Dual Supply LDO The input pin of the DSLDO is VBAT. The Low drop-out regulator provides VDD required in PN7120. 10.5.3 TXLDO This is the LDO which generates the transmitter voltage. The value of VDD(TX) is configured at 3.1 V 0.2 V. VDD(TX) value is given according to the minimum targeted VBAT value for which Reader mode shall work. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 18 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware For VBAT above 3.1 V, VDD(TX) = 3.1 V: V BAT 3.1V V DD TX = 3.1V 3.1V V BAT 2.3V V DD TX = V BAT In Standby state, VDD(TX) is around 2.5 V with some ripples; it toggles between 2.35 V to 2.65 V with a period which depends on the capacitance and load on VDD(TX). Figure 12 shows VDD(TX) behavior for 3.1 V: V VBAT VDD(TX) set to 3.1 V 3.1 V time aaa-015875 Fig 12. VDD(TX) offset disabled behavior Figure 13 shows the case where the PN7120 is in Standby state: V VBAT 2.65 V 2.5 V 2.35 V time aaa-007538 Fig 13. VDD(TX) behavior when PN7120 is in Standby state 10.5.3.1 TXLDO limiter The TXLDO includes a current limiter to avoid too high current within TX1, TX2 when in reader or initiator modes. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 19 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware The current limiter block compares an image of the TXLDO output current to a reference. Once the reference is reached, the output current gets limited which is equivalent to a typical output current of 220 mA whatever VBAT = 2.7 V and 180 mA for VBAT = 3.1 V. 10.5.4 Battery voltage monitor The PN7120 features low-power VBAT voltage monitor which protects the host device battery from being discharged below critical levels. When VBAT voltage goes below VBATcritical threshold, then the PN7120 goes in Monitor state. Refer to Figure 14 for principle schematic of the battery monitor. The battery voltage monitor is enabled via an EEPROM setting. The VBATcritical threshold can be configured to 2.3 V or 2.75 V by an EEPROM setting. At the first start-up, VBAT voltage monitor functionality is OFF and then enabled if properly configured in EEPROM. The PN7120 monitors battery voltage continuously. VBAT enable EEPROM VBAT MONITOR REGISTERS threshold selection POWER MANAGEMENT VDD low-power SYSTEM MANAGEMENT power off POWER SWITCHES VDD(CPU) DIGITAL (memories, cpu, etc,...) aaa-015877 Fig 14. Battery voltage monitor principle The value of the critical level can be configured to 2.3 V or 2.75 V by an EEPROM setting. This value has a typical hysteresis around 150 mV. 10.6 Reset concept 10.6.1 Resetting PN7120 To enter reset there are 2 ways: • Pulling VEN voltage low (Hard Power Down state) • if VBAT monitor is enabled: lowering VBAT below the monitor threshold (Monitor state, if VEN voltage is kept above 1.1 V) PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 20 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Reset means resetting the embedded FW execution and the registers values to their default values. Part of these default values is defined from EEPROM data loaded values, others are hardware defined. See Ref. 4 to know which ones are accessible to tune PN7120 to the application environment. To get out of reset: • Pulling VEN voltage high with VBAT above VBAT monitor threshold if enabled Figure 15 shows reset done via VEN pin. VBAT VDD(PAD) VEN tw(VEN) host communication possible tboot aaa-015878 Fig 15. Resetting PN7120 via VEN pin See Section 15.2.2 for the timings values. 10.6.2 Power-up sequences There are 2 different supplies for PN7120. PN7120 allows these supplies to be set up independently, therefore different power-up sequences have to be considered. 10.6.2.1 VBAT is set up before VDD(PAD) This is at least the case when VBAT pin is directly connected to the battery and when PN7120 VBAT is always supplied as soon the system is supplied. As VEN pin is referred to VBAT pin, VEN voltage shall go high after VBAT has been set. VBAT VDD(PAD) tt(VDD(PAD)-VEN) tboot host communication possible VEN aaa-015879 Fig 16. VBAT is set up before VDD(PAD) PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 21 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware See Section 15.2.3 for the timings values. 10.6.2.2 VDD(PAD) and VBAT are set up in the same time It is at least the case when VBAT pin is connected to a PMU/regulator which also supply VDD(PAD). VBAT tt(VBAT-VEN) VDD(PAD) tboot host communication possible VEN aaa-015881 Fig 17. VDD(PAD) and VBAT are set up in the same time See Section 15.2.3 for the timings values. 10.6.2.3 PN7120 has been enabled before VDD(PAD) is set up or before VDD(PAD) has been cut off This can be the case when VBAT pin is directly connected to the battery and when VDD(PAD) is generated from a PMU. When the battery voltage is too low, then the PMU might no more be able to generate VDD(PAD). When the device gets charged again, then VDD(PAD) is set up again. As the pins to select the interface are biased from VDD(PAD), when VDD(PAD) disappears the pins might not be correctly biased internally and the information might be lost. Therefore it is required to make the IC boot after VDD(PAD) is set up again. VBAT VDD(PAD) tt(VDD(PAD)-VEN) VEN tW(VEN) tboot host communication possible aaa-015884 Fig 18. VDD(PAD) is set up or cut-off after PN7120 has been enabled See Section 15.2.3 for the timings values. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 22 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 10.6.3 Power-down sequence tVBAT(L) VBAT t > 0 ms (nice to have) t > 0 ms VEN VDD(PAD) aaa-015886 Fig 19. PN7120 power-down sequence 10.7 Contactless Interface Unit PN7120 supports various communication modes at different transfer speeds and modulation schemes. The following chapters give more detailed overview of selected communication modes. Remark: all indicated modulation index and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimum performance. 10.7.1 Reader/Writer communication modes Generally 5 Reader/Writer communication modes are supported: • • • • • 10.7.1.1 PCD Reader/Writer for ISO/IEC 14443A/MIFARE PCD Reader/Writer for Jewel/Topaz tags PCD Reader/Writer for FeliCa cards PCD Reader/Writer for ISO/IEC 14443B VCD Reader/Writer for ISO/IEC 15693/ICODE ISO/IEC 14443A/MIFARE and Jewel/Topaz PCD communication mode The ISO/IEC 14443A/MIFARE PCD communication mode is the general reader to card communication scheme according to the ISO/IEC 14443A specification. This modulation scheme is as well used for communications with Jewel/Topaz cards. Figure 20 describes the communication on a physical level, the communication table describes the physical parameters (the numbers take the antenna effect on modulation depth for higher data rates). PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 23 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware PCD to PICC 100 % ASK at 106 kbit/s > 25 % ASK at 212, 424 or 848 kbit/s Modified Miller coded NFCC ISO/IEC 14443A - MIFARE PCD mode PICC (Card) PICC to PCD, subcarrier load modulation Manchester coded at 106 kbit/s BPSK coded at 212, 424 or 848 kbit/s ISO/IEC 14443A - MIFARE aaa-016749 Fig 20. ISO/IEC 14443A/MIFARE Reader/Writer communication mode diagram Table 14. Overview for ISO/IEC 14443A/MIFARE Reader/Writer communication mode Communication direction ISO/IEC 14443A/ ISO/IEC 14443A higher transfer speeds MIFARE/ Jewel/ Topaz Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s Bit length (128/13.56) s (64/13.56) s (32/13.56) s (16/13.56) s 100 % ASK > 25 % ASK > 25 % ASK > 25 % ASK Modified Miller Modified Miller Modified Miller Modified Miller subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 bit coding Manchester BPSK BPSK BPSK PN7120 PICC (data sent by PN7120 to a modulation on card) PN7120 side bit coding PICC PN7120 (data received by PN7120 modulation on from a card) PICC side The contactless coprocessor and the on-chip CPU of PN7120 handle the complete ISO/IEC 14443A/MIFARE RF-protocol, nevertheless a dedicated external host has to handle the application layer communication. 10.7.1.2 FeliCa PCD communication mode The FeliCa communication mode is the general Reader/Writer to card communication scheme according to the FeliCa specification. Figure 21 describes the communication on a physical level, the communication overview describes the physical parameters. PCD to PICC, 8 - 12 % ASK at 212 or 424 kbits/s Manchester coded NFCC ISO/IEC 18092 - FeliCa PCD mode PICC to PCD, load modulation Manchester coded at 212 or 424 kbits/s PICC (Card) FeliCa card aaa-016750 Fig 21. FeliCa Reader/Writer communication mode diagram PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 24 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 15. Overview for FeliCa Reader/Writer communication mode Communication direction FeliCa FeliCa higher transfer speeds Transfer speed 212 kbit/s 424 kbit/s Bit length (64/13.56) s (32/13.56) s modulation on PN7120 side 8 % 12 % ASK 8 % 12 % ASK bit coding Manchester Manchester modulation on PICC side load modulation load modulation subcarrier frequency no subcarrier no subcarrier bit coding Manchester Manchester PN7120 PICC (data sent by PN7120 to a card) PICC PN7120 (data received by PN7120 from a card) The contactless coprocessor of PN7120 and the on-chip CPU handle the FeliCa protocol. Nevertheless a dedicated external host has to handle the application layer communication. 10.7.1.3 ISO/IEC 14443B PCD communication mode The ISO/IEC 14443B PCD communication mode is the general reader to card communication scheme according to the ISO/IEC 14443B specification.Figure 22 describes the communication on a physical level, the communication table describes the physical parameters. PCD to PICC, 8 - 14 % ASK at 106, 212, 424 or 848 kbit/s NRZ coded NFCC ISO/IEC 14443 Type B PCD mode PICC to PCD, subcarrier load modulation BPSK coded at 106, 212, 424 or 848 kbit/s PICC (Card) ISO/IEC 14443 Type B aaa-016751 Fig 22. ISO/IEC 14443B Reader/Writer communication mode diagram Table 16. Overview for ISO/IEC 14443B Reader/Writer communication mode Communication direction ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s Bit length (128/13.56) s (64/13.56) s (32/13.56) s (16/13.56) s 8 % 14 % ASK 8 % 14 % ASK 8 % 14 % ASK 8 % 14 % ASK NRZ NRZ PN7120 PICC (data sent by PN7120 to a modulation on card) PN7120 side bit coding NRZ NRZ PICC PN7120 PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 25 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 16. Overview for ISO/IEC 14443B Reader/Writer communication mode …continued Communication direction ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s Bit length (128/13.56) s (64/13.56) s (32/13.56) s (16/13.56) s subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 bit coding BPSK BPSK BPSK BPSK (data received by PN7120 modulation on from a card) PICC side The contactless coprocessor and the on-chip CPU of PN7120 handles the complete ISO/IEC 14443B RF-protocol, nevertheless a dedicated external host has to handle the application layer communication. 10.7.1.4 ISO/IEC 15693 VCD communication mode The ISO/IEC 15693 VCD Reader/Writer communication mode is the general reader to card communication scheme according to the ISO/IEC 15693 specification. PN7120 will communicate with VICC using only the higher data rates of the VICC (26.48 kbit/s with single subcarrier and 26.69 kbit/s with dual subcarrier). PN7120 supports the commands as defined by the ETSI HCI (see Ref. 1) and on top offers the inventory of the tags (anticollision sequence) on its own. NFCC ISO/IEC 15693 VCD mode VCD to VICC, 10 - 30 % or 100 % ASK at 1.65 or 26.48 kbit/s pulse position coded VICC to VCD, subcarrier load modulation Manchester coded at 26.48 or 26.69 kbit/s Card (VICC/TAG) ISO/IEC 15693 aaa-016752 Fig 23. ISO/IEC 15693 VCD communication mode diagram Figure 23 shows the communication schemes used. 2 communication schemes can be used from card to PN7120 and 2 communication schemes can be used from PN7120 to card. Thus, 4 communication schemes are possible. Table 17. Overview for ISO/IEC 15693 VCD communication mode Communication direction PN7120 VICC (data sent by PN7120 to a tag) PN7120 Product data sheet COMPANY PUBLIC transfer speed 1.65 kbit/s 26.48 kbit/s bit length (8192/13.56) s (512/13.56) s modulation on PN7120 side 10 % 30 % or 100 % ASK 10 % 30 % or 100 % ASK bit coding pulse position modulation 1 out of 256 mode pulse position modulation 1 out of 4 mode All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 26 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 17. Overview for ISO/IEC 15693 VCD communication mode …continued Communication direction VICC PN7120 (data received by PN7120 from a tag) transfer speed 26.48 kbit/s 26.69 kbit/s bit length (512/13.56) s (508/13.56) s modulation on VICC subcarrier load modulation side subcarrier load modulation subcarrier frequency single subcarrier dual subcarrier bit coding Manchester Manchester 10.7.2 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes An NFCIP-1 communication takes place between 2 devices: • NFC Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication. • NFC Target: responds to NFC Initiator command either in a load modulation scheme in Passive communication mode or using a self-generated and self-modulated RF field for Active communication mode. The NFCIP-1 communication differentiates between Active and Passive communication modes. • Active communication mode means both the NFC Initiator and the NFC Target are using their own RF field to transmit data • Passive communication mode means that the NFC Target answers to an NFC Initiator command in a load modulation scheme. The NFC Initiator is active in terms of generating the RF field. PN7120 supports the Active Target, Active Initiator, Passive Target and Passive Initiator communication modes at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard. BATTERY BATTERY NFCC NFCC HOST HOST NFC Initiator: Passive or Active Communication modes NFC Target: Passive or Active Communication modes aaa-016755 Fig 24. NFCIP-1 communication mode Nevertheless a dedicated external host has to handle the application layer communication. 10.7.2.1 ACTIVE communication mode Active communication mode means both the NFC Initiator and the NFC Target are using their own RF field to transmit data. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 27 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware host 1. NFC Initiator starts the communication at selected transfer speed NFC Target power to generate the field host host NFCC NFC Initiator power for digital processing host NFCC NFC Initiator NFC Target 2. NFC Target answers at the same transfer speed power for digital processing power to generate the field aaa-016756 Fig 25. Active communication mode The following table gives an overview of the Active communication modes: Table 18. Overview for Active communication mode Communication direction ISO/IEC 18092, Ecma 340, NFCIP-1 Baud rate 106 kbit/s 212 kbit/s 424 kbit/s Bit length (128/13.56) s (64/13.56) s (32/13.56) s modulation 100 % ASK 8 % 30 % ASK[1] 8 % 30 % ASK[1] bit coding Modified Miller Manchester Manchester modulation 100 % ASK 8 % 30 % ASK[1] 8 % 30 % ASK[1] bit coding Miller Manchester Manchester NFC Initiator to NFC Target NFC Target to NFC Initiator [1] This modulation index range is according to NFCIP-1 standard. It might be that some NFC forum type 3 cards does not withstand the full range as based on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see Ref. 6. 10.7.2.2 Passive communication mode Passive communication mode means that the NFC Target answers to an NFC Initiator command in a load modulation scheme. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 28 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware host 1. NFC Initiator starts the communication at selected transfer speed NFC Target power to generate the field host host NFCC NFC Initiator power for digital processing host NFCC NFC Initiator 2. NFC Target answers using load modulation at the same transfer speed NFC Target power to generate the field power for digital processing aaa-016757 Fig 26. Passive communication mode Table 19 gives an overview of the Passive communication modes: Table 19. Overview for Passive communication mode Communication direction ISO/IEC 18092, Ecma 340, NFCIP-1 Baud rate 106 kbit/s 212 kbit/s 424 kbit/s Bit length (128/13.56) s (64/13.56) s (32/13.56) s modulation 100 % ASK 8 % 30 % ASK[1] 8 % 30 % ASK[1] bit coding Modified Miller Manchester Manchester modulation subcarrier load modulation load modulation load modulation subcarrier frequency 13.56 MHz/16 no subcarrier no subcarrier bit coding Manchester Manchester Manchester NFC Initiator to NFC Target NFC Target to NFC Initiator [1] This modulation index range is according to NFCIP-1 standard. It might be that some NFC forum type 3 cards does not withstand the full range as based on FeliCa range which is narrow (8 % to 14 % ASK). To adjust the index, see Ref. 6. 10.7.2.3 NFCIP-1 framing and coding The NFCIP-1 framing and coding in Active and Passive communication modes are defined in the NFCIP-1 standard: ISO/IEC 18092 or Ecma 340. 10.7.2.4 NFCIP-1 protocol support The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol, refer to the ISO/IEC 18092 or Ecma 340 NFCIP-1 standard. However the datalink layer is according to the following policy: PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 29 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware • Transaction includes initialization, anticollision methods and data transfer. This sequence must not be interrupted by another transaction • PSL shall be used to change the speed between the target selection and the data transfer, but the speed should not be changed during a data transfer 10.7.3 Card communication modes PN7120 can be addressed as a ISO/IEC 14443A or ISO/IEC 14443B cards. This means that PN7120 can generate an answer in a load modulation scheme according to the ISO/IEC 14443A or ISO/IEC 14443B interface description. Remark: PN7120 does not support a complete card protocol. This has to be handled by the host controller. Table 20 and Table 21 describe the physical parameters. 10.7.3.1 Table 20. ISO/IEC 14443A/MIFARE card communication mode Overview for ISO/IEC 14443A/MIFARE card communication mode Communication direction ISO/IEC 14443A ISO/IEC 14443A higher transfer speeds Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s Bit length (128/13.56) s (64/13.56) s (32/13.56) s > 25 % ASK > 25 % ASK Modified Miller Modified Miller Modified Miller subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 bit coding Manchester BPSK BPSK PCD PN7120 (data received by PN7120 modulation on PCD 100 % ASK from a card) side bit coding PN7120 PCD (data sent by PN7120 to a modulation on card) PN7120 side 10.7.3.2 Table 21. ISO/IEC 14443B card communication mode Overview for ISO/IEC 14443B card communication mode Communication direction ISO/IEC 14443B ISO/IEC 14443B higher transfer speeds Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s Bit length (128/13.56) s (64/13.56) s (32/13.56) s 8 % 14 % ASK 8 % 14 % ASK NRZ NRZ NRZ subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 bit coding BPSK BPSK BPSK PCD PN7120 (data received by PN7120 modulation on PCD 8 % 14 % ASK from a Reader) side bit coding PN7120 PCD (data sent by PN7120 to a modulation on Reader) PN7120 side PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 30 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 10.7.4 Frequency interoperability When in communication, PN7120 is generating some RF frequencies. PN7120 is also sensitive to some RF signals as it is looking from data in the field. In order to avoid interference with others RF communication, it is required to tune the antenna and design the board according to Ref. 5. Although ISO/IEC 14443 and ISO/IEC 18092/Ecma 340 allows an RF frequency of 13.56 MHz 7 kHz, FCC regulation does not allow this wide spread and limits the dispersion to 50 ppm, which is in line with PN7120 capability. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 31 of 55 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PN7120 CLOCK INTERFACE ANTENNA MATCHING/TUNING CIRCUIT ANTENNA Cant1 Y2 3 I2CSDA host controller external interrupt input (optional) IRQ host controller GPIO (output) - reset control VEN i.c. n.c. CLK_REQ i.c. n.c. VDD(PAD) VBAT POWER INTERFACE VDD controller IO power supply (1.8 V or 3.3 V) E6 C5 A7 i.c. i.c. B7 i.c. n.c. n.c. n.c. n.c. i.c. i.c. F4 E7 B2 F6 D2 G3 B1 G5 C1 F5 D1 PN7120 Ctvdd 1 μF A6 G7 G6 E1 F7 A1 D7 A2 F1 B3 F2 D3 G2 C7 G1 VDD(TX) n.c. Rrxp1 1 kΩ Lemc1 Cs1 560 nH xxx(1) pF/50 V Rq1 Cemc1 180 pF/16 V ANT1 Cemc2 180 pF/16 V RXP TX1 0Ω Cp1 xxx(1) pF/50 V Cp2 xxx(1) pF/50 V Lemc2 Cs2 Rq2 560 nH xxx(1) pF/50 V 0Ω Rrxn1 1 kΩ TX2 RXN Crxn ANT2 1 nF/16 V Rrxn2 Cant2 n.c. xxx(1) pF/50 V VDD(MID) i.c. i.c. i.c. VBAT1 VBAT2 VBAT C6 Cvdd 1 μF VSS1 VSS(PAD) battery power (2.75 V up to 5.5 V) Cpvdd 1 μF E4 C3 C2 B6 Cvbat 4.7 μF E3 Crxp 1 nF/16 V C4 D4 D6 F3 E2 G4 Cvbat2 100 nF Cvmid 100 nF main ground (GND) aaa-015905 (1) xxx: customer antenna matching tuning. Fig 27. Application schematic PN7120 © NXP Semiconductors N.V. 2015. All rights reserved. 32 of 55 Full NFC Forum-compliant controller with integrated firmware Rev. 3.1 — 8 October 2015 312431 All information provided in this document is subject to legal disclaimers. host controller I2C-bus data D5 VSS(TX) I2CSCL E5 VSS(DC_DC) BOOST_CTRL A5 VSS4 n.c. host controller I2C-bus clock A4 VSS3 XTAL2 I2CADR0 B4 VSS2 HOST INTERFACE host controller I2C-bus B5 A3 VSS XTAL1 n.c. Rrxp2 CXTAL 2 10 pF i.c. 27.12 MHz xxx(1) pF/50 V CXTAL 1 10 pF 1 i.c. 2 i.c. 4 i.c. Product data sheet COMPANY PUBLIC 11. Application design-in information PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 12. Limiting values Table 22. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD(PAD) VDD(PAD) supply voltage VBAT battery supply voltage VESD electrostatic discharge voltage Conditions Min Max Unit supply voltage for host interface - 4.2 V - 6 V HBM; 1500 , 100 pF; EIA/JESD22-A114-D - 1.5 kV CDM; field induced model; EIA/JESC22-C101-C - 500 V 55 +150 C - 0.55 W storage temperature Tstg [1] Ptot total power dissipation VRXN(i) RXN input voltage 0 2.5 V VRXP(i) RXP input voltage 0 2.5 V [1] all modes The design of the solution shall be done so that for the different use cases targeted the power to be dissipated from the field or generated by PN7120 does not exceed this value. 13. Recommended operating conditions Table 23. Parameter Conditions Tamb ambient temperature JEDEC PCB-0.5 VBAT PN7120 Product data sheet COMPANY PUBLIC Operating conditions Symbol battery supply voltage VDD supply voltage VDD(PAD) VDD(PAD) supply voltage Ptot total power dissipation IO(VDDTX) output current on pin VDD(TX) Min Typ Max Unit 30 +25 +85 C battery monitor enabled; VSS = 0 V [1] 2.3 - 5.5 V Card Emulation and Passive Target; VSS = 0 V [1] 2.3 - 5.5 V Reader, Active Initiator and Active Target; VSS = 0 V [1] 2.7 - 5.5 V 1.65 1.8 1.95 V [2] [2] supply voltage for host interface 1.8 V host supply; VSS = 0 V [1] 1.65 1.8 1.95 V 3 V host supply; VSS = 0 V [1] 3.0 - 3.6 V - - 0.5 W - - 100 mA Reader; IVDD(TX) = 100 mA; VBAT = 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 [2] © NXP Semiconductors N.V. 2015. All rights reserved. 33 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 23. Operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit IBAT battery supply current in Hard Power Down state; VBAT = 3.6 V; T = 25 °C - 10 12 A in Standby state; VBAT = 3.6 V; T = 25 °C - - 20 A in Monitor state; VBAT = 2.75 V; T = 25 °C - - 12 A in low-power polling loop; VBAT = 3.6 V; T = 25 °C; loop time = 500 ms - 150 - A IVBAT(tot) total supply current on VBAT PCD mode at typical 3 V [3] - - 170 mA Ith(Ilim) current limit threshold current current limiter on VDD(TX) pin; VDD(TX) = 3.1 V [3] - 180 - mA [4] [1] VSS represents VSS, VSS1, VSS2, VSS3, VSS4, VSS(PAD) and VSS(TX). [2] The antenna should be tuned not to exceed this current limit (the detuning effect when coupling with another device must be taken into account). [3] The antenna shall be tuned not to exceed the maximum of IVBAT. [4] This is the threshold of a built-in protection done to limit the current out of VDD(TX) in case of any issue at antenna pins to avoid burning the device. It is not allowed in operational mode to have IVDD(TX) such that IVBAT maximum value is exceeded. 14. Thermal characteristics Table 24. Thermal characteristics Symbol Parameter Rth(j-a) PN7120 Product data sheet COMPANY PUBLIC Conditions thermal resistance from in free air with exposed pad junction to ambient soldered on a 4 layer JEDEC PCB All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 Min Typ Max Unit - - 74 K/W © NXP Semiconductors N.V. 2015. All rights reserved. 34 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 15. Characteristics 15.1 Current consumption characteristics Table 25. Current consumption characteristics for operating ambient temperature range Symbol Parameter Conditions Min Typ Max Unit IBAT battery supply current in Hard Power Down state; VBAT = 3.6 V; VEN voltage = 0 V - 10 18 A IO(VDDTX) IO(VDDPAD) [1] in Standby state; VBAT = 3.6 V; including emulation phase of polling loop [1] - 20 35 A in Idle and Target Active power states; VBAT = 3.6 V [2] - 6 - mA in Initiator Active power state; VBAT = 3.6 V [2] - 13 - mA in Monitor state; VBAT = 2.75 V [3] - 10 18 A [4] - 30 100 mA - - 15 mA output current on pin VDD(TX) output current on pin VDD(PAD) [5] total current which can be pulled on VDD(PAD) referenced outputs Refer to Section 10.1.2.4 for the description of the power modes. [2] Refer to Section 10.1.2.5 for the description of the polling loop. [3] This is the same value for VBAT = 2.3 V when the monitor threshold is set to 2.3 V. [4] IVDD(TX) depends on VDD(TX) and on the external circuitry connected to TX1 and TX2. [5] During operation with a typical circuitry as recommended by NXP in Ref. 6, the overall current is below 100 mA even when loaded by target/card/tag. 15.2 Functional block electrical characteristics 15.2.1 Battery voltage monitor characteristics Table 26. Battery voltage monitor characteristics Symbol Parameter Vth Vhys threshold voltage Conditions Min Typ Max Unit set to 2.3 V 2.2 2.3 2.4 V set to 2.75 V 2.65 2.75 2.85 V 100 150 200 mV hysteresis voltage 15.2.2 Reset via VEN Table 27. PN7120 Product data sheet COMPANY PUBLIC Reset timing Symbol Parameter Conditions Min Typ Max Unit tW(VEN) VEN pulse width to reset 3 - - s tboot boot time - - 2.5 ms All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 35 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 15.2.3 Power-up timings Table 28. Power-up timings Symbol Parameter Conditions Min Typ Max Unit tt(VBAT-VEN) transition time from pin VBAT VBAT, VEN to pin VEN voltage = HIGH 0 - - ms tt(VDDPAD-VEN) transition time from pin VDD(PAD) to pin VEN VDD(PAD), VEN voltage = HIGH 0 - - ms tt(VBAT-VDDPAD) transition time from pin VBAT VBAT, to pin VDD(PAD) VDD(PAD) = HIGH 0 - - ms Min Typ Max Unit 20 - - ms Min Typ Max Unit 120 125 130 C 15.2.4 Power-down timings Table 29. Power-down timings Symbol Parameter tVBAT(L) time VBAT LOW Conditions 15.2.5 Thermal protection Table 30. Thermal threshold Symbol Parameter Tth(act)otp overtemperature protection activation threshold temperature Conditions 15.2.6 I2C-bus timings Here below are timings and frequency specifications. tf(HIF3) tr(HIF3) tHD;DAT HIF3 (SDA) tSU;STA tHD;STA tHIGH tSU;DAT tLOW HIF4 (SCL) aaa-014046 Fig 28. I2C-bus timings PN7120 Product data sheet COMPANY PUBLIC Table 31. High-speed mode I2C-bus timings specification Symbol Parameter Conditions Min Max Unit fclk(I2CSCL) clock frequency on pin I2CSCL I2C-bus SCL; Cb < 100 pF 0 3.4 MHz tSU;STA set-up time for a repeated START condition Cb < 100 pF 160 - ns tHD;STA hold time (repeated) START condition Cb < 100 pF 160 - ns All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 36 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 31. High-speed mode I2C-bus timings specification …continued Symbol Parameter Conditions Min Max Unit tLOW LOW period of the SCL clock Cb < 100 pF 160 - ns tHIGH HIGH period of the SCL clock Cb < 100 pF 60 - ns tSU;DAT data set-up time Cb < 100 pF 10 - ns tHD;DAT data hold time Cb < 100 pF 0 - ns tr(I2CSDA) rise time on pin I2CSDA I2C-bus SDA; Cb < 100 pF 10 80 ns tf(I2CSDA) fall time on pin I2CSDA I2C-bus SDA; Cb < 100 pF 10 80 ns Vhys hysteresis voltage Schmitt trigger inputs; Cb < 100 pF 0.1VDD(PAD) - V Table 32. Fast mode I2C-bus timings specification Symbol Parameter Conditions Min Max Unit I2C-bus SCL; Cb < 400 pF 0 400 kHz fclk(I2CSCL clock frequency on pin I2CSCL ) tSU;STA set-up time for a repeated START condition Cb < 400 pF 600 - ns tHD;STA hold time (repeated) START condition Cb < 400 pF 600 - ns tLOW LOW period of the SCL clock Cb < 400 pF 1.3 - s tHIGH HIGH period of the SCL clock Cb < 400 pF 600 - ns tSU;DAT data set-up time Cb < 400 pF 100 - ns tHD;DAT data hold time Cb < 400 pF 0 900 ns Vhys hysteresis voltage Schmitt trigger inputs; Cb < 400 pF 0.1VDD(PAD) - V 15.3 Pin characteristics 15.3.1 XTAL1 and XTAL2 pins characteristics Table 33. PN7120 Product data sheet COMPANY PUBLIC Input clock characteristics on XTAL1 when using PLL Symbol Parameter Min Typ Max Unit Vi(p-p) peak-to-peak input voltage Conditions 0.2 - 1.8 V duty cycle 35 - 65 % Table 34. Pin characteristics for XTAL1 when PLL input Symbol Parameter Conditions Min Typ Max Unit IIH HIGH-level input current VI = VDD - - 1 A IIL LOW-level input current VI = 0 V 1 - - A Vi input voltage - - VDD V Vi(clk)(p-p) peak-to-peak clock input voltage 200 - - mV Ci input capacitance - 2 - pF all power modes All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 37 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 35. Pin characteristics for 27.12 MHz crystal oscillator Symbol Parameter Conditions Min Typ Max Unit Ci(XTAL1) XTAL1 input capacitance VDD = 1.8 V; VDC = 0.65 V; VAC = 0.9 V(p-p) - 2 - pF Ci(XTAL2) XTAL2 input capacitance - 2 - pF [1] See the Figure 27 for example of appropriate connected components. The layout should ensure minimum distance between the pins and the components. Table 36. PLL accuracy Symbol Parameter fo(acc) output frequency accuracy Conditions Min Typ Max Unit deviation added to XTAL1 frequency on RF frequency generated; worst case whatever input frequency 50 - +50 ppm 15.3.2 VEN input pin characteristics Table 37. VEN input pin characteristics Symbol Parameter VIH Conditions Min Typ Max Unit HIGH-level input voltage 1.1 - VBAT V VIL LOW-level input voltage 0 - 0.4 V IIH HIGH-level input current VEN voltage = VBAT - - 1 A IIL LOW-level input current VEN voltage = 0 V 1 - - A Ci input capacitance - 5 - pF Unit 15.3.3 Pin characteristics for IRQ, CLK_REQ and BOOST_CTRL Table 38. Pin characteristics for IRQ, CLK_REQ and BOOST_CTRL Symbol Parameter Conditions Min Typ Max VOH HIGH-level output voltage IOH < 3 mA VDD(PAD) 0.4 - VDD(PAD) V VOL LOW-level output voltage IOL < 3 mA 0 - 0.4 V CL load capacitance - - 20 pF tf fall time high speed 1 - 3.5 ns slow speed 2 - 10 ns 1 - 3.5 ns 2 - 10 ns 0.4 - 0.75 M tr CL = 12 pF max rise time CL = 12 pF max high speed slow speed Rpd [1] PN7120 Product data sheet COMPANY PUBLIC pull-down resistance [1] Activated in HPD and Monitor states. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 38 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 15.3.4 ANT1 and ANT2 pin characteristics Table 39. Electrical characteristics of ANT1 and ANT2 Symbol Parameter Conditions Zi(ANT1-ANT2) input impedance between ANT1 and low impedance ANT2 Min Typ Max Unit - 10 17 Vth(ANT1) ANT1 threshold voltage I = 10 mA - 3.3 - V Vth(ANT2) ANT2 threshold voltage I = 10 mA - 3.3 - V 15.3.5 Input pin characteristics for RXN and RXP Table 40. Parameter Min Typ Max Unit VRXN(i) RXN input voltage 0 - VDD V VRXP(i) RXP input voltage 0 - VDD V Ci(RXN) RXN input capacitance - 12 - pF Ci(RXP) RXP input capacitance - 12 - pF Zi(RXN-VDDMI input impedance between RXN and VDD(MID) Reader, Card and P2P modes 0 - 15 k Zi(RXP-VDDMID input impedance between RXP and VDD(MID) ) Reader, Card and P2P modes 0 - 15 k Vi(dyn)(RXN) Miller coded 106 kbit/s - 150 200 mV(p-p) 212 to 424 kbit/s - 150 200 mV(p-p) 106 kbit/s - 150 200 mV(p-p) 212 to 424 kbit/s - 150 200 mV(p-p) D) Vi(dyn)(RXP) PN7120 Product data sheet COMPANY PUBLIC Input pin characteristics for RXN and RXP Symbol RXN dynamic input voltage RXP dynamic input voltage Conditions Miller coded Vi(dyn)(RXN) RXN dynamic input voltage Manchester, NRZ or BPSK coded; 106 to 848 kbit/s - 150 200 mV(p-p) Vi(dyn)(RXP) RXP dynamic input voltage Manchester, NRZ or BPSK coded; 106 to 848 kbit/s - 150 200 mV(p-p) Vi(dyn)(RXN) RXN dynamic input voltage All data coding; 106 kbit/s to 848 kbit/s VDD - - V(p-p) Vi(dyn)(RXP) RXP dynamic input voltage All data coding; 106 kbit/s to 848 kbit/s VDD - - V(p-p) Vi(RF) RF input voltage RF input voltage detected; Initiator modes 100 - mV(p-p) All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 39 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 15.3.6 Output pin characteristics for TX1 and TX2 Table 41. Output pin characteristics for TX1 and TX2 Symbol Parameter Conditions Min VOH HIGH-level output voltage VDD(TX) = 3.1 V and IOH = 30 mA; PMOS driver fully on VOL LOW-level output voltage VDD(TX) = 3.1 V and IOL = 30 mA; NMOS driver fully on Table 42. Typ Max Unit VDD(TX) 150 - - mV - - 200 mV Output resistance for TX1 and TX2 Symbol Parameter Conditions Min Typ Max Unit ROL LOW-level output resistance VDD(TX) 100 mV; CWGsN = 01h - - 80 ROL LOW-level output resistance VDD(TX) 100 mV; CWGsN = 0Fh - - 5 ROH HIGH-level output resistance VDD(TX) 100 mV - - 4 15.3.7 Input pin characteristics for I2CADR0 Table 43. Input pin characteristics for I2CADR0 Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage 0.65VDD(PAD) - VDD(PAD) VIL LOW-level input voltage 0 - 0.35VDD(PAD) V IIH HIGH-level input current VI = VDD(PAD); T = 125 °C - - 1 A IIL LOW-level input current VI = 0 V; T = 125 °C 1 - - A Ci input capacitance - 5 - pF V 15.3.8 Pin characteristics for I2CSDA and I2CSCL Table 44. Pin characteristics for I2CSDA and I2CSCL Below values are given for VDD(PAD) in the range of 1.8 V; unless specified. Symbol Parameter PN7120 Product data sheet COMPANY PUBLIC Min Typ Max Unit VOL LOW-level output IOL < 3 mA voltage Conditions 0 - 0.4 V CL load capacitance - - 10 pF All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 40 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 44. Pin characteristics for I2CSDA and I2CSCL …continued Below values are given for VDD(PAD) in the range of 1.8 V; unless specified. Symbol Parameter Conditions Min Typ Max Unit tf CL = 100 pF; Rpull-up = 1.8 k; Standard and Fast mode 30 - 250 ns CL = 100 pF; VDD(PAD) = 3.3 V; Rpull-up = 3.3 k; Standard and Fast mode 30 - 250 ns CL = 100 pF; Rpull-up = 1 k; High-speed mode 80 - 110 ns CL = 100 pF; Rpull-up = 1.8 k; Standard and Fast mode 30 - 250 ns CL = 100 pF; 30 - 250 ns 10 - 100 ns V tr fall time rise time VDD(PAD) = 3.3 V; Rpull-up = 3.3 k; Standard and Fast mode CL = 100 pF; Rpull-up = 1 k; High-speed mode PN7120 Product data sheet COMPANY PUBLIC VIH HIGH-level input voltage 0.7VDD(PAD) - VDD(PAD) VIL LOW-level input voltage 0 - 0.3VDD(PAD) V IIH HIGH-level input current VI = VDD(PAD); high impedance - - 1 A IIL LOW-level input current VI = 0 V; high impedance 1 - - A Ci input capacitance - 5 - pF All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 41 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 16. Package outline SOT1320-1 VFBGA49: plastic very thin fine-pitch ball grid array package; 49 balls A B D ball A1 index area A A2 E A1 detail X e1 C e C A B C Øv Øw b y y1 C G F e E e2 D C B A ball A1 index area 1 2 3 4 5 6 7 X 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 A2 b max 1.00 0.25 0.75 0.35 nom 0.90 0.20 0.70 0.30 min 0.80 0.15 0.65 0.25 D E e e1 e2 4.1 4.0 3.9 4.4 4.3 4.2 0.5 3.0 3.0 v w y 0.15 0.05 0.08 y1 0.1 sot1320-1_po Outline version References IEC JEDEC JEITA European projection Issue date 11-11-11 11-12-30 SOT1320-1 Fig 29. Package outline, VFBGA49, SOT1320-1, MSL 1 PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 42 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 17.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 43 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 45 and 46 Table 45. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 46. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 44 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 45 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 18. Abbreviations Table 47. PN7120 Product data sheet COMPANY PUBLIC Abbreviations Acronym Description API Application Programming Interface ASK Amplitude Shift keying ASK modulation index The ASK modulation index is defined as the voltage ratio (Vmax - Vmin)/ (Vmax + Vmin) 100 % Automatic device discovery Detect and recognize any NFC peer devices (initiator or target) like: NFC initiator or target, ISO/IEC 14443-3, -4 Type A&B PICC, MIFARE Standard and Ultralight PICC, ISO/IEC 15693 VICC BPSK Bit Phase Shift Keying Card Emulation The IC is capable of handling a PICC emulation on the RF interface including part of the protocol management. The application handling is done by the host controller DEP Data Exchange Protocol DSLDO Dual Supplied LDO FW FirmWare HPD Hard Power Down LDO Low Drop Out LFO Low Frequency Oscillator MOSFET Metal Oxide Semiconductor Field Effect Transistor MSL Moisture Sensitivity Level NCI NFC Controller Interface NFC Near Field Communication NFCC NFC Controller, PN7120 in this data sheet NFC Initiator Initiator as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication NFCIP NFC Interface and Protocol NFC Target Target as defined in ISO/IEC 18092 or ECma 340: NFCIP-1 communication NRZ Non Return to Zero P2P Peer to Peer PCD Proximity Coupling Device. Definition for a Card reader/writer device according to the ISO/IEC 14443 specification or MIFARE PCD -> PICC Communication flow between a PCD and a PICC according to the ISO/IEC 14443 specification or MIFARE PICC Proximity Interface Coupling Card. Definition for a contactless Smart Card according to the ISO/IEC 14443 specification or MIFARE PICC-> PCD Communication flow between a PICC and a PCD according to the ISO/IEC 14443 specification or MIFARE PMOS P-channel MOSFET PMU Power Management Unit PSL Parameter SeLection TXLDO Transmitter LDO UM User Manual All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 46 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Table 47. PN7120 Product data sheet COMPANY PUBLIC Abbreviations …continued Acronym Description VCD Vicinity Coupling Device. Definition for a reader/writer device according to the ISO/IEC 15693 specification VCO Voltage Controlled Oscillator VICC Vicinity Integrated Circuit Card WUC Wake-Up Counter All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 47 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 19. References [1] NFC Controller Interface (NCI) Technical Specification — V1.0 [2] ISO/IEC 14443 — parts 2: 2001 COR 1 2007 (01/11/2007), part 3: 2001 COR 1 2006 (01/09/2006) and part 4: 2nd edition 2008 (15/07/2008) [3] I2C Specification — I2C Specification, UM10204 rev4 (13/02/2012) [4] PN7120 User Manual — UM10819 PN7120 User Manual [5] PN7120 Hardware Design Guide — AN11565 PN7120 Hardware Design Guide [6] PN7120 Antenna and Tuning Design Guide — AN11564 PN7120 Antenna and Tuning Design Guide [7] ISO/IEC 18092 (NFCIP-1) — edition, 15/032013. This is similar to Ecma 340. [8] ISO/IEC15693 — part 2: 2nd edition (15/12/2006), part 3: 1st edition (01/04/2001) [9] PN7120 Low-Power Mode Configuration — AN11562 PN7120 Low-Power Mode Configuration [10] ISO/IEC 21481 (NFCIP-2) — edition, 01/07/2012. This is similar to Ecma 352. [11] NFC Forum Device Requirements — V1.3 [12] ETSI SWP — TS 102 613; UICC - Contactless Front-end (CLF) Interface; Part 1: Physical and data link layer characteristics (Release 9) [13] ETSI HCI — TS 102 622; UICC - Contactless Front-end (CLF) Interface; Host Controller Interface (HCI) (Release 9) [14] ETSI UICC — TS 102 221; UICC - Terminal Interface; Physical and logical characteristics (Release 9) [15] EMVCo — EMV Contactless Specifications for Payment Systems - Book D - EMV Contactless Communication Protocol Specification”, version 2.3.1, December 2013 PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 48 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 20. Revision history Table 48. Revision history Document ID Release date Data sheet status Change notice Supersedes PN7120 v.3.1 20151008 Product data sheet - PN7120 v.3.0 Modifications: PN7120 v.3.0 Modifications: PN7120 v.2 Modifications: PN7120 v.1 PN7120 Product data sheet COMPANY PUBLIC • • Table 4 “PN7120 pin description”: Description of Pin A1 and A5 updated Figure 27 “Application schematic”: updated 20150727 • • • • • Product data sheet PN7120 v.2 Data sheet status changed to “Product data sheet” Section 2 “General description”: first sentence updated Section 3 “Features and benefits”: first bullet added Section 10.1 “System modes”: updated Section 21.4 “Licenses”: License statement “Purchase of NXP ICs with NFC technology” updated 20150611 • - Preliminary data sheet - PN7120 v.1 Objective data sheet - - Table 33: updated 20150506 All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 49 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 21.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PN7120 Product data sheet COMPANY PUBLIC Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 50 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 21.4 Licenses Purchase of NXP ICs with ISO/IEC 14443 type B functionality This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s Contactless Card patents license for ISO/IEC 14443 B. The license includes the right to use the IC in systems and/or end-user equipment. RATP/Innovatron Technology Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. Purchase of NXP Semiconductors IC does not include a license to any NXP patent (or other IP right) covering combinations of those products with other products, whether hardware or software. 21.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. DESFire — is a trademark of NXP Semiconductors N.V. MIFARE — is a trademark of NXP Semiconductors N.V. MIFARE Classic — is a trademark of NXP Semiconductors N.V. MIFARE Ultralight — is a trademark of NXP Semiconductors N.V. ICODE and I-CODE — are trademarks of NXP Semiconductors N.V. 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 51 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 23. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Quick reference data . . . . . . . . . . . . . . . . . . . . .3 Ordering information . . . . . . . . . . . . . . . . . . . . .4 Marking code . . . . . . . . . . . . . . . . . . . . . . . . . . .5 PN7120 pin description . . . . . . . . . . . . . . . . . . .7 System power modes description . . . . . . . . . .10 System power modes configuration . . . . . . . . .10 System power modes description . . . . . . . . . .10 PN7120 power states . . . . . . . . . . . . . . . . . . . 11 Functional modes in active state . . . . . . . . . . .12 Functionality for I2C-bus interface . . . . . . . . . .15 I2C-bus interface addressing . . . . . . . . . . . . . .15 Crystal requirements . . . . . . . . . . . . . . . . . . . .16 PLL input requirements . . . . . . . . . . . . . . . . . .17 Overview for ISO/IEC 14443A/MIFARE Reader/Writer communication mode . . . . . . . .24 Overview for FeliCa Reader/Writer communication mode . . . . . . . .25 Overview for ISO/IEC 14443B Reader/Writer communication mode . . . . . . . . . . . . . . . . . . .25 Overview for ISO/IEC 15693 VCD communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Overview for Active communication mode . . . .28 Overview for Passive communication mode . .29 Overview for ISO/IEC 14443A/MIFARE card communication mode . . . . . . . . . . . . . . . . . . .30 Overview for ISO/IEC 14443B card communication mode . . . . . . . . . . . . . . . . . . .30 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .33 Operating conditions . . . . . . . . . . . . . . . . . . . .33 Thermal characteristics . . . . . . . . . . . . . . . . . .34 Current consumption characteristics for operating ambient temperature range . . . . . . . . . . . . . . .35 Battery voltage monitor characteristics . . . . . .35 Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Power-up timings . . . . . . . . . . . . . . . . . . . . . . .36 Power-down timings . . . . . . . . . . . . . . . . . . . .36 Thermal threshold . . . . . . . . . . . . . . . . . . . . . .36 High-speed mode I2C-bus timings specification . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Fast mode I2C-bus timings specification . . . . .37 Input clock characteristics on XTAL1 when using PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Pin characteristics for XTAL1 when PLL input .37 Pin characteristics for 27.12 MHz crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PLL accuracy . . . . . . . . . . . . . . . . . . . . . . . . . .38 VEN input pin characteristics . . . . . . . . . . . . . .38 pin characteristics for IRQ, CLK_REQ and BOOST_CTRL . . . . . . . . . . . . . . . . . . . . . . . . .38 Electrical characteristics of ANT1 and ANT2 . .39 Input pin characteristics for RXN and RXP . . .39 Output pin characteristics for TX1 and TX2 . . .40 Output resistance for TX1 and TX2 . . . . . . . . .40 Input pin characteristics for I2CADR0 . . . . . . .40 Pin characteristics for I2CSDA and I2CSCL . .40 SnPb eutectic process (from J-STD-020C) . . .44 PN7120 Product data sheet COMPANY PUBLIC Table 46. Lead-free process (from J-STD-020C) . . . . . . 44 Table 47. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 48. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 49 All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 52 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 24. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. PN7120 transmission modes . . . . . . . . . . . . . . . . .2 PN7120 package marking (top view) . . . . . . . . . . .4 PN7120 block diagram . . . . . . . . . . . . . . . . . . . . .6 PN7120 pinning (bottom view). . . . . . . . . . . . . . . .7 PN7120 connection . . . . . . . . . . . . . . . . . . . . . . . .9 System power mode diagram . . . . . . . . . . . . . . .10 Polling loop: all phases enabled . . . . . . . . . . . . .13 Polling loop: low-power RF polling. . . . . . . . . . . .14 27.12 MHz crystal oscillator connection. . . . . . . .16 Input reference phase noise characteristics . . . .17 PMU functional diagram . . . . . . . . . . . . . . . . . . .18 VDD(TX) offset disabled behavior . . . . . . . . . . . . .19 VDD(TX) behavior when PN7120 is in Standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Battery voltage monitor principle . . . . . . . . . . . . .20 Resetting PN7120 via VEN pin . . . . . . . . . . . . . .21 VBAT is set up before VDD(PAD) . . . . . . . . . . . . . . .21 VDD(PAD) and VBAT are set up in the same time . .22 VDD(PAD) is set up or cut-off after PN7120 has been enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PN7120 power-down sequence. . . . . . . . . . . . . .23 ISO/IEC 14443A/MIFARE Reader/Writer communication mode diagram. . . . . . . . . . . . . . .24 FeliCa Reader/Writer communication mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 ISO/IEC 14443B Reader/Writer communication mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .25 ISO/IEC 15693 VCD communication mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 NFCIP-1 communication mode . . . . . . . . . . . . . .27 Active communication mode . . . . . . . . . . . . . . . .28 Passive communication mode . . . . . . . . . . . . . . .29 Application schematic . . . . . . . . . . . . . . . . . . . . .32 I2C-bus timings . . . . . . . . . . . . . . . . . . . . . . . . . .36 Package outline, VFBGA49, SOT1320-1, MSL 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 53 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 25. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 6 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 7 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 9.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 Functional description . . . . . . . . . . . . . . . . . . . 8 10.1 System modes . . . . . . . . . . . . . . . . . . . . . . . . . 9 10.1.1 System power modes . . . . . . . . . . . . . . . . . . . . 9 10.1.2 PN7120 power states . . . . . . . . . . . . . . . . . . . 10 10.1.2.1 Monitor state . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10.1.2.2 Hard Power Down (HPD) state. . . . . . . . . . . . 11 10.1.2.3 Standby state . . . . . . . . . . . . . . . . . . . . . . . . . 11 10.1.2.4 Active state . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10.1.2.5 Polling loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10.2 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . 14 10.3 Host interfaces . . . . . . . . . . . . . . . . . . . . . . . . 14 10.3.1 I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 15 10.3.1.1 I2C-bus configuration . . . . . . . . . . . . . . . . . . . 15 10.4 PN7120 clock concept . . . . . . . . . . . . . . . . . . 15 10.4.1 27.12 MHz quartz oscillator . . . . . . . . . . . . . . 16 10.4.2 Integrated PLL to make use of external clock 16 10.4.3 Low-power 20 MHz oscillator . . . . . . . . . . . . . 18 10.4.4 Low-power 380 kHz oscillator. . . . . . . . . . . . . 18 10.5 Power concept . . . . . . . . . . . . . . . . . . . . . . . . 18 10.5.1 PMU functional description . . . . . . . . . . . . . . . 18 10.5.2 DSLDO: Dual Supply LDO . . . . . . . . . . . . . . . 18 10.5.3 TXLDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.5.3.1 TXLDO limiter . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.5.4 Battery voltage monitor. . . . . . . . . . . . . . . . . . 20 10.6 Reset concept. . . . . . . . . . . . . . . . . . . . . . . . . 20 10.6.1 Resetting PN7120 . . . . . . . . . . . . . . . . . . . . . 20 10.6.2 Power-up sequences . . . . . . . . . . . . . . . . . . . 21 10.6.2.1 VBAT is set up before VDD(PAD) . . . . . . . . . . . . 21 10.6.2.2 VDD(PAD) and VBAT are set up in the same time 22 10.6.2.3 PN7120 has been enabled before VDD(PAD) is set up or before VDD(PAD) has been cut off . . . . . . 22 10.6.3 Power-down sequence . . . . . . . . . . . . . . . . . . 23 10.7 Contactless Interface Unit. . . . . . . . . . . . . . . . 23 10.7.1 Reader/Writer communication modes . . . . . . 23 10.7.1.1 ISO/IEC 14443A/MIFARE and Jewel/Topaz PCD communication mode . . . . . . . . . . . . . . . . . . . 23 10.7.1.2 10.7.1.3 10.7.1.4 10.7.2 FeliCa PCD communication mode. . . . . . . . . 24 ISO/IEC 14443B PCD communication mode. 25 ISO/IEC 15693 VCD communication mode . . 26 ISO/IEC 18092, Ecma 340 NFCIP-1 communication modes . . . . . . . . . . . . . . . . . . 27 10.7.2.1 ACTIVE communication mode. . . . . . . . . . . . 27 10.7.2.2 Passive communication mode . . . . . . . . . . . . 28 10.7.2.3 NFCIP-1 framing and coding . . . . . . . . . . . . . 29 10.7.2.4 NFCIP-1 protocol support . . . . . . . . . . . . . . . 29 10.7.3 Card communication modes . . . . . . . . . . . . . 30 10.7.3.1 ISO/IEC 14443A/MIFARE card communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.7.3.2 ISO/IEC 14443B card communication mode . 30 10.7.4 Frequency interoperability . . . . . . . . . . . . . . . 31 11 Application design-in information. . . . . . . . . 32 12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33 13 Recommended operating conditions . . . . . . 33 14 Thermal characteristics . . . . . . . . . . . . . . . . . 34 15 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 15.1 Current consumption characteristics . . . . . . . 35 15.2 Functional block electrical characteristics . . . 35 15.2.1 Battery voltage monitor characteristics . . . . . 35 15.2.2 Reset via VEN . . . . . . . . . . . . . . . . . . . . . . . . 35 15.2.3 Power-up timings . . . . . . . . . . . . . . . . . . . . . . 36 15.2.4 Power-down timings. . . . . . . . . . . . . . . . . . . . 36 15.2.5 Thermal protection . . . . . . . . . . . . . . . . . . . . . 36 15.2.6 I2C-bus timings. . . . . . . . . . . . . . . . . . . . . . . . 36 15.3 Pin characteristics . . . . . . . . . . . . . . . . . . . . . 37 15.3.1 XTAL1 and XTAL2 pins characteristics . . . . . 37 15.3.2 VEN input pin characteristics . . . . . . . . . . . . . 38 15.3.3 Pin characteristics for IRQ, CLK_REQ and BOOST_CTRL . . . . . . . . . . . . . . . . . . . . . . . . 38 15.3.4 ANT1 and ANT2 pin characteristics. . . . . . . . 39 15.3.5 Input pin characteristics for RXN and RXP . . 39 15.3.6 Output pin characteristics for TX1 and TX2 . . 40 15.3.7 Input pin characteristics for I2CADR0 . . . . . . 40 15.3.8 Pin characteristics for I2CSDA and I2CSCL . 40 16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 42 17 Soldering of SMD packages . . . . . . . . . . . . . . 43 17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 43 17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 43 17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 43 17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 44 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 46 19 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . 49 continued >> PN7120 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 8 October 2015 312431 © NXP Semiconductors N.V. 2015. All rights reserved. 54 of 55 PN7120 NXP Semiconductors Full NFC Forum-compliant controller with integrated firmware 21 21.1 21.2 21.3 21.4 21.5 22 23 24 25 Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 50 50 50 51 51 51 52 53 54 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 8 October 2015 312431