NS DESIG W E N R ED F O 4B1 MEND HC550rt Center at M O d n C a E R B o 4 T p 0 55 NO S up m/tsc See HCr Technical rsil.co te n u .i o t w tac or w w or c on TERSIL N -I 8 8 1-8 ® May 1997 HC-5504DLC SLIC Subscriber Line Interface Circuit Features Description • Pin for Pin Replacement for the HC-5504 The Intersil SLIC incorporates many of the BORSHT functions on a single IC chip. This includes DC battery feed, a ring relay driver, supervisory and hybrid functions. This device is designed to maintain transmission performance in the presence of externally induced longitudinal currents. Using the unique Intersil dielectric isolation process, the SLIC can operate directly with a wide range of station battery voltages. • Capable of +5V or +12V (VB+) Operation • Monolithic Integrated Device • DI High Voltage Process • Compatible With Requirements Worldwide PBX Performance • Internal Ring Relay Driver The SLIC also provides selective denial of power. If the PBX system becomes overloaded during an emergency, the SLIC will provide system protection by denying power to selected subscriber loops. • Allows Interfacing With Negative Superimposed Ringing Systems The Intersil SLIC is ideally suited for the design of new digital PBX systems by eliminating bulky hybrid transformers. • Controlled Supply of Battery Feed Current for Short Loops (41mA) • Low Power Consumption During Standby • Switch Hook Ground Key and Ring Trip Detection Functions • Selective Denial of Power to Subscriber Loops Applications • Solid State Line Interface Circuit for Analog and Digital PBX Systems • Direct Inward Dial (DID) Trunks • Voice Messaging PBXs • Allows Multi-Phone Operation Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE HC1-5504DLC-5 0o to +75oC HC1-5504DLC-9 -40o to +85oC HC3-5504DLC-5 0o to +75oC HC3-5504DLC-9 -40o to +85oC HC4P5504DLC-5 0o to +75oC HC4P5504DLC-9 -40o to +85oC 28 Lead PLCC HC9P5504DLC-5 0o to +75oC 24 Lead SOIC HC9P5504DLC-9 -40o to +85oC 24 Lead SOIC 24 Lead Ceramic DIP 24 Lead Ceramic DIP 24 Lead Plastic DIP 24 Lead Plastic DIP 28 Lead PLCC Pinouts TIP 1 24 TX RING TIP N/C TX AG C4 HC-5504DLC (PLCC) TOP VIEW RFS HC-5504DLC (PDIP, CDIP, SOIC) TOP VIEW RING 2 23 AG 4 3 2 1 28 27 26 RFS 3 22 C4 VB+ 4 21 RX VB+ 5 25 RX C3 5 20 +IN C3 6 24 +IN DG 6 19 -IN DG 7 23 -IN RS 7 18 OUT N/C 8 22 N/C RD 8 17 C2 RS 9 21 OUT TF 9 16 RC RF 10 15 PD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 8-19 13 14 15 16 17 18 PD RF 12 GKD 13 SHD 19 RC 11 SHD BG 12 TF N/C 14 GKD BG 11 20 C2 VB- VB- RD 10 File Number 2443.3 Specifications HC-5504DLC Absolute Maximum Ratings (Note 1) Operating Conditions Maximum Continuous Supply Voltages (V B-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to +0.5 V (V B+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +15 V (V B+ - VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +75V Relay Drive Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +15V Junction Temperature Ceramic . . . . . . . . . . . . . . . . . . . . . . +175oC Junction Temperature Plastic . . . . . . . . . . . . . . . . . . . . . . . . +150oC Lead Temperature (Soldering 10 Sec.) . . . . . . . . . . . . . . . . +300oC Operating Temperature Range HC-5504DLC-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +75oC HC-5504DLC-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC Relay Driver Voltage (VRD ) . . . . . . . . . . . . . . . . . . . . . . . +5 to +12V Positive Supply Voltage (V B+). . . . . . . 4.75 to 5.25 or 10.8 to 13.2V Negative Supply Voltage (VB-) . . . . . . . . . . . . . . . . . . . . -42 to -58V High Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V Low Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V Loop Resistance (R L) . . . . . . . . . . . . . . . . . . . . . . . . . 200 to 1200Ω CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications Unless Otherwise Specified, V B- = -48V, VB+ = +12V and +5V, AG = BG = DG = 0V, Typical Parameters TA = +25oC. Min-Max Parameters are Over Operating Temperature Range. PARAMETER CONDITIONS MIN TYP MAX UNITS On Hook Power Dissipation ILONG* = 0, VB+ = +12V - 170 235 mW Off Hook Power Dissipation RL = 600Ω, ILONG* = 0, VB+ = +12V - 425 550 mW Off Hook IB+ RL = 600Ω, ILONG* = 0, TA = -40oC - - 6.0 mA Off Hook IB+ RL = 600Ω, ILONG* = 0, TA = +25oC - - 5.3 mA Off Hook IB- RL = 600Ω, ILONG* = 0 - 35 41 mA Off Hook Loop Current RL = 1200Ω, ILONG* = 0 - 21 - mA Off Hook Loop Current RL = 1200Ω, VB- = -42V, ILONG* = 0 TA = +25oC 17.5 - - mA Off Hook Loop Current RL = 200Ω, ILONG* = 0 36 41 48 mA TIP to Ground - 14 - mA RING to Ground - 55 - mA TIP to RING - 41 - mA TIP and RING to Ground - 55 - mA Fault Currents Ring Relay Drive VOL IOL = 62mA - 0.2 0.5 V Ring Relay Driver Off Leakage VRD = +12V, RC = 1 = HIGH, TA = +25oC - - 100 µA Ring Trip Detection Period RL = 600Ω - 2 3 Ring Cycles - - 30 mApk Switch Hook Detection Threshold SHD = VOL 18 - - mA SHD = VOH - - 12 mA Ground Key Detection Threshold GKD = VOL 20 - - mA GKD = VOH - - 10 mA Loop Current During Power Denial RL = 200Ω - ±2 - mA On Hook Ringing Current Dial Pulse Distortion 0 - 5 ms (Note 2) - 110 - kΩ Transmit Output Impedance (Note 2) - 10 20 Ω Two Wire Return Loss (Referenced to 600Ω + 2.16µF), (Note 2) SRL LO - 15.5 - dB ERL - 24 - dB - 31 - dB 2 Wire Off Hook 58 65 - dB 2 Wire On Hook 60 63 - dB 50 58 - dB Receive Input Impedance SRL HI Longitudinal Balance 4 Wire Off Hook 1VRMS 200Hz - 3400Hz, (Note 2) IEEE Method 0 C ≤ TA ≤ +75 C o o 8-20 Specifications HC-5504DLC Electrical Specifications Unless Otherwise Specified, V B- = -48V, VB+ = +12V and +5V, AG = BG = DG = 0V, Typical Parameters TA = +25oC. Min-Max Parameters are Over Operating Temperature Range. (Continued) PARAMETER Low Frequency Longitudinal Balance Insertion Loss CONDITIONS R.E.A. Method, (Note 2), RL = 600Ω 0oC ≤ TA ≤ +75oC TYP MAX UNITS - - 23 dBrnC - - -67 dBm0p - ±0.05 ±0.2 dB - ±0.02 ±0.05 dB - 1 5 dBrnC - -89 -85 dBm0p at 1kHz, 0dBm Input Level, Referenced 600Ω 2 Wire - 4 Wire, 4 Wire - 2 Wire Frequency Response 200 - 3400Hz Referenced to Absolute Loss at 1kHz and 0dBm Signal Level (Note 2) Idle Channel Noise (Note 2) 2 Wire - 4 Wire, 4 Wire - 2 Wire Absolute Delay MIN (Note 2) - - 2 ms Trans Hybrid Loss 2 Wire - 4 Wire, 4 Wire - 2 Wire Balance Network Set Up for 600Ω Termination at 1kHz 36 40 - dB Overload Level VB+ = +5V 1.5 - - Vpeak VB+ = +12V 1.75 - - Vpeak 2 Wire - 4 Wire, 4 Wire - 2 Wire Level Linearity 2 Wire - 4 Wire, 4 Wire - 2 Wire Power Supply Rejection Ratio VB+ to 2 Wire At 1kHz, (Note 2) Referenced to 0dBm Level +3 to -40dBm - - ±0.05 dB -40 to -50dBm - - ±0.1 dB -50 to -55dBm - - ±0.3 dB (Note 2) 15 - - dB VB+ to Transmit 15 - - dB VB- to 2 Wire 15 - - dB VB- to Transmit 15 - - dB VB+ to 2 Wire 30 - 60Hz, RL = 600Ω 30 - - dB VB+ to Transmit 30 - - dB VB- to 2 Wire 30 - - dB VB- to Transmit 30 - - dB - - ±100 µA Logic Input Current (RS, RC, PD) 200 - 16kHz RL = 600Ω 0V ≤ VIN ≤ + 5V Logic Inputs Logic ‘0’ V IL - - 0.8 V Logic ‘1’ V IH 2.0 - 5.5 V - 0.1 0.5 V ILOAD 80µA, VB+ = +12V 2.7 5.0 5.5 V ILOAD 40µA, VB+ = +5V 2.7 - 5.0 V Logic Outputs Logic ‘0’ V OL Logic ‘1’ V OH ILOAD 800µA, VB+ = +12V, +5V * ILONG = Longitudinal Current NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. 2. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. 8-21 Specifications HC-5504DLC Uncommitted Op Amp Specifications MIN TYP MAX UNITS Input Offset Voltage PARAMETER CONDITIONS - ±5 - mV Input Offset Current - ±10 - nA Input Bias Current - 20 - nA Differential Input Resistance (Note 2) - 1 - MΩ Output Voltage Swing RL = 10K, VB+ = +12V - ±5 - V PEAK RL = 10K, VB+ = +5V - ±3 - V PEAK Output Resistance AVCL = 1 (Note 2) - 10 - Ω Small Signal GBW (Note 2) - 1 - MHz Pin Descriptions 28 PIN PLCC 24 PIN DIP/SOIC SYMBOL DESCRIPTION 2 1 TIP An analog input connected to the TIP (more positive) side of the subscriber loop through a 150Ω feed resistor and a ring relay contact. Functions with the Ring terminal to receive voice signals from the telephone and for loop monitoring purposes. 3 2 RING An analog input connected to the RING (more negative) side of the subscriber loop through a 150Ω feed resistor and a ring relay contact. Functions with the Tip terminal to receive voice signals from the telephone and for loop monitoring purposes. 4 3 RFS Senses ring side of loop for ground key and ring trip detection. During ringing, the ring signal is inserted into the line at this node and RF is isolated from RFS via a relay. 5 4 VB + Positive Voltage Source - Most positive supply. VB+ is typically 12V or 5V. 6 5 C3 Capacitor #3 - An external capacitor to be connected between this terminal and analog ground. Required for proper operation of the loop current limiting function, and for filtering V B-. Typical value is 0.3µF, 30V. 7 6 DG Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and outputs on the SLIC microcircuit. 9 7 RS Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a positive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive going zero crossing. This ensures that the ring relay activates and deactivates when the instantaneous ring voltage is near zero. If synchronization is not required, the pin should be tied to +5V. 10 8 RD Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized. 11 9 TF Tip Feed - A low impedance analog output connected to the TIP terminal through a 150Ω feed resistor. Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 12 10 RF Ring Feed - A low impedance analog output connected to the RING terminal through a 150Ω feed resistor. Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 13 11 VB - Negative Voltage Source - Most negative supply. VB- is typically -48V with an operational range of -42V to -58V. Frequently referred to as “battery”. 14 12 BG Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground terminal. 16 13 SHD Switch Hook Detection - A low active LS TTL - compatible logic output. 17 14 GKD Ground Key Detection - A low active LS TTL - compatible logic output. This output is enabled if the DC current into the ring lead exceeds the DC current out of the tip lead by more than 20mA, and disabled if this current difference is below an internally set threshold. 18 15 PD Power Denial - A low active TTL - Compatible logic input. When enabled, the switch hook detect (SHD) and ground key detect (GKD) are not necessarily valid, and the relay driver (RD) output is disabled. 8-22 Specifications HC-5504DLC Pin Descriptions (Continued) 28 PIN PLCC 24 PIN DIP/SOIC SYMBOL DESCRIPTION 19 16 RC Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output goes low on the next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial state (PD = 0) or the subscriber is not already off- hook (SHD = 0). 20 17 C2 Capacitor #2 - An external capacitor to be connected between this terminal and digital ground. Prevents false ground key indications from occurring during ring trip detection. Typical value is 0.15µF, 10V. This capacitor is not used if ground key function is not required and (Pin 17) may be left open or connected to digital ground. 21 18 OUT 23 19 -IN The inverting analog input of the spare operational amplifier. 24 20 +IN The non-inverting analog input of the spare operational amplifier. 25 21 RX Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and Ring feed terminals, which in turn drive tip and ring through 300Ω of feed resistance on each side of the line. 26 22 C4 Capacitor #4 - An external capacitor to be connected between this terminal and analog ground. This capacitor prevents false ground key indication and false ring trip detection from occurring when longitudinal currents are induced onto the subscriber loop from near by power lines and other noise sources. This capacitor is also required for the proper operation of ring trip detection. Typical value is 0.5µF, to 1.0µF, 20V. This capacitor should be nonpolarized. 27 23 AG Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX) and receive input (RX) terminals. 28 24 TX Transmit Output, Four Wire Side - A low impedance analog output which represents the differential voltage across Tip and Ring. Transhybrid balancing must be performed (using the SLIC microcircuit’s spare op amp) beyond this output to completely implement two to four wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is essential. NC No Internal Connection. 1,8,15,22 The analog output of the spare operational amplifier. The output voltage swing is typically ±5V. NOTE: All grounds (AG, BG, & DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first. Functional Diagram RING SYNC RING COMMAND RING TRIP RS RC RD RING CONTROL SHD SWITCH HOOK DETECTION GKD GROUND KEY LOOP MONITORING DETECTION 1/2 RING RELAY TIP TIP 150Ω DIFF AMP + 150Ω TX TRANSMIT OUTPUT TF 2 WIRE LOOP BG SECONDARY PROTECTION BATTERY FEED V B- VB- OUT +1 +IN RF LOOP CURRENT LIMITER RFS 1/2 RING RELAY + LINE DRIVERS RING VOLTAGE -IN 150Ω RING 150Ω OP AMP RING POWER DENIAL PD -1 SLIC MICROCIRCUIT VB- 8-23 RX RECEIVE INPUT HC-5504DLC Schematic SLIC FUNCTIONAL SCHEMATIC (DIP/SOIC PIN NUMBERS SHOWN) 21 22 11 12 23 6 4 20 19 18 RX C4 VBAT BAT GND ANA GND DIG GND VB+ + - OUT VB + VB+ VB1 VB2 VB3 VB4 VB5 +5V VOLTAGE & CURRENT BIAS NETWORK A-400 TIP FEED AMP TF V 9 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 VBATIB9 IB10 IB11 VB2 - BAT RING TRIP DETECTOR IB4 R12 - R8 VB+ R9 R22 IB7 IB8 SWITCH HOOK DETECTOR IB6 17 VB+ SHD SH + R6 - 13 VB1 IB6 R16 QD27 VBAT/2 REFERENCE R15 VB2 R14 R 18 RC THERMAL LIMITING LOAD CURRENT LIMITING I B2 R21 - QD28 16 RFC VB5 + A-300 RING FEED AMP PD VB5 15 R 19 + VBAT C2 STTL AND LOGIC INTERFACE VBAT VBAT - R1 VB+ R2 10 14 + VB3 A-100 TRANSV’L I/V AMP R4 RF GKD GND SHORTS CURRENT LIMITING R5 V + VBAT R23 B + 2 VB4 + IB1 R3 RING VBAT R20 VBAT + R11 VBAT 3 GK A-200 LONG’L I/V AMP QD3 QD36 R10 RING FEED SENSE +5V IB10 VB+ +5V VB+ R7 TIP 1 VBAT IB3 R17 + VB+ A-500 OP AMP IB5 VBAT R13 VBAT VBAT C3 TX RS RD 5 24 7 8 8-24 HC-5504DLC ontinued) LOGIC GATE SCHEMATIC C2 LOGIC BIAS 2 DELAY 4 6 8 7 9 3 5 12 10 13 11 RELAY DRIVER 14 15 TTL TO STTL TTL TO STTL TTL TO STTL TO R21 STTL TO TTL C B A STTL TO TTL A B RS RC PD C RD SHD GKD SCHOTTKY LOGIC High voltage surge conditions are as specified in Table 1. Die Characteristics Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Diode Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102 Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . Connected Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI Thermal Constants (oC/W) θJA θJC Ceramic DIP . . . . . . . . . . . . . . . . . . . . 52 15 Plastic DIP . . . . . . . . . . . . . . . . . . . . . . 52 22 PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . 67 29 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . 76 24 The SLIC will withstand longitudinal currents up to a maximum or 30mArms, 15mArms per leg, without any performance degradation. . Overvoltage Protection and Longitudinal Current Protection The SLIC device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. 8-25 TABLE 1 PARAMETER Longitudinal Surge Metallic Surge TEST CONDITION PERFORMANCE (MAX) UNITS 10µs Rise/ ±1000 (Plastic) V PEAK 1000µs/Fall ±500 (Ceramic) V PEAK 10µs Rise/ ±1000 (Plastic) V PEAK 1000µ Fall ±500 (Ceramic) V PEAK T/GND 10µs Rise/ ±1000 (Plastic) V PEAK R/GND 1000µs Fall ±500 (Ceramic) V PEAK 50/60Hz Current T/GND 11 Cycles 700 (Plastic) V RMS R/GND Limited to 10Arms 350 (Ceramic) V RMS HC-5504DLC Applications Diagram +5V TO +12V SYSTEM CONTROLLER 15 RS1 CS1 K1A TIP SUBSCRIBER LOOP 14 7 POWER SWITCH GROUND RING RING SYNC CMD DENIAL HOOK KEY 8 DETECT DETECT RD RX 1 TIP TX RB2 9 SLIC +IN TIP FEED HC-5504DLC -IN OP AMP VB - RB1 K1B OUT 10 RING FEED 3 RS2 CS2 RING 16 K1 1 PRIMARY PROTECTION 13 RB3 C2 RING FEED SENSE C3 RB4 2 RING C4 NEG. BATT. BATT. GND. DIG. GND. ANA. GND. VB + 11 12 6 23 4 C9 C8 PTC BALANCE NETWORK C5 21 C6 24 20 R1 C7 PCM SWITCHING FILTER/ NETWORK CODEC ZB 19 R3 R2 18 17 5 22 + C4 C3 C2 + VB + -48V 150V PEAK (MAX) RING GENERATOR Z1 -48V FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC Typical Component Values C2 = 0.15µF, 10V C3 = 0.3µF, 30V C4 = 0.5µF to 1.0µF, 10%, 20V (Should be nonpolarized) C5 = 0.5µF, 20V C6 = C7 = 0.5µF (10% Match Required) (Note 2) C8 = 0.01µF, 100V C9 = 0.01µF, 20V, ±20% R1 = R2 = R3 = 100k (0.1% Match Required, 1% absolute value) ZB = 0 for 600Ω Terminations (Note 2) RB1 = RB2 = RB 3 = RB4 = 150Ω (0.1% Match Required, 1% absolute value) RS1 = RS2 =1kΩ, typically. CS1 = CS2 = 0.1µF, 200V typically, depending on VRING and line length. Z1 = 150V to 200V transient protection. PTC used as ring generator ballast. NOTES: 1. Secondary protection diode bridge recommended is a 2A, 200V type. 2. To obtain the specified transhybrid loss it is necessary for the three legs of the balance network, C6-R1 and R2 and C7-ZB-R3, to match in impedance to within 0.3%. Thus, if C6 and C7 are 1µF each, a 20% match is adequate. It should be noted that the transmit output to C6 sees a -22V step when the loop is closed. Too large a value for C6 may produce an excessively long transient at the op amp output to the PCM Filter/CODEC. A 0.5µF and 100kΩ gives a time constant of 50msec. The uncommitted op amp output is internally clamped to stay within ±5.5V and also has current limiting protection. 3. All grounds (AG, BG, & DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first. 4. To prevent saturation of longitudinal amplifier during ringing, the ringer current should be limited to less than 30mA peak. 5. Application shows Ring injected ringing, a Balanced or Tip injected configuration may be used. 6. Pin numbers given for DIP/SOIC package. Additional information is contained in Application Note 549, “The HC-550X Telephone SLICs’’ By Geoff Phillips 8-26 8-27