DATASHEET Dual LDO with Low Noise, Very High PSRR and Low IQ ISL78302A Features ISL78302A is a high-performance dual LDO capable of sourcing 300mA current from each output. It has a low standby current and very high PSRR and is stable with output capacitance of 1µF to 10µF with ESR of up to 200mΩ. • Integrates Two 300mA High-performance LDOs • Excellent Transient Response to Large Current Steps • ±1.8% Accuracy Over All Operating Conditions • Excellent Load Regulation: < 0.1% Voltage Change Across Full Range of Load Current The device integrates an individual Power-On Reset (POR) function for each output. The POR delay for VO2 can be externally programmed by connecting a timing capacitor to the CPOR pin. The POR delay for VO1 is internally fixed at approximately 2ms. A reference bypass pin is also provided for connecting a noise-filtering capacitor for low noise and high-PSRR applications. • Low Output Noise: Typically 30µVRMS at 100µA (1.5V) • Very High PSRR: 90dB at 1kHz • Extremely Low Quiescent Current: 47µA (Both LDOs Active) • Wide Input Voltage Capability: 2.3V to 6.5V • Low Dropout Voltage: Typically 230mV at 300mA The quiescent current is typically only 47µA with both LDOs enabled and active. Separate Enable pins control each individual LDO output. When both Enable pins are low, the device is in shutdown, typically drawing less than 0.3µA. • Stable with 1µF to 10µF Ceramic Capacitors • Separate Enable and POR Pins for Each LDO • Soft-start and Staged Turn-on to Limit Input Current Surge During Enable The ISL78302A is AEC-Q100 qualified. The ISL78302A is rated for the automotive temperature range (-40°C to +105°C). • Current Limit and Overheat Protection • Tiny 10 Ld 3mmx3mm DFN Package • -40°C to +105°C Operating Temperature Range • Pb-free (RoHS Compliant) • AEC-Q100 Qualified Applications • Radio Receivers • Camera Modules • GPS/Navigation • Infotainment Systems ISL78302A VIN (2.3 TO 6.5V) 1 ON 2 ENABLE1 OFF ON ENABLE2 OFF 3 4 5 C1 C2 VIN EN1 VO1 VO2 EN2 POR2 CBYP POR1 CPOR GND 10 VOUT1 9 VOUT2 OK 8 7 VOUT2 TOO LOW VOUT1 OK 6 C3 C4 C5 VOUT1 TOO LOW VOUT2 RESET2 (200ms DELAY, C3 = 0.01µF) RESET1 (2ms DELAY) C1, C4, C5: 1µF X5R CERAMIC CAPACITOR C2: 0.1µF X7R CERAMIC CAPACITOR C3: 0.01µF X7R CERAMIC CAPACITOR FIGURE 1. TYPICAL APPLICATION December 22, 2015 FN7932.2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013, 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL78302A Block Diagram VIN VO1 VO2 LDO VO1 ERROR AMPLIFIER ~1.0V VO2 VREF TRIM IS1 POR COMPARATOR QEN1 VOK1 1V POR1 LDO-1 POR2 QEN2 VO2 100k QEN1 IS2 LDO-2 IS1 VOK2 EN1 CONTROL LOGIC EN2 POR2 VOK2 POR2 DELAY CBYP VO1 BANDGAP AND TEMPERATURE SENSOR VOLTAGE REFERENCE GENERATOR 100k UVLO 1.00V VOK1 0.94V 2 POR1 0.90V CPOR Submit Document Feedback POR1 DELAY GND FN7932.2 December 22, 2015 ISL78302A Pin Configuration ISL78302A (10 LD 3X3 DFN) TOP VIEW VIN 1 10 VO1 EN1 2 9 VO2 EN2 3 8 POR2 CBYP 4 7 POR1 CPOR 5 6 GND Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION 1 VIN Analog I/O Supply Voltage/LDO Input. Connect a 1µF capacitor to GND. 2 EN1 Low Voltage Compatible CMOS Input LDO-1 Enable 3 EN2 Low Voltage Compatible CMOS Input LDO-2 Enable 4 CBYP Analog I/O Reference Bypass Capacitor Pin. Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the desired noise and PSRR performance. 5 CPOR Analog I/O POR2 Delay Setting Capacitor Pin. Connect a capacitor between this pin and GND to delay the POR2 output release after LDO-2 output reaches 94% of its specified voltage level (200ms delay per 0.01µF). 6 GND Ground 7 POR1 Open Drain Output (1mA) Open-drain POR Output for LDO-1 (active-low). Internally connected to VO1 through 100kΩ resistor. 8 POR2 Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low). Internally connected to VO2 through 100kΩ resistor. 9 VO2 Analog I/O LDO-2 Output. Connect capacitor of value 1µF to 10µF to GND (1µF recommended). 10 VO1 Analog I/O LDO-1 Output. Connect capacitor of value 1µF to 10µF to GND (1µF recommended). Connection to system ground. Connect to PCB Ground plane. Ordering Information PART NUMBER (Notes 1, 2, 3) ISL78302AARMMZ PART MARKING DNAL VO1 VOLTAGE (V) VO2 VOLTAGE (V) TEMP RANGE (°C) 3.0 3.0 -40 to +105 PACKAGE (RoHS Compliant) 10 Ld 3x3 DFN PKG DWG. # L10.3x3C ISL78302AARLLZ DNAM 2.9 2.9 -40 to +105 10 Ld 3x3 DFN L10.3x3C ISL78302AARJMZ DNAN 2.8 3.0 -40 to +105 10 Ld 3x3 DFN L10.3x3C ISL78302AARJRZ DNAP 2.8 2.6 -40 to +105 10 Ld 3x3 DFN L10.3x3C ISL78302AARJCZ DNAK 2.8 1.8 -40 to +105 10 Ld 3x3 DFN L10.3x3C ISL78302AARGCZ DNAR 2.7 1.8 -40 to +105 10 Ld 3x3 DFN L10.3x3C ISL78302AARPLZ DNAS 1.85 2.9 -40 to +105 10 Ld 3x3 DFN L10.3x3C ISL78302AARBJZ DNAT 1.5 2.8 -40 to +105 10 Ld 3x3 DFN L10.3x3C NOTES: 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78302A. For more information on MSL, please see Tech Brief TB363. Submit Document Feedback 3 FN7932.2 December 22, 2015 ISL78302A Absolute Maximum Ratings Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.1V VO1, VO2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V Thermal Resistance JA (°C/W) JC (°C/W) 10 Ld 3x3 DFN Package (Notes 4, 5). . . . . 59 18.5 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 ESD Ratings Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3000V Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . . . . 200V Charge Device Model (Tested per AEC-Q100-011) . . . . . . . . . . . . . . 1500V Recommended Operating Conditions Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-40°C to +105°C Operating Temperature Range . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to 105°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF; CPOR = 0.01µF. Boldface limits apply over the operating temperature range, -40°C to +105°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS 6.5 V DC CHARACTERISTICS Supply Voltage 2.3 VIN Quiescent condition: IO1 = 0µA; IO2 = 0µA Ground Current IDD1 One LDO active 30 36 µA IDD2 Both LDO active 47 55 µA 0.3 2.1 µA Shutdown Current IDDS UVLO Threshold VUV+ 1.9 2.1 2.3 V VUV- 1.6 1.8 2.0 V Regulation Voltage Accuracy Maximum Output Current IMAX Internal Current Limit ILIM Dropout Voltage (Note 7) VDO1 VDO2 VDO3 Thermal Shutdown Temperature VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = +25°C -0.8 +0.8 % VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = -40°C to +125°C -1.8 +1.8 % 650 mA Continuous 300 320 mA 475 IO = 300mA; VO 2.5V 450 IO = 150mA; VO 2.5V 225 IO = 300mA; 2.5V VO 2.8V 250 IO = 150mA; 2.5V VO 2.8V 125 IO = 300mA; VO > 2.8V 230 IO = 150mA; VO > 2.8V 115 mV 250 mV 160 mV mV 145 mV TSD+ 145 °C TSD- 110 °C AC CHARACTERISTICS IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1µF Ripple Rejection Submit Document Feedback 4 @ 1kHz 90 dB @ 10kHz 70 dB @ 100kHz 50 dB FN7932.2 December 22, 2015 ISL78302A Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to 105°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF; CPOR = 0.01µF. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued) (Continued) PARAMETER SYMBOL Output Noise Voltage MIN (Note 6) TYP TEST CONDITIONS MAX (Note 6) UNITS IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.1µF BW = 10Hz to 100kHz 30 µVRMS 250 500 µs 30 60 µs/V DEVICE START-UP CHARACTERISTICS Device Enable Time tEN Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO (nom) LDO Soft-Start Ramp Rate tSSR Slope of linear portion of LDO output voltage ramp during start-up EN1, EN2 PIN CHARACTERISTICS Input Low Voltage VIL -0.3 0.5 V Input High Voltage VIH 1.35 VIN + 0.3 V 0.1 µA Input Leakage Current IIL, IIH Pin Capacitance CPIN Informative 5 pF POR1, POR2 PIN CHARACTERISTICS POR1, POR2 Thresholds VPOR+ POR1 Delay 91 94 97 % VPOR- As a percentage of nominal output voltage 87 90 93 % tP1LH 0.5 2.0 3.2 ms 25 tP1HL POR2 Delay tP2LH CPOR = 0.01µF 100 VOL POR1, POR2 Pin Internal Pull-Up Resistance 300 25 tP2HL POR1, POR2 Pin Output Low Voltage 200 µs @ IOL = 1.0mA RPOR 78 100 ms µs 0.2 V 180 kΩ NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. VOx = 0.98*VOx(NOM); valid for VOx greater than 1.85V. EN1 EN2 tEN VPOR+ VPOR- VPOR+ VPOR- <tP1HL VO1 VO2 <tP2HL tP1LH tP1HL tP2LH tP2HL POR1 POR2 FIGURE 2. TIMING PARAMETER DEFINITION Submit Document Feedback 5 FN7932.2 December 22, 2015 ISL78302A Typical Performance Curves 0.10 0.8 VO = 3.3V ILOAD = 0mA 0.4 0.2 -40°C 0.0 +25°C -0.2 +85°C -0.4 VIN = 3.8V VO = 3.3V 0.08 OUTPUT VOLTAGE CHANGE (%) OUTPUT VOLTAGE, VO (%) 0.6 -0.6 0.06 0.04 -40°C 0.02 +25°C 0.00 -0.02 +85°C -0.04 -0.06 -0.08 -0.8 3.4 3.8 4.6 4.2 5.0 5.4 5.8 6.2 -0.10 6.6 0 50 200 250 300 350 400 LOAD CURRENT - IO (mA) FIGURE 3. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) FIGURE 4. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT 0.10 3.4 VIN = 3.8V VO = 3.3V ILOAD = 0mA 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 VO = 3.3V IO = 0mA 3.3 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE CHANGE (%) 150 100 INPUT VOLTAGE (V) 3.2 IO = 150mA 3.1 IO = 300mA 3.0 2.9 -0.08 -0.10 -40 2.8 -25 5 -10 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 3.6 4.1 4.6 5.1 5.6 6.1 6.5 INPUT VOLTAGE (V) FIGURE 5. OUTPUT VOLTAGE CHANGE vs TEMPERATURE FIGURE 6. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) 2.9 350 VO = 2.8V IO = 0mA DROPOUT VOLTAGE, VDO (mV) 2.8 OUTPUT VOLTAGE, VO (V) 3.1 2.7 IO = 150mA 2.6 IO = 300mA 2.5 2.4 2.3 2.6 300 250 VO = 2.8V 200 VO = 3.3V 150 100 50 0 3.1 3.6 4.1 4.6 5.1 5.6 6.1 6.5 INPUT VOLTAGE (V) FIGURE 7. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT) Submit Document Feedback 6 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 400 FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT FN7932.2 December 22, 2015 ISL78302A Typical Performance Curves (Continued) 55 350 VO = 3.3V 50 GROUND CURRENT (µA) DROPOUT VOLTAGE, VDO (mV) 300 250 +85°C +25°C -40°C 200 150 100 +125°C +25°C 45 -40°C 40 35 VO1 = 3.3V VO2 = 2.8V 30 50 IO (BOTH CHANNELS) = 0µA 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 25 400 3.0 3.5 4.0 4.58 5.5 5.0 6.0 6.5 INPUT VOLTAGE (V) FIGURE 9. DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 10. GROUND CURRENT vs INPUT VOLTAGE 55 200 180 50 140 GROUND CURRENT (µA) GROUND CURRENT (µA) 160 +85°C +25°C 120 100 -40°C 80 60 40 VIN = 3.8V VO1 = 3.3V VO2 = 2.8V 20 0 0 50 100 150 200 250 300 45 40 35 VIN = 3.8V VO = 3.3V ILOAD = 0µA 30 BOTH OUTPUTS ON 25 -40 400 350 -25 -10 5 LOAD CURRENT (mA) FIGURE 11. GROUND CURRENT vs LOAD 5 3.5 IL2 = 300mA V O1 95 110 125 VO2 VO1 = 3.3V VO2 = 2.8V IL1 = 300mA IL2 = 300mA 2.5 3 2 POR1 3.0 VOLTAGE (V) VOLTAGE (V) 4 80 FIGURE 12. GROUND CURRENT vs TEMPERATURE VO1 = 3.3V VO2 = 2.8V IL1 = 300mA VIN 20 35 50 65 TEMPERATURE (°C) POR2 CPOR = 0.1µF 2.0 VO1 1.5 1 1.0 0 0.5 V O2 0 0 1 2 3 4 5 TIME (s) 6 7 8 FIGURE 13. POWER-UP/POWER-DOWN Submit Document Feedback 7 9 10 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (s) 3.5 4.0 4.5 5.0 FIGURE 14. POWER-UP/POWER-DOWN WITH POR SIGNALS FN7932.2 December 22, 2015 ISL78302A Typical Performance Curves (Continued) VO = 3.3V ILOAD = 300mA VO2 (10mV/DIV) VO1 (V) CLOAD = 1µF CBYP = 0.01µF VIN = 5.0V VO1 = 3.3V VO2 = 2.8V IL1 = 300mA IL2 = 300mA CL1, CL2 = 1µF CBYP = 0.01µF 3 2 1 4.3V 3.6V VEN (V) 0 5 10mV/DIV 0 0 100 200 300 400 500 600 700 800 900 1000 400µs/DIV TIME (µs) FIGURE 16. LINE TRANSIENT RESPONSE (3.3V OUTPUT) FIGURE 15. TURN-ON/TURN-OFF RESPONSE VO = 2.8V ILOAD = 300mA CLOAD = 1µF CBYP = 0.01µF VO (25mV/DIV) 4.2V 3.5V VO = 1.8V VIN = 2.8V 300mA 10mV/DIV ILOAD 100µA 100µs/DIV 400µs/DIV FIGURE 17. LINE TRANSIENT RESPONSE (2.8V OUTPUT) FIGURE 18. LOAD TRANSIENT RESPONSE 100 1000 90 80 CBYP = 0.1µF 70 PSRR (dB) SPECTRAL NOISE DENSITY (nV/Hz) VIN = 3.6V VO = 1.8V IO = 10mA CLOAD = 1µF 60 50 40 30 20 10 0 0.1 1k 10k FREQUENCY (Hz) 100k FIGURE 19. PSRR vs FREQUENCY Submit Document Feedback 8 1M 100 10 1 VIN = 3.6V VO = 1.8V ILOAD = 10mA CBYP = 0.1µF CIN = 1µF CLOAD = 1µF 0.1 10 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 20. SPECTRAL NOISE DENSITY vs FREQUENCY FN7932.2 December 22, 2015 ISL78302A Functional Description The ISL78302A contains two high-performance LDOs. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL78302A adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, staged turn-on, and soft-start. Smart thermal shutdown protects the device against overheating. Staged turn-on and soft-start minimize start-up input current surges without causing excessive device turn-on time. Power Control The ISL78302A has two separate enable pins (EN1 and EN2) to individually control power to each of the LDO outputs. When both EN1 and EN2 are low, the device is in shutdown mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.3µA. When one or both of the enable pins are asserted, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage, and current generation circuitry power up. Once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the CBYP pin) to the proper operating voltage. After the bypass capacitor has been charged, the LDOs power up in their specified sequence. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30µs/V to minimize current surge. If EN1 is brought high, and EN2 goes high before the VO1 output stabilizes, the ISL78302A delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high before VO2 starts its output ramp, then VO1 turns on first, and the ISL78302A delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high after VO2 starts its output ramp, then the ISL78302A immediately starts to ramp up the VO1 output. If both EN1 and EN2 are brought high at the same time, the VO1 output has priority, and is always powered up first. During operation, whenever the VIN voltage drops below about 1.8V, the ISL78302A immediately disables both LDO outputs. When VIN rises back above 2.1V, the device re-initiates its start-up sequence, and LDO operation resumes automatically. Reference Generation The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01µF capacitor connected to CBYP implements a 100Hz lowpass filter and is recommended for most high-performance applications. For the lowest noise application, a 0.1µF or greater CBYP capacitor should be used. This filters the reference noise below the 10Hz to Submit Document Feedback 9 1kHz frequency band, which is crucial in many noise-sensitive applications. The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference, POR detection thresholds, and other voltage references required for current generation and over-temperature detection. The current generator provides the references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. LDO Regulation and Programmable Output Divider The LDO regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL78302A provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1µF to 10µF output capacitor that has a tolerance better than 20% and ESR less than 200mΩ. The design is performance-optimized for a 1µF capacitor. Unless limited by the application, use of an output capacitor value above 4.7µF is not normally needed as LDO performance improvement is minimal. Each LDO uses an independently trimmed 1V reference. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. Power-On Reset Generation Each LDO has a separate power-on reset (POR) signal generation circuit that outputs to the respective POR pins. The POR signal is generated as follows. A POR comparator continuously monitors the output of each LDO. The LDO enters a power-good state when the output voltage is above 94% of the expected output voltage for a period exceeding the LDO PGOOD entry delay time. In the power-good state, the open-drain PORx output is in a high-impedance state. An internal 100kΩ pull-up resistor pulls the pin up to the respective LDO output voltage. An external resistor can be added between the PORx output and the LDO output for a faster rise time; however, the PORx output should not connect through an external resistor to a supply greater than the associated LDO voltage. For the 1.5V regulated output option, it has been found that the internal pull-ups on POR output does not always function correctly above VIN = 6V. For this reason, it is recommended to use an external 100k pull-up resistor for the POR pin that is associated to the 1.5V output. For outputs higher than 1.5V, no external resistor is required over the full input range from 2.3V to 6.5V. The power-good state is exited when the LDO output falls below 90% of the expected output voltage for a period longer than the PGOOD exit delay time. While power-good is false, the ISL78302A pulls the respective POR pin low. For LDO-1, the PGOOD entry delay time is fixed at about 2ms while the PGOOD exit delay is about 25µs. For LDO-2, the PGOOD entry and exit delays are determined by the value of the external capacitor connected to the CPOR pin. For a 0.01µF capacitor, the FN7932.2 December 22, 2015 ISL78302A entry and exit delays are 200ms and 25µs, respectively. Larger or smaller capacitor values yield proportionately longer or shorter delay times. The POR exit delay should never be allowed to be less than 10µs to ensure sufficient immunity against transient induced false POR triggering. Overheat Detection The bandgap provides a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +145°C, one or both of the LDOs momentarily shuts down until the die cools sufficiently. In the overheat condition, only the LDO sourcing more than 50mA is shut off. This does not affect the operation of the other LDO. If both LDOs source more than 50mA and an overheat condition occurs, both LDO outputs are disabled. Once the die temperature falls back below about +110°C, the disabled LDOs are re-enabled, and soft-start automatically takes place. The ISL78302A provides short-circuit protection by limiting the output current to about 475mA. If short circuited, an output current of 475mA will cause die heating. If the short circuit lasts long enough, the overheat detection circuit will turn off the output. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE December 22, 2015 FN7932.2 On page 4, updated Charged Device Model test method from “JESD22-C101C” to “AEC-Q100-011”. Updated POD L10.3x3C to current version with changes as follows: Removed package outline and included center to center distance between lands on recommended land pattern. Removed Note 4 “Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip.” since it is not applicable to this package. Renumbered notes accordingly. Tiebar Note 4 updated From: Tiebar shown (if present) is a non-functional feature. To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). December 23, 2013 FN7932.1 Page 10 - 2nd line of the disclaimer changed from: "Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted" to: "Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted" May 21, 2012 FN7932.0 Initial Release About Intersil ntersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. For additional products, see www.intersil.com/en/products.html Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 10 FN7932.2 December 22, 2015 ISL78302A Package Outline Drawing L10.3x3C 10 LEAD DUAL FLAT PACKAGE (DFN) Rev 4, 3/15 3.00 5 PIN #1 INDEX AREA A B 10 5 PIN 1 INDEX AREA 1 2.38 3.00 0.50 2 10 x 0.25 6 (4X) 0.10 C B 1.64 TOP VIEW 10x 0.40 BOTTOM VIEW (4X) 0.10 M C B SEE DETAIL "X" (10 x 0.60) (10x 0.25) 0.90 MAX 0.10 C BASE PLANE 2.38 0.20 C SEATING PLANE 0.08 C SIDE VIEW (8x 0.50) 1.64 2.80 TYP C TYPICAL RECOMMENDED LAND PATTERN 0.20 REF 4 0.05 DETAIL "X" NOTES: Submit Document Feedback 11 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). 5. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 6. Compliant to JEDEC MO-229-WEED-3 except for E-PAD dimensions. FN7932.2 December 22, 2015