LDMOS Transistor Bias Control in Basestation RF Power Amplifiers Using Intersil’s ISL21400 Application Note February 27, 2007 Introduction AN1385.0 The ISL21400 Programmable Output Temperature Sensor IC LDMOS transistors are used for RF Power Amplification in numerous applications from point-to-multipoint communications to Radar. The most pervasive application is in cell phone basestations. These RF Power Amplifiers (RFPA) provide from 5W to over 200W of output power per channel, and require very good linearity to maximize the data throughput in a given channel. The main point to consider is that linearity is the DC biasing of the LDMOS transistor for optimal drain current for a given power output. This bias needs to be held constant over temperature and time. Typically the target accuracy for bias current over temperature is ±5% but ±3% is much more desirable for a high performance design. The ISL21400 is an analog output temperature sensor, which is programmable for both DC output voltage and temperature slope (see Figure 2). Two voltage reference blocks produce both temperature compensated and proportional to temperature outputs. There are two DACs inside the device which are programmed via the I2C bus interface. One DAC is for the voltage reference, the other is for the temperature sensor, and they provide 8-bit control to scale either output. The resulting output is summed and then a variable gain stage provides for a gain of 1, 2 or 4. The DC voltage reference output is 1.20V nominal, and considering the DAC scaling and the gain available, this gives a DC output range of 0V to 4.8V (with a 5.0V supply). The nominal temperature slope is -2.1mV/°C, and this is scaled for both positive and negative slopes by the DAC. Including the gain stage, this provides for up to ±8.4mV/°C temperature slope. A simplified circuit of an LDMOS amplifier bias circuit is shown in Figure 1. The DC Bias on these amplifiers is set by applying a DC voltage to the gate (VGS) and monitoring the Drain current (IDD). Ideally, this IDD will be constant over temperature, but since the VGS of LDMOS amplifier devices varies with temperature, some type of temperature compensation is required. One method of setting this DC bias involves using an adjustable reference, DAC, or Digital potentiometer combined with a temperature compensation source, such as a transistor VBE multiplier. This solution can work well, but getting tight temperature compensation can be problematic since the VBE junction temperature characteristic for production transistors will vary. Also, the VGS tempco for LDMOS amplifiers will vary with IDD. The result is that there are variations in VBE junction characteristics as well as the LDMOS characteristics. For optimal temperature compensation, in-circuit adjustments need to be made for both the temperature compensation as well as the VGS bias itself. VDD RF OUT LDMOS TRANSISTOR RF IN BIAS GENERATOR FIGURE 1. RFPA SIMPLIFIED SCHEMATIC A new way to bias an LDMOS amplifier is presented in the following, which involves digitally converting temperature information. VCC TEMP SENSE VTS(n) DAC VREF(m) VREF VOUT A S DAC GAIN SELECT AV = 1, 2, 4 BIAS EEPROM 5 BYTES n = 0 to 255 m = 0 to 255 VSS SCL COMMUNICATIONS AND REGISTERS A0 A1 SDA A2 FIGURE 2. ISL21400 BLOCK DIAGRAM 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC. Copyright Intersil Americas LLC. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1385 The ISL21400 is especially suited to temperature compensation functions due to the slope programmability and 2% accuracy of the temperature sensing function. The bias voltage produced by the device has both a programmable DC component and a temperature slope component. The voltage output is capable of driving nominal resistive loads with up to 0.5mA of DC output current, and can handle up to 500pF of capacitive loads. These characteristics are well suited to LDMOS applications where the output voltage is isolated from any capacitive load with a small resistor, and the bias current required is negligible. U2 VCC supply. An LC filter is added to the U2 VCC supply to insure no RF energy is present on that supply line. Hardware Design using the ISL21400 The ISL21400 SCL and SDA lines can be tied to a local microcontroller or to an I/O connector for external PC control and programming. The A0, A1, A2 pins are all tied to ground giving an I2C slave address of 0101000x, where x is the read/write bit. RFPA bias control using the ISL21400 is very straightforward. The dashed rectangle highlights the RFPA circuit using an MRF9080 from NXP (formerly Freescale)1.The basic schematic is shown in Figure 3. The maximum supply voltage for the ISL21400 (U2) is 5.5V and U1 drops the LDMOS VDD supply from +26V to +5.0V for the The ISL21400 output is connected to the LDMOS gate (VGG) through a lowpass filter, which blocks any RF energy from reaching the ISL21400. A series 100 output resistor (R2) isolates the filter capacitor from the VOUT pin to insure stability. Also, R2 allows a simple shutdown circuit to be added with Q2 and R3, which will provide a soft VGG clamp when the gate of Q2 is brought high (>2V). An open drain gate can be used as well as long as the leakage current at high temperatures is not excessive. FIGURE 3. RFPA BIAS CONTROL WITH THE ISL21400 2 AN1385.0 February 27, 2007 Application Note 1385 Calculating the ISL21400 Register Values The ISL21400 data sheet2 contains guidelines for calculating temperature slope using the three control registers: Offset, Slope and Gain control. We will use the equations given in the following sections to calculate the register values for this design. In this circuit, the N-channel LDMOS transistor gate has approximately a -2.8mV/°C temperature coefficient from -10°C to +85°C. A constant bias drain current is desired, with a target VGS range derived from the data sheet of 2.5V to 3.5V at +25°C. OFFSET SETTING Using Equation 1 for setting VOUT offset and targeting VOUT = 3.0VDC: V OUT DC = A V V REF A REF = 3.00V V REF = 1.20V (EQ. 1) A V A OS = 2.50 Note that since VGS drift is not perfectly linear with temperature, that the IDS bias error will increase at the temperature extremes due to this nonlinearity. Results The amplifier platform was powered up with the VGG voltage clamped in shutdown mode until the ISL21400 was powered up and programmed. The initial setting for VGS = 3.0V was too low for the target value of IDD = 600mA so the value for n was increased until a suitable IDD close to the target was reached. The final register setting was n = B0h. The amplifier platform including the ISL21400 bias control circuit was placed in a temperature chamber and tested from -10°C ambient to +65°C. This resulted in board temperatures from -10°C to +90°C. The bias current was monitored (RF power OFF and input/output terminated in 50) and results are shown in Figure 4. VGG bias voltage was monitored with a voltmeter tied to the drain of Q2 to limit parasitic effects on the LDMOS gate. The result is plotted in Figure 4 as well. Error from Ideal is shown in Figure 5. Figure 5 includes ±5% range, and the amplifier stays within these limits fairly consistently, meeting the design goals. The initial setting for bias appears somewhat high at 620mA (compared to target of 600mA) but this is limited by the resolution of the ISL21400 at the gain = 4 setting. The next lowest offset level results in a bias of 568mA, which is too low. 690 Note that AREF varies from 0 to 1, so to get 2.40, AV = 4, use Equation 2. 2.50 n A REF = ----------- = 0.625 = ---------4 255 n = 159 decimal 670 IDD (mA) (EQ. 2) = 9F hex The variable n corresponds to register address 0h, and the variable AV is the gain register, which is address 02h. TEMPERATURE SLOPE SETTING Using Equation 3 for temperature slope, we can solve for Slope directly: V OUT TS = A V K A PTAT = – 2.8mV C – 2.8 A PTAT = -------------------4 – 2.1 3.70 VGG 650 3.65 630 3.60 610 3.55 IDD 590 3.50 570 3.45 550 -10 10 30 50 3.40 90 70 TEMPERATURE (°C) FIGURE 4. MEASURED DRAIN CURRENT vs TEMPERATURE 5 (EQ. 3) 2 m – 255 A PTAT = 0.333 = ---------------------------------255 3.75 VDD (V) This entire circuit was implemented on the RFPA evaluation board with the MRF9080. The ISL21400 is placed adjacent to the LDMOS device to get best temperature tracking. The register programming is done using a LabVIEW PC tool for software control and parallel port interface board, which has lines for SCL/SDA. The board is disconnected for testing in a temperature chamber. The variable m corresponds to address 01h. The ISL21400 device is then programmed with these parameters for initial testing. Temperature chamber testing is then performed to verify performance, and if needed, adjustments to the register settings are implemented to optimize performance. PERCENT ERROR 3 m = 170 decimal = A9 hex 1 -1 -3 -5 -10 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 90 FIGURE 5. IDD BIAS ERROR VS TEMPERATURE 3 AN1385.0 February 27, 2007 Application Note 1385 One thing to note in this design or any that requires temperature compensation is the mechanical properties of the board mounting and the cooling system. In this example, airflow over the LDMOS device and the temperature sensor was limited, which enhanced the resulting compensation. Also, the sensor was surface mounted with conductive grease next to the LDMOS device. In many designs, precise control over placement and airflow is not possible, but since calibration takes place after the assembly of the unit, these effects can be minimized as long as the final installation is similar to the calibration conditions. References 1. NXP (formerly Freescale) Wireless Infrastructure Division 2100 East Elliot Road Tempe, AZ 85284 (800) 521-6274 http://www.nxp.com/ 2. Intersil Corporation 1001 Murphy Ranch Road Milpitas, CA 95035 http://www.intersil.com/ LDMOS amplifiers also have a characteristic IDD drift over time (drain current reduces for a given VGS), as well as temperature. This can be addressed with either recalibration or purposely setting the IDD bias high, knowing the drift will be in the negative direction. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 4 AN1385.0 February 27, 2007