ISL21400
Data Sheet
March 31, 2011
Programmable Temperature Slope
Voltage Reference
Features
• Programmable reference voltage
The ISL21400 features a precision voltage reference
combined with a temperature sensor whose output voltage
varies linearly with temperature. The precision 1.20V
reference has a very low temperature coefficient (tempco),
and its output voltage is scaled by an internal DAC (VREF) to
produce a temperature stable output voltage that is
programmable from 0V to 1.20V. The output voltage from the
temperature sensor (VTS) is summed with VREF to produce
a temperature dependent output voltage.
The slope of the VTS portion of the output voltage can be
programmed to be positive or negative in the range
-2.1mV/°C to +2.1mV/°C. A programmable gain amplifier
(PGA) sums the VTS and the VREF voltages and provides
gains of 1x, 2x, and 4x to scale the output up to 4.8V and the
slope to ±8.4mV/°C.
The VREF and VTS terms are programmable with 8 bits of
resolution via an I2C bus and the values are stored in
non-volatile registers. The PGA gain is also set via the I2C
bus and the value is stored in a non-volatile register.
Non-volatile memory storage assures the programmed
settings are retained on power-down, eliminating the need
for software initialization at device power-up.
Temperature Characteristics Curve
3.0
VREF (V)
• Programmable Gain Amplifier
• Non-volatile storage of programming registers
• I2C serial interface
• 2% total accuracy over temperature and VCC range
• 200µA typical active supply current
• Operating temperature range = -40°C to +85°C
• 8 Ld MSOP package
• Pb-free (RoHS compliant)
Applications
• RF power amplifier bias compensation
• LCD bias compensation
• Laser diode bias compensation
• Sensor bias and linearization
• Data acquisition systems
• Variable DAC reference
Pinout
2.5
TS = 127
ISL21400
(8 LD MSOP)
TOP VIEW
TS = 255
TS = 0
1.5
• Programmable temperature slope
• Amplifier biasing
AV = 2
2.0
AV = 1
A2
1
8
VCC
A1
2
7
VOUT
A0
3
6
SDA
VSS
4
5
SCL
1.0
0.5
TS = 127
TS = 0
0.0
-40
-15
FN8091.3
10
35
TEMPERATURE (°C)
1
TS = 255
60
85
Pin Descriptions
MSOP
SYMBOL
DESCRIPTION
1
A2
Hardwire slave address pin for I2C serial bus
2
A1
Hardwire slave address pin for I2C serial bus
3
A0
Hardwire slave address pin for I2C serial bus
4
VSS
Ground pin
5
SCL
Serial bus clock input
6
SDA
7
VOUT
8
VCC
Serial bus data input/output
Output voltage
Device power supply
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006-2008, 2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL21400
Ordering Information
PART NUMBER
(Note 3)
PART MARKING
VDD RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL21400IU8Z (Note 2)
DEW
2.7 to 5.5
-40 to +85
8 Ld MSOP (3.0mm), green mtl
M8.118
ISL21400IU8Z-TK (Notes 1, 2)
DEW
2.7 to 5.5
-40 to +85
8 Ld MSOP (3.0mm), green mtl
M8.118
ISL21400USB-EVALZ
Evaluation Board
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL21400. For more information on MSL please see techbrief
TB363.
Block Diagram
VCC
TEMP
SENSE
VTS(n)
DAC
VREF(m)
VREF
VOUT
A
S
DAC
GAIN
SELECT
AV = 1, 2, 4
BIAS
EEPROM
5 BYTES
n = 0 to 255
m = 0 to 255
VSS
2
SCL
COMMUNICATIONS
AND
REGISTERS
A0
A1
SDA
A2
FN8091.3
March 31, 2011
ISL21400
Absolute Maximum Ratings
Thermal Information
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 6.5V
Voltage on VOUT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to VCC
Voltage on All Other Pins . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Thermal Resistance (Typical)
θJA (°C/ W)
8 Ld MSOP Package (Note 4) . . . . . . . . . . . . . . . . .
130
Moisture Sensitivity for MSOP Package
(See Technical Brief TB363) . . . . . . . . . . . . . . . . . . . . . . . Level 2
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Bried TB379 for details.
Analog Specifications
SYMBOL
VCC = 5.5V, TA = +25°C to +85°C, Unless Otherwise Noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 6)
MAX
UNITS
2.7
3.0
5.5
V
POWER SUPPLY
VCC
IQ
IQ(NV)
Supply Voltage Range
Supply
VCC = 2.7V
Standby, SDA = SCL = VCC
200
400
µA
VCC = 5.5V
Standby, SDA = SCL = VCC
235
500
µA
VCC = 2.7V
Nonvolatile write
500
750
µA
VCC = 5.5V
Nonvolatile write
1.3
1.6
mA
2.6
V
Non-Volatile Supply
Vpor
Power-on Recall Voltage
Minimum VCC at which memory recall
occurs
2.0
VCC
Ramp
VCC Ramp Rate
0.2
tD
V/ms
Power-Up Delay
VCC above Vpor, time delay to Register
recall, and I2C Interface in standby
state
3
ms
OUTPUT VOLTAGE PERFORMANCE SPECIFICATIONS
GE1
Gain Error
AV = 2 (Notes 5, 6, 15)
-1
+1
%
GE2
Gain Error
AV = 4 (Notes 5, 6, 15)
-1
+1
%
Temperature Sensor Coefficient
(Notes 5, 12)
-2.0
mV/°C
Absolute Output Voltage (Swing)
Range
Unloaded, TA = +25°C (Note 7)
VCC - 0.100
GND + 0.100
V
Absolute Output Voltage (Swing)
Range
Loaded, IOUT = ±500µA (Note 7)
VCC - 0.250
GND + 0.250
V
TS1
Temperature Sensor Slope
AV = 1, n = 255, m = 255 (Notes 5, 9)
-2.1
mV/°C
TS2
Temperature Sensor Slope
AV = 2, n = 255, m = 255 (Notes 5, 9)
-4.2
mV/°C
TS3
Temperature Sensor Slope
AV = 4, n = 255, m = 255 (Notes 5, 9)
-8.4
mV/°C
K
3
-2.2
-2.1
FN8091.3
March 31, 2011
ISL21400
Analog Specifications
VCC = 5.5V, TA = +25°C to +85°C, Unless Otherwise Noted. (Continued)
PARAMETER
TS4
Incremental Temperature Sensor Slope
AV = 1, n = 255, m = 0 to 255
(Notes 5, 13)
8.2
TSNL
Temperature Slope Non-Linearity
n = 255, m = 0 to 255, T = -40°C to
+85°C
(Notes 5, 14)
±0.5
DNL
DAC Relative Linearity
(VCC = 2.7 to 5.5V)
VREF and Temp Sense; AV = 1 (Note 17)
INL
DAC Absolute Linearity (VCC = 2.7 to
5.5V)
VREF and Temp Sense; AV = 1 (Note 17)
VOUT(TE) Total Error for VOUT
TEST CONDITIONS
MIN
TYP
(Note 6)
SYMBOL
MAX
UNITS
µV/°C
per
Code
±1.0
%
-1.0
+1.0
LSB
-3.0
+3.0
LSB
±1
±2
%
(Notes 5, 11, 12)
VOUT1
Output Voltage VREF, Gain = 1
AV = 1, n = 255, m = 128, TA = +25°C,
VCC = 5.5V
1.189
1.2
1.211
V
VOUT2
Output Voltage VREF, Gain = 2
AV = 2, n = 255, m = 128, TA = +25°C,
VCC = 5.5V
2.378
2.40
2.422
V
VOUT3
Output Voltage VREF, Gain = 4
AV = 4, n = 255, m = 128, TA = +25°C,
VCC = 5.5V
4.756
4.80
4.844
V
VOUT4
Output Voltage VREF + TS
AV = 1, n = 255, m = 0, TA = +85°C
(Note 7)
1.315
1.326
1.337
V
VOUT5
Output Voltage VREF + TS
AV = 1, n = 255, m = 128, TA = +85°C
(Note 7)
1.188
1.199
1.210
V
VOUT6
Output Voltage VREF + TS
AV = 1, n = 255, m = 255, TA = +85°C
(Note 7)
1.063
1.074
1.085
V
VOUT7
Output Voltage VREF + TS
AV = 1, n = 255, m = 0, TA = -40°C,
(Note 7)
1.052
1.063
1.074
V
VOUT8
Output Voltage VREF + TS
AV = 1, n = 255, m = 128, TA = -40°C,
(Note 7)
1.189
1.200
1.211
V
VOUT9
Output Voltage VREF + TS
AV = 1, n = 255, m = 255, TA = -40°C,
(Note 7)
1.336
1.325
1.347
V
50
60
OUTPUT VOLTAGE DC SPECIFICATIONS
PSRR
Power Supply Rejection Ratio
AV = 1, n = 255, m = 128, (Note 10)
ROUT
Output Impedance (load regulation)
Given by ROUT = (ΔVOUT/ΔIOUT),
TA = +25°C, IOUT = ±500µA
2
5
Ω
Short Circuit, Sourcing
VCC = 5.5V, VOUT = 0V
5
9
mA
Short Circuit, Sinking
VCC = 5.5V, VOUT = 5.5V
6
9
mA
Load Capacitance
Reference output stable for all CL up to
specifications
5
nF
0.1Hz to 10Hz, AV =1
90
µVP-P
10Hz to 10kHz, CL = 0, AV = 1
TBD
mVRMS
Power-On Response
1% Settling
500
µs
Line Ripple Rejection
VCC = 5V ±100mV, f = 120Hz
60
dB
ISC
CL
dB
OUTPUT VOLTAGE AC SPECIFICATIONS
VN
Output Voltage Noise
4
FN8091.3
March 31, 2011
ISL21400
Serial Interface Specification for SCL, SDA, A0, A1, A2 Unless Otherwise Noted.
SYMBOL
PARAMETER
ILI
Input Leakage
VIL
Input LOW Voltage
VIH
Hysteresis
TEST CONDITIONS
MIN
TYP
(Note 2)
VIN = GND to VCC
MAX
UNITS
1
V
-0.3
0.3 x VCC
V
Input HIGH Voltage
0.7 x VCC
VCC + 0.3
SDA and SCL Input Buffer
Hysteresis
0.05 x VCC
VOL
SDA Output Buffer LOW Voltage
IOL = 3mA
Cpin
Pin Capacitance
(Note 7)
fSCL
SCL Frequency
tsp
tAA
V
V
0.4
V
(Note 7)
400
kHz
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed
(Note 7)
50
ns
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing
30% of VCC, until SDA exits
the 30% to 70% of VCC
window (Note 7)
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VCC
during a STOP condition, to
SDA crossing 70% of VCC
during the following START
condition (Note 7)
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC
crossing (Note 7)
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC
crossing (Note 7)
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA
falling edge; both crossing
70% of VCC (Note 7)
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge
crossing 30% of VCC to SCL
falling edge crossing 70% of
VCC (Note 7)
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to
70% of VCC window, to SCL
rising edge crossing 30% of
VCC (Note 7)
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge
crossing 70% of VCC to SDA
entering the 30% to 70% of
VCC window (Note 7)
0
ns
tSU:STO
STOP Condition Set-up Time
From SCL rising edge
crossing 70% of VCC, to
SDA rising edge crossing
30% of VCC (Note 7)
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to
SCL falling edge; both
crossing 70% of VCC
(Note 7)
1300
ns
Output Data Hold Time
From SCL falling edge
crossing 30% of VCC, until
SDA enters the 30% to 70%
of VCC window (Note 7)
0
ns
SDA and SCL Rise Time
From 30% to 70% of VCC
(Note 7)
tDH
tR
5
0
10
20 + 0.1 x Cb
pF
250
ns
FN8091.3
March 31, 2011
ISL21400
Serial Interface Specification for SCL, SDA, A0, A1, A2 Unless Otherwise Noted. (Continued)
SYMBOL
TEST CONDITIONS
MAX
UNITS
SDA and SCL Fall Time
From 70% to 30% of VCC
(Note 7)
20 + 0.1 x Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
(Note 7)
10
400
pF
Rpu
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by
tR and tF
For Cb = 400pF, max is
about 2kΩ~2.5kΩ
For Cb = 40pF, max is about
15kΩ~20kΩ
1
ILO
Output Leakage Current (SDA only) VOUT = GND to VCC
VIL
A1, A0, SHDN, SDA, and SCL Input
Buffer LOW Voltage
VIH
A1, A0, SHDN, SDA, and SCL Input
Buffer HIGH Voltage
VOL
SDA Output Buffer LOW Voltage
Capacitive Loading of SDA or SCL
µA
-0.3
VCC x 0.3
V
VCC x 0.7
VCC
V
IOL = 100µA (Note 7), at
3mA sink
0
0.4
V
Total on-chip and off-chip
(Note 7)
10
400
pF
1,000,000
Cycles
50
Years
Temperature T ≤ +55°C
EEPROM Retention
kΩ
1
EEPROM Endurance
tWC
(Note 18)
MIN
TYP
(Note 2)
tF
CL
PARAMETER
Non-Volatile Write Cycle Time
12
20
ms
NOTES:
5. Equation 1 governs the output voltage and is stated as follows:
⎧
n
( 2 • m ) – 255 ⎫
V OUT = A V • ⎨ V REF • ---------- + K ( T – T 0 ) -------------------------------- ⎬, n = 0 to 255, m = 0 to 255, K = -2.1mV/C(typ), T0 = +25°C
255
255
⎩
⎭
6. Typical values are for TA = +25°C and VCC = 5.5V.
7. This parameter is not 100% tested.
8. Cb = total capacitance of one bus line in pF.
9. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user.
10. Over the specified temperature range. Temperature slope (TS) is measured by the box method whereby the change in VOUT is divided by the
temperature range; in this case, -40°C to +85°C = +125°C. TS1, TS2, TS3 =
V OUT ( Tmin ) – V OUT ( Tmax )
TS = -------------------------------------------------------------------------------Tmin – Tmax
11. Given by PSRR (dB) = 20 * log10 (ΔVout/ΔVCC) at DC.
12. Test +25°C and +85°C only.
13. Total error of Equation 1 @ AV = 1, K = -2.1mV/°C, VREF = 1.20V, m = 255, n = 255 to 0, VCC = 3.0V.
V OUT ( measured ) – V OUT ( Equation1 )
V OUT ( TE ) = ------------------------------------------------------------------------------------------------------------- x100%
V OUT ( Equation1 )
14. Over the specified temperature range. Temperature slope (TS) is measured by the box method whereby the change in VOUT is divided by the
temperature range. Incremental TS is the temperature slope at m = 255 minus the temperature slope at m = 0 divided by 255 with AV = 1, n = 255
⎛ V OUT ( Tmin ) – V OUT ( Tmax )
⎞ ⎛ V OUT ( Tmin ) – V OUT ( Tmax )
⎞
TS4 = ⎜ -------------------------------------------------------------------------------⎟ – ⎜ -------------------------------------------------------------------------------⎟ ÷ 255
( Tmin – Tmax )
( Tmin – Tmax )
⎝
⎠
⎝
m = 255
m = 0⎠
6
FN8091.3
March 31, 2011
ISL21400
Serial Interface Specification for SCL, SDA, A0, A1, A2 Unless Otherwise Noted. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
(Note 2)
MIN
MAX
UNITS
NOTES:(Continued)
15. Temperature Slope Non- linearity is measured over the specified temperature range. The actual change in output voltage is subtracted from the
expected change in output voltage, and then divided by the expected change to normalize before converting to percent.
( T S y ( ΔT ) ) – ΔVOUT
TSNL = ---------------------------------------------------------- x100%; y = 1, 2, 3
TS y × ΔT
16. For codes n = 8 to 255
17. Guaranteed monotonic.
18. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal nonvolatile
write cycle.
Timing Diagrams
Bus Timing
tHIGH
tF
SCL
tLOW
tsp
tR
tHD:STO
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA
(INPUT TIMING)
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
Write Cycle Timing
SCL
SDA
8th BIT OF LAST BYTE
ACK
tWC
STOP
CONDITION
7
START
CONDITION
FN8091.3
March 31, 2011
ISL21400
Typical Performance Curves
3.0
6.0
AV = 2
2.5
TS = 127
1.5
5.0
TS = 255
TS = 0
VREF (V)
VREF (V)
2.0
AV = 1
1.0
0.5
AV = 4
5.5
4.5
TS = 127
TS = 127
TS = 0
0.0
-40
-15
10
35
TS = 255
60
3.5
3.0
-40
85
-15
FIGURE 1. VOUT vs TEMPERATURE (AV = 1, 2)
35
60
85
FIGURE 2. VOUT vs TEMPERATURE (AV = 4)
0.40
VREF REGISTER = 255d
0.35 TS REGISTER = 127d
VREF REGISTER = 255d
TS REGISTER = 127d
+85°C
0.30
ICC (mA)
1.21
VREF (V)
10
TEMPERATURE (°C)
TEMPERATURE (°C)
1.22
TS = 255
TS = 0
4.0
1.20
+25°C
0.25
0.20
-40×C
-40°C
0.15
0.10
1.19
0.05
1.18
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
2
3
NO LOAD
AV = 1
100µV/DIV (VOUT x 1000)
5
6
7
VCC (V)
VCC (V)
FIGURE 3. VOUT vs VCC (VCC = +2.7V TO +5.5V)
4
FIGURE 4. SUPPLY VOLTAGE vs SUPPLY CURRENT
NO LOAD
AV = 4
50µV/DIV (VOUT x 1000)
FIGURE 5. VOUT VOLTAGE NOISE (AV = 1, NO LOAD)
8
FIGURE 6. VOUT VOLTAGE NOISE (AV = 4, NO LOAD)
FN8091.3
March 31, 2011
ISL21400
Typical Performance Curves
(Continued)
CH1 = VCC
1.22
VREF (V)
1.21
CH2 = VOUT
1.20
1.19
VREF REGISTER = 255d
TS REGISTER = 127d
1.18
-40
-15
10
35
60
85
TEMPERATURE (°C)
FIGURE 8. POWER-ON
FIGURE 7. ACCURACY vs TEMPERATURE (-40°C TO +85°C)
3
1.0
0.8
AT +25°C
0.6
0.4
1
0
AT +25°C
-1
DNL IN LSB
INL IN LSB
2
0.2
0.0
-0.2
-0.4
-0.6
-2
-0.8
-3
-1.0
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255
CODE
FIGURE 9. INL, VREF AND TEMP SLOPE DAC
1.4
1.2
FIGURE 10. DNL, VREF AND TEMP SLOPE DAC
1.40
AT +25°C
TS REGISTER = 127d
VREF REGISTER = 255d
1.35
1.30
1.0
0.8
VREF (V)
VREF (V)
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255
CODE
0.6
0.4
1.25
1.15
1.10
0.2
+85°C
1.20
-40°C
1.05
0.0
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255
VREF REGISTER CODE (m)
FIGURE 11. VOUT vs VREF CODE (m)
9
1.00
0 15 30 45 60 75 90 105 120 135 15 0 165 180 195 210 225 240 255
TS REGISTER CODE (n)
FIGURE 12. VOUT vs TEMP SENSE CODE (n), TA = -40°C AND
+85°C
FN8091.3
March 31, 2011
ISL21400
Typical Performance Curves
(Continued)
1.209
1.208
1.207
VREF REGISTER = 255d
TS REGISTER = 127d
AT +25°C
VREF (V)
1.206
1.205
1.204
1.203
1.202
1.201
1.200
-1
-0.5
0
IOUT (mA)
0.5
1
FIGURE 13. VOUT vs IOUT (±1mA)
Pin Descriptions
Functional Description
VOUT
Functional Overview
Programmable voltage output pin. Absolute voltage is
determined by device temperature and Equation 1. Drive
capability is limited to ±500µA output current and 5000pF
output capacitance.
Refer to the Functional Block Diagram on page 2. The
ISL21400 provides a programmable output voltage which
combines both a temperature independent term and a
temperature dependent term. The temperature independent
term uses a bandgap voltage reference, and the
temperature dependent term uses a Proportional To
Absolute Temperature (PTAT) reference, or Temperature
Sensor. Each voltage source is scalable using two DACs via
the I2C serial bus. The resulting output voltage can vary from
0V to over 5V and has a variable, programmable
Temperature Slope (TS).
A2, A1, A0
Hardware slave address pins that can be used to provide
several ISL21400 with a unique physical address to allow for
multiple devices off one I2C bus.
GND
This is the circuit ground pin. It is common for the VOUT and
control signal inputs.
SDA
Serial Data Input/Output. Bidirectional pin used for serial
data transfer. As an output, it is open drain and may be
wire-ored with any number of open drain or open collector
outputs. A pull-up resistor is required and the value is
dependent on the speed of the serial data bus and the
number of outputs tied together.
SCL
Reference Sections
Referring to the Block Diagram on page 2, the VREF and
Temperature Sense (VTS) outputs are summed together (Σ)
and then passed through the output gain stage (A). The
voltage output is programmable and is determined by
Equation 1:
⎧
n
( 2 • m ) – 255 ⎫
V OUT = A V • ⎨ V REF • ---------- + V TS -------------------------------- ⎬
255
255
⎩
⎭
(EQ. 1)
where:
Serial Clock Input. Accepts a clock signal for clocking serial
data into and out of the device. The SCL line requires a
pull-up resistor whose value is dependent on the speed of
the serial clock bus and the number of inputs tied together.
VCC
Positive Power Supply. Connect to a voltage supply in the
range of 2.7V < VCC < 5.5V, with minimum noise and ripple. For
best performance, bypass with a 0.1µF capacitor to ground.
If the AV gain is set to 4 and VOUT approaches 5.0V, then
VCC must be set to >5.2V for best output performance.
• AV = 1, 2, 4
• VREF = 1.200 (not temperature dependent)
• 0 ≤ n ≤ 255 (setting contained in Register 0, VREF)
• VTS = K(T - T0)
• K = dVTS/ dT = -2.1mV/C
• T = device temperature
• T0 = +25°C
• 0 ≤ m ≤ 255 (setting contained in Register 1, TS)
See “Applications Information” on page 14 for ways to use
Equation 1 and methods for output voltage calculations.
10
FN8091.3
March 31, 2011
ISL21400
TABLE 1. ISL21400 REGISTER BIT MAP
Addr
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
0
VREF7
VREF6
VREF5
VREF4
VREF3
VREF2
VREF1
VREF0
1
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
2
D7
D6
D5
D4
D3
D2
GAIN1
GAIN0
3
D7
D6
D5
D4
D3
D2
D1
D0
4
D7
D6
D5
D4
D3
D2
D1
D0
DACs Section
Register 1: Temperature Slope Gain (Nonvolatile)
The ISL21400 contains two 8-bit DACs whose registers can
be programmed via the I2C serial bus. The DAC registers
are non-volatile such that the values are restored during the
VCC power-up cycle of the device. One DAC (VREF) is
dedicated to scale the bandgap voltage reference
(Temperature invariant) and the other DAC (VTS) is
dedicated to scale the Temperature Sensor. Both of these
DACs can determine the output voltage as defined by
Equation 1 (see “Register Descriptions”).
Register 1 sets the Temperature Slope (TS) of the
temperature sensor. Referring to Equation 1, the number “m”
is the setting from Register 1 as shown in Equation 3:
Output Gain Amplifier Section
The ISL21400 contains an output gain amplifier (A) that is
programmed via the I2C serial bus. The gain amplifier is the
last stage before the output and therefore controls the
overall gain for the device. The gain can be programmed for
1x, 2x, or 4x amplification. This gain factor is used to
program the output voltage as determined by Equation 1
(see “Register Descriptions”).
There are 5 registers in the ISL21400 device, all nonvolatile
(see Table 2). All registers are accessible for reading or
writing through the I2C serial bus.
Register Descriptions
NONVOLATILE
0
Y
Reference setting
1
Y
Temperature Sensor setting
2
Y
Gain and storage
3
Y
Storage
4
Y
Storage
DESCRIPTION
(EQ. 2)
11
Register 2: Device Gain and Storage (nonvolatile)
TABLE 3. REGISTER 2 OUTPUT GAIN (NONVOLATILE):
OUTPUT GAIN
GAIN1
GAIN0
OUTPUT GAIN, AV
0
0
x1
0
1
x2
1
0
x2
1
1
x4
Registers 3 and 4: General Purpose Data
(nonvolatile)
Register 0 sets the output voltage of the bandgap reference
(VREF). Referring to Equation 1, the number “n” is the setting
from Register 0 as shown in Equation 2:
This term of Equation 1 can vary from 0V to 1.20V.
VTS is the temperature dependent term and varies from
+136mV at -40°C to -126mV at +85°C. The other term varies
from -1 to +1 and scales the temperature term before adding
to the VREF portion.
The other 6-bits in the register can be used for general
purpose memory (nonvolatile) or left alone.
Register 0: Bandgap Reference Gain (Nonvolatile)
n
V REF • ---------- , for n = 0 to 255
255
(EQ. 3)
Register 2 contains 2 bits (2 LSB’s) which control the output
gain of the device. Table 3 shows the state of these two bits
and the resulting output gain. Note that two states produce
the same gain (Gain 1:0 set to 01b and 10b) of x2.
TABLE 2. REGISTER DESCRIPTIONS
REG
( 2 • m ) – 255
V TS -------------------------------255
These two registers are one byte each and can be used for
general purpose nonvolatile memory.
I2C Serial Interface
The ISL21400 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is the master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL21400
operates as a slave device in all applications.
FN8091.3
March 31, 2011
ISL21400
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 10). On power-up of the ISL21400 the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL21400 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 10). A START condition is ignored during the
power-up sequence and during non-volatile write cycles for
the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 10) A STOP condition at the end of
a read operation, or at the end of a write operation places
the device in its standby mode. A STOP condition at the end
of a write operation to a non-volatile byte initiates an internal
non-volatile write cycle. The device enters its standby state
when the internal, non-volatile write cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 11).
The ISL21400 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL21400 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 0101 A2 A1 A0 as the
seven MSBs. The A2 A1 A0 bits must correspond to the
logic levels at those pins of the ISL21400 device. The LSB in
the Read/Write bit. Its value is “1” for a Read operation, and
“0” for a Write operation (see Table 4).
Write Operation
TABLE 4. IDENTIFICATION BYTE FORMAT
0
1
0
1
A2
(MSB)
A1
A0
R/W
(LSB)
non-volatile write cycle. During this time, the device ignores
transitions at the SDA and SCL pins, and the SDA output is
at a high impedance state. When the internal non-volatile
write cycle is completed, the ISL21400 enters its standby
state (see Figure 12).
STOP conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte and
its associated ACK signal. If a STOP byte is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the ISL21400 resets itself without performing the
write. The contents of the array are not affected.
Data Protection
A valid Identification Byte, Address Byte, and total number of
SCL pulses act as a protection for the registers. A STOP
condition also acts as a protection for non-volatile memory.
During a Write sequence, the Data Byte is loaded into an
internal shift register as it is received. The presence of the
STOP condition after the rest of the bits are received then
triggers the non-volatile write.
Read Operation
A Current Address Read operation is shown in Figure 13. It
consists of a minimum 2 bytes: a START followed by the ID
byte from the master with the R/W bit set to 1, then an ACK
followed by the data byte or bytes sent by the slave. The
master terminates the Read operation by not responding
with an ACK and then issuing a STOP condition. This
operation is useful if the master knows the current address
and desires to read one or more data bytes.
A Random Address Read operation consists of a three byte
“dummy write” instruction followed by a Current Address
Read operation (see Figure 14). The master initiates the
operation issuing the following sequence: a START, the
identification byte with the R/W bit set to "0", an Address
Byte, a second START, and a second Identification byte with
the R/W bit set to "1". After each of the three bytes, the
ISL21400 responds with an ACK. The ISL21400 then
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the Read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(see Figure 13).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial’s value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
Address 04h is the last valid data byte, higher addresses are
not available. Data from addresses higher than memory
location 04h will be invalid.
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL21400 responds with an ACK. The master will then send
a STOP and at this time the device begins its internal
12
FN8091.3
March 31, 2011
ISL21400
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 14. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH
HIGH
SDA OUTPUT
FROM RECEIVER
START
ACK
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
T
A
R
T
SIGNALS FROM THE
MASTER
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH R/W = 0
0 1
ADDRESS
BYTE
0 1 A2 A1 A0 0
SIGNALS FROM THE
ISL21400
0 0 0 0
S
T
O
P
DATA
BYTE
0
A
C
K
A
C
K
A
C
K
FIGURE 16. BYTE WRITE SEQUENCE
S
T
A
R
T
SIGNALS
FROM THE
MASTER
SIGNAL AT SDA
READ
A
C
K
IDENTIFICATION
BYTE WITH R/W = 1
S
T
O
P
A
C
K
0 1 0 1 A2 A1 A0 1
SIGNALS FROM
THE SLAVE
A
C
K
FIRST READ DATA
BYTE
LAST READ DATA
BYTE
FIGURE 17. ADDRESS READ SEQUENCE
13
FN8091.3
March 31, 2011
ISL21400
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R BYTE WITH R/W = 0
T
SIGNAL AT SDA
ADDRESS
BYTE
0 1 0 1 A A A 0
A
C
K
S
T
O
P
A
C
K
0 1 0 1 A A A 1
0 0 0 0 0
A
C
K
A
C
K
SIGNALS FROM
THE SLAVE
S
T
A
R IDENTIFICATION
T BYTE WITH R/W = 1
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 18. RANDOM ADDRESS READ SEQUENCE
Applications Information
DC OUTPUT CONTROL DISCUSSION
The reference term yields Equation 4 for Reference Output:
Power-Up Considerations
The ISL21400 has on-chip EEPROM memory storage for
the DAC and gain settings of the device. These settings
must be recalled correctly on power-up for proper operation.
Normally there are no issues with recall, although it is always
best to provide a smooth, glitch-free power-up waveform on
VCC. Adding a small 0.1µF capacitor at the device VCC will
help with power-up as well as VOUT load changes.
Noise Performance
The output noise voltage in a 0.1Hz to 10Hz bandwidth is
typically 90µVP-P. The noise measurement is made with a
bandpass filter made of a 1-pole high-pass filter with a
corner frequency at 0.1Hz and a 2-pole low-pass filter with a
corner frequency at 12.6Hz to create a filter with a 9.9Hz
bandwidth. Load capacitance up to 5000pF can be added
but will result in only marginal improvements in output noise
and transient response. The output stage of the ISL21400 is
not designed to drive heavily capacitive loads. For high
impedance loads, an R-C network can be added to filter high
frequency noise and preserve DC control.
Output Voltage Programming Considerations
Setting and controlling the output voltage of the ISL21400
can be done easily by breaking down the components into
temperature variant and invariant, and setting them
separately. Let’s use Equation 1 to derive separate
Reference Output and Output Temperature Slope equations:
⎧
( 2 • m ) – 255 ⎫
n ⎫ ⎧
V OUT = ⎨ A V • V REF • ---------- ⎬ + ⎨ A V • V • ⎛ ----------------------------------⎞ ⎬
⎠
TS ⎝
255
255 ⎭ ⎩
⎭
⎩
= { A V • V REF • A REF } + { A V • V
TS
• A TS }""
Reference Term + Temp Slope Term
The first term controls the output DC value, and the second
term controls the Temperature slope, where
n
A REF = ---------- (ranges from 0 to 1)
255
( 2 • m ) – 255
A TS = ⎛ ----------------------------------⎞
⎝
⎠
255
(ranges from -1 to +1)
14
V OUT (DC) = A • V REF • A REF
V
(EQ. 4)
Note that the DC term is dependent on the 1.20V reference
voltage, which is constant, the overall gain, AV, and the
Reference gain, AREF. Since the product AV*AREF ranges
from 0 to 4, the total reference DC output can range from
0.0V to 4.8V. In order to get the 4.8V output, VCC must be
greater than 4.8V by the output dropout plus any overhead
for output loading (the specification for VOUT = 5.0V is listed
with VCC = 5.5V). The Resolution of VOUT(DC) control
changes with AV, so that with a 4.80V full scale output
(AV = 4), the resolution is 4.80/255 or 18.8mV/bit. With
AV = 1, the resolution is 4.7mV/bit.
TEMP SENSE CONTROL DISCUSSION
Equation 4 yields this expression, Equation 5, for
Temperature Slope:
V OUT ( TS ) = A V • V TS • A TS
(EQ. 5)
Since VTS = K(T - T0), the slope term is dependent on the
base temp slope of the device, K (-2.1mV/°C), and the gain
terms AV and ATS. This gives a formula (Equation 6) for the
portion of VOUT at a specific temperature:
V OUT ( TS ) = A V • K • A TS • ( T – T 0 )
(EQ. 6)
The product AV*ATS ranges from -4 to 4, so the Temperature
Slope can range from -8.4 to +8.4mV/°C, which is
independent of the output DC voltage. The resolution of
Slope control is determined by this range (±8.4mV/°C) and
the gain terms, and will vary from 65.8µV/°C/bit (AV = 4)
down to 16.2µV/°C/bit (AV = 1).
At T = T0 = +25°C, VOUT(TS) = 0, no changes in ATS will
cause a change in VOUT, and VOUT will only vary with the
VOUT(DC) control. As temperature increases or decreases,
from T = +25°C, VOUT will then change according to the
programmed Temp Slope.
FN8091.3
March 31, 2011
ISL21400
In many cases a form of Equation 6 is needed which yields a
VOUT change with respect to temperature. By rearranging,
we get Equation 7:
V OUT ( TS )
V OUT ( T ) = ----------------------------- = A V • K • A TS ,(in mV/°C )
( T – T0 )
(EQ. 7)
EXAMPLE 1: PROGRAMMED TEMPERATURE
COMPENSATION EXAMPLE
The ISL21400 can easily compensate for known
temperature drift by programming the device for the initial
VOUT setting and Tempco using standard equations and
some simple steps. The accuracy of the final programmed
output will be limited to the data sheet specifications
(typically 1% accuracy for VOUT and Slope).
In this example, an N-Channel MOSFET gate has a
-2.8mV/°C Tempco from -10°C to +85°C. A constant bias
drain current is desired, with a target Vgs range derived from
the data sheet of 2.5V to 3.5V at +25°C.
VOUT parameters, the system characteristics can be
recorded.
For the following example, let’s determine the voltage output,
VOUT(DC) at +25°C, and also the change due to
temperature variation (ppm) from +25°C to +85°C.
Equations 4 and 7 will be used to calculate the answers.
Given, the contents of the registers:
AV = 1
n = 178 decimal
m = 74 decimal
Using Equation 2:
V OUT ( DC ) = ( A V • V REF • A REF )
178
= ⎛ 1 • 1.20 • ----------⎞
⎝
255⎠
= 0.8376V
Offset Setting: Using Equation 2 and targeting
VOUT = 3.0VDC:
Using Equation 5:
V OUT ( DC ) = ( A V • V REF • A REF ) = 3.00V
V REF = 1.20V
( 2 • 74 ) – 255
= 1 • – 2.1 • -----------------------------------255
A V • A REF = 2.50
V OUT ( T ) = ( A V • K • A TS ) mV ⁄ °C
= 0.8812mV ⁄ °C
Also, to solve for overall temp slope of the output:
Note that AREF varies from 0 to 1, so to get 2.40, AV = 4.
2.50
n
A ( REF ) = ----------- = 0.625 = ---------4
255
n = 159 decimal
= 9F hex
Temperature Slope Setting: Using Equation 5, which can
solve for Slope directly:
V OUT ( T ) = A V • K • A TS = – 2.8mV ⁄ °C
– 2.8
A TS = -------------------4 • – 2.1
6
0.8812mV ⁄ °C
--------------------------------------- • 10 = 1010ppm ⁄ °C
872.5mV
Note that Equation 1 can be used directly to solve for output
voltage at a given temperature, in this case +85°C:
⎧
n
( 2 • m ) – 255 ⎫
V OUT = A V • ⎨ V REF • ---------- + K ( T – T 0 ) -------------------------------- ⎬
255
255
⎩
⎭
1
V OUT ( +85°C ) =
⎧
178
⎩
( 2 • m ) – 255
A TS = 0.333 = ---------------------------------255
m = 170 decimal
= A9 hex
The ISL21400 device can be programmed with these
calculated parameters and perform temperature
compensation or direct control in the target circuit. If
parameters change for some reason, then the device can be
reprogrammed with new values and the circuit retested.
EXAMPLE 2. CALCULATING THE VOUT TEMPERATURE
SLOPE
In some applications, it may be desirable to calculate what
the output voltage and temp slope are, given the
programmed register settings. Such an application could be
a closed loop system with internal calibration procedure. By
reading the registers of the ISL21400, then calculating the
15
( 2 • 74 ) – 255 ⎫
- + ( – 0.0021 ) ( 85 – 25 ) ---------------------------------- ⎬
= • ⎨ 1.20 • --------255
255
⎭
= 0.8905V
Typical Applications Circuits
LDMOS RF Power Amplifier (RFPA). The ISL21400 is used
to set the gate bias for the LDMOS transistor in a single
stage of an RFPA. Normally this is done with a DAC or digital
potentiometer with some discrete temperature
compensation circuitry. The ISL21400 simplifies this control
and allows a full range of DC bias and tempco control.
A typical circuit can be calibrated for correct bias at room
temperature (+25°C) on power-up using a microcontroller or
direct I2C control. The temperature of the unit can then be
increased to the highest operating range, and the
Temperature Slope setting can then be adjusted to bring the
amplifier back to correct bias. Since the Temp Slope setting
has a negligible effect on the room temperature setting, the
amplifier will be biased correctly over the operating
temperature of the unit.
FN8091.3
March 31, 2011
ISL21400
+28V
U2
1
IN
OUT
3
2 GND
+28V
+5V REGULATOR
I2C BUS
5
6
1
2
3
SCL
SDA
A2
A1
A0
A2
VCC
VOUT
8
7
GND 4
R1
R2
1k
100
L1
C1
100pF
ISL21400
RF OUTPUT
C2
RF INPUT
Q1
LDMOS
FIGURE 19. LDMOS RFPA BIAS CONTROL
16
FN8091.3
March 31, 2011
ISL21400
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L
SEATING
PLANE
C
0.20 (0.008)
C
a
CL
E1
C D
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.026 BSC
0.65 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
0.20 (0.008)
MIN
A
L1
-A-
SIDE VIEW
SYMBOL
e
L1
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
α
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN8091.3
March 31, 2011