STMICROELECTRONICS M69KB096AA85AW8

M69KB096AA
64 Mbit (4M x16)
1.8V Supply, 80MHz Clock Rate, Burst PSRAM
FEATURES SUMMARY
■
■
■
■
■
SUPPLY VOLTAGE
– VCC = 1.7 to 1.95V core supply voltage
– VCCQ = 1.7 to 3.3V for I/O buffers
ASYNCHRONOUS MODES
– Asynchronous Random Read: 70ns and
85ns access time
– Asynchronous Write
– Asynchronous Page Read
Page Size: 16 words
Subsequent read within page: 20ns
SYNCHRONOUS BURST READ AND
WRITE MODES
– Burst Write in Continuous Mode
– Burst Read:
Fixed Length (4, 8, or 16 Words) or
Continuous mde
Maximum Clock Frequency: 66MHz,
80MHz
Burst initial latency: 50ns (4 clock cycles)
at 80MHz
Output delay: 9ns at 80MHz
BYTE CONTROL BY LB/UB
LOW POWER CONSUMPTION
– Asynchronous Random Read Mode:
< 25mA
– Asynchronus Page Read Mode
(subsequent read operations): < 15mA
– Synchronous Burst Read
Initial access: < 35mA
Continuous Burst Read: < 15mA
– Standby Current: 120µA
– Deep Power-Down Current: 10µA (typ)
Figure 1. Package
Wafer
■
■
LOW POWER FEATURES
– Temperature Compensated Refresh
(TCR)
– Partial Array Refresh (PAR)
– Deep Power-Down (DPD) Mode
OPERATING TEMPERATURE
– –30°C to +85°C
THE M69KB096AA IS ONLY AVAILABLE AS PART OF A MULTI-CHIP PACKAGE PRODUCT
January 2006
1/48
M69KB096AA
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Upper Byte Enable (UB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clock Input (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration Register Enable (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
VCCQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Asynchronous Random Read and Write Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Asynchronous Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Synchronous Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Mixed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Deep Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Programming and Reading the Configuration Registers using the CR Controlled Method . 13
Programming and Reading the Configuration Registers by the Software Method. . . . . . . . . 13
Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating Mode Bit (BCR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Latency Counter Bits (BCR13-BCR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
WAIT Polarity Bit (BCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
WAIT Configuration Bit (BCR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock Configuration Bit (BCR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Driver Strength Bit (BCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/48
M69KB096AA
Burst Wrap Bit (BCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Burst Length Bits (BCR2-BCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page Mode Operation Bit (RCR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Temperature Compensated Refresh Bits (RCR6-RCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Deep Power-Down Bit (RCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Partial Array Refresh Bits (RCR2-RCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3/48
M69KB096AA
SUMMARY DESCRIPTION
The M69KB096AA is a 64 Mbit (67,108,864 bit)
PSRAM, organized as 4,194,304 words by 16 bits.
The memory array is implemented using a one
transistor-per-cell topology, to achieve bigger array sizes.
This device is a high-speed CMOS, dynamic random-access memory. It provides a high-density
solution for low-power handheld applications.
The M69KB096AA includes the industry standard
Flash memory burst mode that dramatically increases read/write over that of other low-power
SRAM or PSRAMs.
The PSRAM interface supports both asynchronous and burst-mode transfers. Page mode accesses are also included as a bandwidthenhancing extension to the asynchronous read
protocol.
PSRAMs are based on the DRAM technology, but
have a transparent internal self-refresh mechanism that requires no additional support from the
system memory controller, and has no significant
impact on the device read/write performance.
The device has two configuration registers, accessible to the user to define the device operation: the
Bus Configuration Register (BCR) and the Refresh
Configuration Register (RCR). The Bus Configuration Register (BCR) indicates how the device interacts with the system memory bus. Overall, it is
identical to its counterpart in burst-mode Flash
memory devices. The Refresh Configuration Register (RCR) is used to control how the memory array refresh is performed. At power-up, these
registers are automatically loaded with default settings and can be updated any time during normal
operation.
To minimize the value of the standby current during self-refresh operations, the M69KB096AA includes three system-accessible mechanisms
configured via the Refresh Configuration Register
(RCR):
■
The Temperature Compensated Refresh
(TCR) is used to adjust the refresh rate
according to the operating temperature. The
refresh rate can be decreased at lower
temperatures to minimize current
consumption during standby.
■
The Partial Array Refresh (PAR) performs a
limited refresh of the part of the PSRAM array
that contains essential data.
■
The Deep Power-Down (DPD) mode
completely halts the refresh operation. It is
used when no essential data is being held in
the device.
4/48
Figure 2. Logic Diagram
VCC
VCCQ
22
16
A0-A21
DQ0-DQ15
W
WAIT
E
CR
G
M69KB096AA
UB
LB
K
L
VSS
VSSQ
AI10584b
Table 1. Signal Names
A0-A21
Address Inputs
DQ0-DQ15
Data Inputs/Outputs
E
Chip Enable Input
CR
Configuration Register Enable Input
G
Output Enable Input
W
Write Enable Input
UB
Upper Byte Enable Input
LB
Lower Byte Enable Input
K
Clock Input
L
Latch Enable Input
WAIT
Wait Output
VCC
Core Supply Voltage
VCCQ
Input/Output Buffers Supply Voltage
VSS
Ground
VSSQ
Input/Output Buffers Ground
M69KB096AA
SIGNAL DESCRIPTIONS
The signals are summarized in Figure 2., Logic Diagram, and Table 1., Signal Names.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access during Read and Write operations.
Data Inputs/Outputs (DQ8-DQ15). The Upper
Byte Data Inputs/Outputs carry the data to or from
the upper part of the selected address during a
Write or Read operation, when Upper Byte Enable
(UB) is driven Low. When disabled, the Data Inputs/Outputs are high impedance.
Data Inputs/Outputs (DQ0-DQ7). The
Lower
Byte Data Inputs/Outputs carry the data to or from
the lower part of the selected address during a
Write or Read operation, when Lower Byte Enable
(LB) is driven Low.
Chip Enable (E). Chip Enable, E, activates the
device when driven Low (asserted). When deasserted (VIH), the device is disabled and goes automatically in low-power Standby mode or Deep
Power-down mode.
Output Enable (G). Output Enable, G, provides a
high speed tri-state control, allowing fast read/
write cycles to be achieved with the common I/O
data bus.
Write Enable (W). Write Enable, W, controls the
Bus Write operation of the memory. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the
configuration registers or to the memory array.
Upper Byte Enable (UB). The Upper Byte Enable, UB, gates the data on the Upper Byte Data
Inputs/Outputs (DQ8-DQ15) to or from the upper
part of the selected address during a Write or
Read operation.
Lower Byte Enable (LB). The Lower Byte Enable, LB, gates the data on the Lower Byte Data
Inputs/Outputs (DQ0-DQ7) to or from the lower
part of the selected address during a Write or
Read operation.
If both LB and UB are disabled (High) during an
operation, the device will disable the data bus from
receiving or transmitting data. Although the device
will seem to be deselected, it remains in an active
mode as long as E remains Low.
Clock Input (K). The Clock, K, is an input signal
to synchronize the memory to the microcontroller
or system bus frequency during Synchronous
Burst Read and Write operations.
The Clock input is required during all synchronous
operations, except in Standby and Deep Power-
Down. It must be kept Low during asynchronous
operations.
Configuration Register Enable (CR). When this
signal is driven High, VIH, Write operations load either the value of the Refresh Configuration Register (RCR) or the Bus configuration register (BCR).
Latch Enable (L). The Latch Enable input is
used to latch the address. Once the first address
has been latched, the state of L controls whether
subsequent addresses come from the address
lines (L = VIL) or from the internal Burst counter (L
= VIH).
The Latch Enable signal, L, must be held Low, VIL,
during Asynchronous operations.
Wait (WAIT). The WAIT output signal provides
data-valid feedback during Synchronous Burst
Read and Write operations. The signal is gated by
E. Driving E High while WAIT is asserted may
cause data corruption.
Once a Read or Write operation has been initiated,
the WAIT signal goes active to indicate that the
M69KB096AA device requires additional time before data can be transferred.
The WAIT signal also is used for arbitration when
a Read or Write operation is launched while an onchip refresh is in progress (see Figure 6., Collision
Between Refresh and Read Operation and Figure
7., Collision between Refresh and Write Operation).
The WAIT signal on the M69KB096AA device is
typically connected to a shared system-level WAIT
signal. The shared WAIT signal is used by the processor to coordinate transactions with multiple
memories on the synchronous bus.
See the Operating Modes section for details on the
WAIT signal operation.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Write,
etc.) and for driving the refresh logic, even when
the device is not being accessed.
VCCQ Supply Voltage. VCCQ provides the power
supply for the I/O pins. This allows all Outputs to
be powered independently from the core power
supply, VCC.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
VSSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by VCCQ. VSSQ
must be connected to VSS.
5/48
M69KB096AA
Figure 3. Block Diagram
DQ7-DQ0
A21-A0
Address Decode
Logic
4,096K x 16
I/O
Buffers
MEMORY
ARRAY
Refresh Configuration
Register (RCR)
DQ15-DQ7
Bus Configuration
Register (BCR)
E
W
G
K
L
Control
Logic
CR
WAIT
LB
UB
AI08721c
Note: Functional block diagram illustrates simplified device operation.
6/48
M69KB096AA
Table 2. Bus Modes– Asynchronous Mode
MODE
POWER
K
L
E
G
W
CR
LB, UB
WAIT
DQ15-DQ0
(2)
(1)
Asynchronous
Read
Active >
Standby
L
L
L
L
H
L
L1
Low Z
Data-Out
3
Asynchronous
Write
Active >
Standby
L
L
L
X
L
L
L1
Low Z
Data-In
3
Standby
Standby
L
X
H
X
X
L
X
High Z
High-Z
4,5
Write
Configuration
Register
Active
L
L
L
H
L
H
X
Low Z
High-Z
Deep PowerDown (DPD)
Deep
PowerDown
L
X
H
X
X
X
X
High-Z
High-Z
6
NOTES
NOTES
Table 3. Bus Modes– Synchronous Burst Mode
MODE
POWER
K
L
E
G
W
CR
LB, UB
WAIT
DQ15-DQ0
(2)
(1)
Initial Burst
Read
Active >
Standby
!
L
L
X
H
L
L
Low Z
Data-Out
3, 7, 8
Initial Burst
Write
Active >
Standby
!
L
L
H
L
L
X
Low Z
Data-In
3, 7, 8
Subsequent
Burst
Operation
Active >
Standby
!
H
L
X
X
X
L
Low Z
Data-In or
Data-Out
3, 7, 8
Burst
Suspend
Active >
Standby
X(9)
X
L
H
X
L
X
Low Z
High-Z
3, 7
Write
Configuration
Register
Active
!
L
L
H
L
H
X
Low Z
High-Z
7, 8
Deep PowerDown (DPD)
Deep
PowerDown
L
X
H
X
X
X
X
High-Z
High-Z
6
Note: 1. When LB and UB are in select mode (Low), DQ15-DQ0 are affected. When only LB is in select mode, DQ7-DQ0 are affected. When
only UB is in the select mode, DQ15-DQ8 are affected.
2. The WAIT polarity is configured through the Bus Configuration Register (BCR10).
3. The device consumes active power in this mode whenever addresses are changed.
4. When the device is in Standby mode, Address inputs and Data inputs/outputs are internally isolated from any external influence.
5. VIN = VCC or 0V.
6. The device remains in Deep Power-Down mode until the RCR register is reconfigured.
7. The Synchronous Burst mode is initialized through the Bus Configuration Register (BCR15).
8. The clock polarity is configured through the Bus Configuration Register (BCR6).
9. The Clock signal, K, must remain stable during Burst Suspend operations.
7/48
M69KB096AA
OPERATING MODES
The M69KB096AA supports Asynchronous Random Read, Page Read and Synchronous Burst
Read and Write modes.
The device mode is defined by the value that has
been loaded into the Bus Configuration Register.
The Page mode is controlled by the Refresh Configuration Register (RCR7).
Power-Up
PSRAM devices include an on-chip voltage sensor used to launch the power-up sequence. VCC
and VCCQ must be applied simultaneously. Once
they reach a stable level, equal to or higher than
1.70V, the device will require tVCHEL to complete
its self-initialization process. During the initialization period, the E signal should remain High. Once
initialization has completed, the device is ready for
normal operation. Initialization will configure the
Bus Configuration Register (BCR) and the Refresh
Configuration Register (RCR) with their default
settings (see Table 5., page 16, and Table
9., Refresh Configuration Register Definition).
See Figure 34., Power-Up AC Waveforms and Table 19., Power-Up AC Characteristics, for details
on the Power-up timing.
Asynchronous Random Read and Write Modes
At power-up, the device is in Asynchronous Random Read mode. This mode uses the industry
standard control bus (E, G, W, LB, UB). Read operations are initiated by bringing E, G, and LB, UB
Low, VIL, while keeping W High, VIH. Valid data will
be gated through the output buffers after the specific access time tAVQV has elapsed.
The WAIT signal will remain active until valid data
is output from the device and its state should be ignored.
Write operations occur when E, W, LB and UB are
driven Low. During Asynchronous Random Write
operations, the G signal is “don't care” and W will
override G. The data to be written is latched on the
rising edge of E, W, LB or UB (whichever occurs
first). During Write operations, the WAIT signal indicates to the system memory controller that data
have been programmed into the memory.
During asynchronous operations (Page mode disabled), the L input can either be used to latch the
address or kept Low, VIL, during the entire Read/
Write operation. The Clock input signal K must be
held Low, VIL.
See Figures 15, 16 and Table 15. for details of
Asynchronous Read AC timing requirements.
See Figures 23, 24, 25, 26, and Table 17. for details of Asynchronous Write AC timing requirements.
8/48
Asynchronous Page Read Mode
The Asynchronous Page read mode gives greater
performance, even than the traditional Asynchronous Random Read mode. The page mode is not
available for write operations.
Asynchronous Page Read mode is enabled by
setting RCR7 to ‘1’. L must be driven Low, VIL, during all Asynchronous Page Read operations.
In Asynchronous Page Read mode, a Page of
data is internally read. Each memory page consists of 16 Words, and has the same set of values
on A4-A21; only of A0 to A3 differ. The first read
operation within the Page has the normal access
time (tAVQV), subsequent reads within the same
Page have much shorter access times (tAVQV1). If
the Page changes then the normal, longer timings
apply again.
During Asynchronous Page Read mode, the K input must be held Low, VIL. E must be kept Low, VIL
upon completion of an Asynchronous Page Read
operation. The WAIT signal remains active until
valid data is output from the device.
See Figure 17. and Table 15. for details of the
Asynchronous Page Read timing requirements.
Synchronous Burst Mode
Burst mode allows high-speed synchronous read
and write operations.
In Synchronous Burst mode, the data is input or
output to or from the memory array in bursts that
are synchronized with the clock. After E goes Low,
the data address is latched on the first rising edge
of the Clock, K. During this first clock rising edge,
the W signal indicates whether the operation is going to be a Read (W=VIH, Figure 4.) or Write
(W=VIL, Figure 5.).
In Synchronous Burst mode, the number of Words
to be input or output during a Synchronous Burst
operation can be configured in the Bus Configuration Register, BCR, as fixed length (4 Words, 8
Words or 16 Words) or Continuous. In Synchronous Continuous Burst mode, the entire memory
can be accessed sequentially in one Burst operation.
The Latency Counter, stored in the BCR11 to
BCR13 bits of the BCR register, defines how many
clock cycles elapse before the first data value is
transferred between the processor and the
M69KB096AA.
The WAIT output will be asserted as soon as a
Synchronous Burst operation is initiated and will
be deasserted to indicate when data is to be transferred into (or out of) the memory array. The WAIT
signal is also asserted when a Continuous Burst
Read or Write operation crosses a row boundary.
The WAIT assertion allows time for the new row to
M69KB096AA
be accessed. It also allows any pending refresh
operations to be performed (see Figure
22., Continuous Burst Read Showing an Output
Delay for End-of-Row Condition (BCR8=0,1)).
The processor can access other devices without
being submitted to the initial burst latency by suspending the burst operation. Burst operations can
be suspended by halting the Clock signal, holding
it High or Low. If another device needs to use the
data bus while Burst operations are suspended,
the Output Enable signal, G, should be driven
High, VIH, to disable data outputs; otherwise, G
can remain Low, VIL. The WAIT output will remain
asserted to prevent any other devices from using
the processor WAIT line.
Burst operations can be resumed by taking G Low,
VIL, and then restarting the Clock as soon as valid
data are available on the bus (see Figure
21., Synchronous Burst Read Suspend and Resume Waveforms).
Mixed Mode
When the BCR register is configured for synchronous operation, the device can support a combination of Synchronous Burst Read and
Asynchronous Random Write operations.
The Asynchronous Random Write operation requires that the Clock signal remains Low, VIL, during the entire sequence. The L signal can either be
used to latch the target address or remain Low,
VIL, during the entire Write operation. E must return Low, VIL, during Asynchronous and Burst operations. Note that the time, necessary to assure
adequate refresh, is the same value as that for
Asynchronous Read and Write mode.
Mixed-mode operation greatly simplifies the interfacing with traditional burst-mode Flash Memory
Controllers.
Low-Power Modes
Standby Mode. During Standby, the device current consumption is reduced to the level necessary to perform the memory array refresh
operation. Standby operation occurs when E is
High, VIH, and no transaction is in progress.
The device will enter Standby mode when a Read
or Write operation is completed, or when the address and control inputs remain stable for an extended period of time. This “active” Standby mode
will continue until address or control inputs
change.
Temperature Compensated Refresh. The
Temperature Compensated Refresh (TCR) is
used to adjust the refresh rate depending on the
device operating temperature.
The leakage current of DRAM capacitive storage
elements increases with the temperature. PSRAM
devices, based on a DRAM architecture, consequently require increasingly frequent refresh operations to maintain data integrity as the
temperature increases. At lower temperatures, the
refresh rate can be decreased to minimize the
standby current.
The TCR mechanism allows adequate refresh
rates to be set at four different temperature thresholds. These are defined by setting the RCR5 and
RCR6 bits of the Refresh Configuration Register,
RCR. To minimize the self refresh current consumption, the selected setting must be higher than
the operating temperature of the PSRAM device.
As an example, if the operating temperature is
+50°C, the +70°C setting must be selected; the
+15°C and +45°C settings would result in inadequate refreshing and could cause data corruption.
See Table 9. for the definition of the Refresh Configuration Register bits.
Partial Array Refresh. The Partial Array Refresh
(PAR) performs a limited refresh of part of the
PSRAM array. This mechanism enables the device to reduce the standby current by refreshing
only the part of the memory array that contains essential data. Different refresh options can be defined by setting the RCR0 to RCR2 bits of the RCR
Register:
■
Full array
■
One half of the array
■
One quarter of the array
■
One eighth of the array
■
None of the array.
These memory areas can be located either at the
top or bottom of the memory array.
The WAIT signal is used for arbitration when a
read/write operation is launched while an on-chip
refresh is in progress. If locations are addressed
while they are undergoing refresh, the WAIT signal
will be asserted for additional clock cycles, until
the refresh has completed (see Figure 6. and Figure 7., Collision between Refresh and Read or
Write Operations). When the refresh operation is
completed, the Read or Write operation will be allowed to continue normally.
9/48
M69KB096AA
Deep Power-Down Mode. Deep
power-down
(DPD) mode is used by the system memory controller to de-activate the PSRAM device when its
storage capabilities are not needed. All refresh-related operations are then disabled. When the
Deep Power-Down mode is enabled, the data
stored in the device become corrupted. When re-
fresh operations have been re-enabled, the device
will be available for normal operations after tVCHEL
(time to perform an initialization sequence). During
this delay, the current consumption will be higher
than the specified standby levels, but considerably
lower than the active current.
Figure 4. Synchronous Burst Read Mode
K
A0-A21
Address
Valid
ADV
Latency Code 2 (3 clocks)
E
G
W
WAIT
Hi Z
DQ0-DQ15
Hi Z
DQ0
DQ1
DQ2
DQ3
LB/UB
Burst Read Identified
(W = High)
AI06774b
Note: Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
10/48
M69KB096AA
Figure 5. Synchronous Burst Write Mode (4-word burst)
K
A0-A21
Address
Valid
L
E
G
W
LB/UB
WAIT
Hi Z
DQ0-DQ15
Hi Z
DQ0
DQ1
DQ2
DQ3
Additional WAIT states inserted
to allow Refresh completion
AI06776c
Note: Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
Figure 6. Collision Between Refresh and Read Operation
K
A0-A21
Address
Valid
L
E
G
W
LB/UB
WAIT
Hi Z
DQ0-DQ15
Hi Z
DQ0
Additional WAIT states inserted
to allow Refresh completion
DQ1
DQ2
DQ3
AI06776b
Note: Additional Wait states inserted to allow Refresh completion.
Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
11/48
M69KB096AA
Figure 7. Collision between Refresh and Write Operation
K
A0-A21
Address
Valid
L
E
G
W
LB/UB
WAIT
Hi Z
DQ0-DQ15
Hi Z
DQ0
Additional WAIT states inserted
to allow Refresh completion
DQ1
DQ2
DQ3
AI06777
Note: Additional Wait states inserted to allow Refresh completion.
Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
12/48
M69KB096AA
CONFIGURATION REGISTERS
Two write-only user-accessible configuration registers have been included to define device operation. These registers are automatically loaded with
default settings during power-up, and can be updated any time the device is operating in a standby
state.
The configuration registers (BCR and RCR) can
be programmed and read using two methods:
■
The CR Controlled Method (or Hardware
Method)
■
The Software Method.
Programming and Reading the Configuration
Registers using the CR Controlled Method
The BCR and the RCR can be programmed and
read using either a Synchronous or an Asynchronous Write and Read operation with the Configuration Register Enable input, CR, at VIH. Address
bit A19 selects the register to be programmed or
read (see Table 4., Register Selection). The values placed on address lines A0 to A21 are latched
into the register on the rising edge of L, E, or W,
whichever occurs first. LB and UB are “don’t care”.
When CR is at VIL, a Read or Write operation will
access the memory array.
See Figures 27 and 33, Configuration Register
Write in Asynchronous and Synchronous Modes.
Table 4. Register Selection
Register
Read or Write Operation
A19
RCR
Read/Write
0
BCR
Read/Write
1
Programming and Reading the Configuration
Registers by the Software Method
Each register can be read by issuing a Read Configuration Register sequence (see Figure 9., Read
Configuration Register (Software Method), and
programmed by issuing a Set Configuration Register sequence (see Figure 8., Set Configuration
Register (Software Method). Both sequences
must be issued in asynchronous mode.
The timings will be identical to those described in
Table 15., Asynchronous Read AC Characteristics. The Chip Enable input, CR, is ‘don’t care’.
Read Configuration Register and Set Configuration Register sequences both require 4 cycles:
■
2 bus read and one bus write cycles to a
unique address location, 3FFFFFh, indicate
that the next operation will read or write to a
configuration register. The data written during
the third cycle must be ‘0000h’ to access the
RCR and ‘0001h’ to access the BCR during
the next cycle.
■
The fourth cycle reads from or writes to the
configuration register.
13/48
M69KB096AA
Figure 8. Set Configuration Register (Software Method)
Addr.
3FFFFFh
3FFFFFh
3FFFFFh
3FFFFFh
(4)
E
tEHEL2
tEHEL2
Don't Care
Don't Care
tEHEL2
G
W
LB, UB
DQ0-DQ15
(2)
CR Data IN
AI10600b
Note: 1.
2.
3.
4.
Only the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified.
To program the BCR or the RCR on last bus write cycle, DQ0-DQ15 must be set to ‘0001h’ and ‘000h’ respectively.
The highest order address location is not modified during this operation.
The third write operation must be controlled by the Chip Enable signal.
Figure 9. Read Configuration Register (Software Method)
Addr.
3FFFFFh
3FFFFFh
3FFFFFh
3FFFFFh
(3)
E
tEHEL2
tEHEL2
Don't Care
Don't Care
tEHEL2
G
W
LB, UB
DQ0-DQ15
(1)
CR Data
OUT
AI10601b
Note: 1.
2.
3.
4.
14/48
To read the BCR, RCR on last bus read cycle, DQ0-DQ15 must be set to ‘0001h’, ‘000h’ respectively.
The highest order address location is not modified during this operation.
The Chip Enable signal, E, must be held High for 150ns before reading the content of the Configuration Register.
The third write operation must be controlled by the Chip Enable signal.
M69KB096AA
Bus Configuration Register
The Bus Configuration Register (BCR) defines
how the PSRAM interacts with the system memory
bus. Overall, it is identical to its counterpart on
burst mode Flash devices.
At power-up, BCR is initialized to 9D4Fh.
Refer to Table 5. for the description of the Bus
Configuration Register Bits.
Operating Mode Bit (BCR15). The
Operating
Mode bit allows the Synchronous Burst mode or
the Asynchronous mode (default setting) to be selected.
Latency Counter Bits (BCR13-BCR11). The
Latency Counter bits are used to set the number of
clock cycles between the beginning of a Read or
Write operation and the first data becoming available. For correct operation, the number of clock
cycles can only be equal to 3 or 4 (default settings)
and the Latency Counter bits can only assume the
values shown in Table 5., Bus Configuration Register Definition. See also Table 7., Latency
Counter Configuration, and Figure 12., Example
of Latency Counter Configuration).
WAIT Polarity Bit (BCR10). The WAIT Polarity
bit indicates whether the WAIT output signal is active High or Low. As a consequence, it also determines whether the WAIT signal requires a pull-up
or pull-down resistor to maintain the de-asserted
state.
By default, the WAIT output signal is active High.
WAIT Configuration Bit (BCR8). The
system
memory controller uses the WAIT signal to control
data transfer during Synchronous Burst Read
Read and Write operations.
The WAIT Configuration bit is used to determine
when the transition of the WAIT output signal between the asserted and the deasserted state occurs with respect to valid data available on the
data bus.
When the Wait Configuration bit is set to ‘0’, data
is valid or invalid on the first Clock rising edge immediately after the WAIT signal transition to the
deasserted or asserted state.
When the Wait Configuration bit is set to ‘1’ (default settings), the WAIT signal transition occurs
one clock cycle prior to the data bus going valid or
invalid.
See Figure 10., WAIT Configuration Example, and
Figure 11., Example of WAIT Configuration During
Synchronous Burst Operation.
Clock Configuration Bit (BCR6). The
Clock
Configuration bit is used to configure the activeedge of the Clock signal, K, during Synchronous
Burst Read or Write operations. When the Clock
Configuration bit is set to ’1’ (default setting), the
rising edge of the Clock is active. Configuring the
active clock edge to the falling edge (BCR6 set to
‘0’) is not supported.
All of the waveforms shown in this datasheet correspond to a Clock signal active on the rising
edge.
Driver Strength Bit (BCR5). The Driver Strength
bit allows to set the output drive strength to adjust
to different data bus loading. Normal driver
strength (full drive) and reduced driver strength (a
quarter drive) are available.
By default, outputs are configured at ‘half drive”
strength.
Burst Wrap Bit (BCR3). The burst reads can be
confined inside the 4, 8 or 16 Word boundary
(wrap) or allowed to step across the boundary (no
wrap). The Burst Wrap bit is used to select between ‘wrap’ and ‘no wrap’. If the Burst Wrap bit is
set to ‘1’ (no wrap), the device outputs data sequentially regardless of burst boundaries. When
Continuous Burst operation is selected, the internal address switches to 000000h if the read address passes the last address. By default, Burst
wrap is selected.
See also Table 6., Burst Type Definition.
15/48
M69KB096AA
Burst Length Bits (BCR2-BCR0). The
Burst
Length bits set the number of Words to be output
during a Synchronous Burst Read operation. They
can be set for 4 Words, 8 Words, 16 Words or
Continuous Burst (default settings), where all the
Words are read sequentially regardless of address
boundaries. Burst Write operations are always
performed using the Continuous Burst mode.
Table 5. Bus Configuration Register Definition
Address
Bits
Bus
Configuration
Register Bit
Description
A21-A20
-
-
A19
-
Register Select
A18-A16
-
-
A15
BCR15
Operating Mode
Bit
A14
-
-
A13-A11
BCR13BCR11
Latency Counter
Bits (LC)
Value
Description
Must be set to ‘0’ Reserved
0
Refresh Selected
1
Bus Configuration Register Selected
Must be set to ‘0’ Reserved
0
Synchronous Burst mode
1
Asynchronous mode (default)
Must be set to ‘0’ Reserved
010
LC = 2 (3 Clock Cycles)
011
LC= 3 (4 Clock Cycles) (default)
Other configurations reserved
A10
BCR10
0
WAIT Active Low
1
WAIT Active High (default)
WAIT Polarity Bit
A9
-
-
A8
BCR8
Wait
Configuration Bit
Must be set to ‘0’ Reserved
0
WAIT Asserted During Delay
1
WAIT Asserted One Clock Cycle Before Delay
(Default)
A7
-
-
Not supported
BCR6
Clock
Configuration Bit
0
A6
1
Rising Clock Edge (Default)
Driver Strength
Bit
0
Full Drive (default)
1
1/4 Drive
A5
BCR5
A4
-
-
A3
BCR3
Burst Wrap Bit
A2-A0
BCR2-BCR0
Must be set to ‘0’ Reserved
Must be set to ‘0’ Reserved
0
Wrap (default)
1
No Wrap
001
4 Words
010
8 Words
011
16 Words
111
Continuous Burst (default)
Burst Length Bit
Note: All Burst Write operations are performed in Synchronous Continuous Burst mode.
16/48
M69KB096AA
Wrap (BCR3=’0’)
Mode
Table 6. Burst Type Definition
Start 4 Words
Add (Sequential)
16 Words
(Sequential)
Continuous Burst
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6...
1
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
1-2-3-4-5-6-7...
2
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
2-3-4-5-6-7-8...
3
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
3-4-5-6-7-8-9...
4
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
4-5-6-7-8-9-10...
5
5-6-7-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
5-6-7-8-9-10-11...
6
6-7-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
6-7-8-9-10-11-12...
7
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9-10-11-12-13...
...
...
...
14
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
14-15-16-17-18-19-20...
15
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-16-17-18-19-20-21...
...
No Wrap (BCR3=’1’)
8 Words
(Sequential)
...
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
2
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
3
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
4
4-5-6-7-8-9-10-11
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
5
5-6-7-8-9-10-11-12
5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20
6
6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21
7
7-8-9-10-11-12-1314
...
Same as for Wrap
(Wrap /No Wrap
has no effect on
Continuous Burst)
7-8-9-10-11-12-13-14-...-17-18-19-20-21-22
...
14
14-15-16-17-18-19...-23-24-25-26-27-28-29
15
15-16-17-18-19-20...-24-25-26-27-28-29-30
Table 7. Latency Counter Configuration
Maximum Input Clock Frequency
Latency
Configuration Code
Access Time 70ns
Maximum Clock Rate in Burst Mode
80MHz
Maximum Clock Rate in Burst Mode
66MHz
Unit
2 (3 Clock Cycles)
53 (18.75ns)
44 (22.7ns)(1)
MHz
3 (4 Clock Cycles)
80 (12.5ns)
66 (15.2ns)
MHz
Note: 1. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
17/48
M69KB096AA
Figure 10. WAIT Configuration Example
K
WAIT
DQ0-DQ15
BCR8='0'
Data Valid During Current Cycle
Hi-Z
DQ0-DQ15
BCR8='1'
Data Valid During Next Cycle
Hi-Z
Data[0] Data[1]
Data[0]
AI06795
Figure 11. Example of WAIT Configuration During Synchronous Burst Operation
K
WAIT
BCR8='0'
Data Valid During Current Cycle
WAIT
BCR8='1'
Data Valid During Next Cycle
Hi-Z
DQ0-DQ15
Data[0]
Data[1]
Data[2] Data[3]
Data[4]
AI06797
Figure 12. Example of Latency Counter Configuration
K
A0-A21
ADDRESS
VALID
L
3 Clock Cycle Latency
VALID
OUTPUT
DQ0-DQ15
BCR13-BCR11='010'
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
4 Clock Cycle Latency
DQ0-DQ15
BCR13-BCR11='011'
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
AI08900
18/48
M69KB096AA
Refresh Configuration Register
The Refresh Configuration Register (RCR) is used
for two purposes:
■
to define how the self refresh of the PSRAM
array is performed
■
to enable Page Read operations.
Altering the self refresh parameters can dramatically reduce current consumption in Standby
mode.
At power-up, RCR is initialized to 0070h.
Refer to Table 9. for the description of the Refresh
Configuration Register Bits.
Page Mode Operation Bit (RCR7). The
Page
Mode operation bit determines whether the Asynchronous Page Read mode is enabled. At powerup, the RCR7 bit is set to ‘0’, and so the Asynchronous Page Read mode is disabled.
Temperature Compensated Refresh Bits
(RCR6-RCR5). The Temperature Compensated
Refresh bits allow an adequate refresh rate to be
selected at one of four different temperature
thresholds: +15°C, +45°C, +70°C, and +85°C. The
default setting is +85°C. See the Temperature
Compensated Refresh section for more details.
Deep Power-Down Bit (RCR4). The Deep Power-Down bit enables or disables all refresh-related
operations. The Deep Power-Down mode is enabled when the RCR4 bit is set to ‘0’, and remains
enabled until this bit is set to ‘1’. At power-up, the
Deep Power-Down mode is disabled.
See the Deep Power-Down section for more details.
Partial Array Refresh Bits (RCR2-RCR0). The
Partial Array Refresh bits allow refresh operations
to be restricted to a portion of the total PSRAM array. The refresh options can be full array, one
eighth, one quarter, one half, or none of the array.
These memory areas can be located either at the
top or bottom of the memory array. By default, the
full memory array is refreshed (see Table
8., Address Patterns for Partial Array Refresh).
Table 8. Address Patterns for Partial Array Refresh
RCR2 RCR1 RCR0
Refreshed Area
Address Space
Size of
Refreshe
d Area
Density
0
0
0
Full Array (Default)
000000h-3FFFFFh 4 Mbitsx16 64 Mbits
0
0
1
Bottom Half of the Array
000000h-1FFFFFh 2 Mbitsx16 32 Mbits
0
1
0
Bottom First Quarter of the Array
000000h-0FFFFFh 1 Mbitsx16 16 Mbits
0
1
1
Bottom First Eighth of the Array
000000h-07FFFFh
512Kbitsx
16
8 Mbits
1
0
0
None of the Array
0
0
0
1
0
1
Top Half of the Array
200000h-3FFFFFh 2 Mbitsx16 32 Mbits
1
1
0
Top Quarter of the Array
300000h-3FFFFFh 1 Mbitsx16 16 Mbits
1
1
1
Top One-Eighth of the Array
380000h-3FFFFFh
512Kbitsx
16
8 Mbits
Note: RCR4 is set to ‘1’.
19/48
M69KB096AA
Table 9. Refresh Configuration Register Definition
Address
Bits
Bus
Configuration
Register Bit
Description
A21-A20
-
-
A19
-
Register Select
A18-A8
-
-
A7
RCR7
Page Mode
Operation Bit
A6-A5
A4
A3
RCR6-RCR5
RCR4
-
Temperature
Compensated
Refresh Bits
Deep PowerDown Bit
-
Value
Description
Must be set to ‘0’ Reserved
0
Refresh Selected
1
Bus Configuration Register Selected
Must be set to ‘0’ Reserved
0
Page Read Mode Disabled (Default)
1
Page Read Mode Enabled
11
+85°C (Default)
00
+70°C
01
+45°C
10
+15°C
0
Deep Power-Down Enabled
1
Deep Power-Down Disabled (Default)
Must be set to ‘0’ Reserved
000
001
010
A2-A0
RCR2-RCR0
Partial Array
Refresh Bits
011
100
101
110
111
20/48
See Table 8., Address Patterns for Partial
Array Refresh
M69KB096AA
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 10. Absolute Maximum Ratings
Symbol
Min
Max
Unit
Ambient Operating Temperature
–30
85
°C
TSTG
Storage Temperature
–55
150
°C
VCC
Core Supply Voltage
–0.2
2.45
V
Input/Output Buffer Supply Voltage
–0.2
4.0
V
Input or Output Voltage
–0.5
4.0 or
VCCQ+0.3
V
TA
VCCQ
VIO
Parameter
(1)
Note: 1. Whichever is the lower.
21/48
M69KB096AA
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 11., Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when relying on the quoted parameters.
Table 11. Operating and AC Measurement Conditions
M69KB096AA
Unit
Parameter
Min
Max
VCC Supply Voltage
1.7
1.95
V
VCCQ Input/Output Buffer Supply Voltage
1.7
3.3
V
Ambient Operating Temperature
–30
85
°C
Load Capacitance (CL)
Output Circuit Protection Resistance (R1, R2)
30
pF
VCCQ = 1.8V
2.7
kΩ
VCCQ = 2.5V
3.7
kΩ
VCCQ = 3.0V
4.5
kΩ
Input Pulse Voltages
VCC
0
V
Input and Output Timing Ref. Voltages
VCC/2
V
Output Transition Timing Ref. Voltages
VRL = 0.3VCC; VRH = 0.7VCC
V
Input Rise and Fall Time (tτ )
1.6
ns
Note: 1. All voltages are referenced to VSS.
Figure 13. AC Measurement I/O Waveform
Figure 14. AC Measurement Load Circuit
VCCQ
I/O Timing Reference Voltage
R1
VCC
VCC/2
DEVICE
UNDER
TEST
0V
Output Timing Reference Voltage
VCC
0V
OUT
CL
R2
0.7VCC
0.3VCC
AI04831
AI07222d
Note: 1. Logic states ‘1’ and ‘0’ correspond to AC test inputs driven at VCCQ and VSS respectively. Input timings begin at VCCQ/2 and
output timings end at VCCQ/2. Input rise and fall time (10% to 90%) are lower than 1.6ns.
2. All the tests are performed with the outputs configured as Full drive strength (BCR[5]=0).
22/48
M69KB096AA
Table 12. Capacitance
Symbol
Test
Condition
Parameter
Min
Max
Unit
CIN1
Address Input Capacitance
VIN = 0V
6
pF
CIO
Data Input/Output Capacitance
VIO = 0V
6
pF
Note: 1. These parameters are not fully tested.
Table 13. DC Characteristics
Symbol
Parameter
ICC1 (1)
Operating Current:
Asynchronous Random
Read/Write
ICC1P (1)
Operating Current:
Asynchronous Page
Read
Test Condition
VIN =VIH or VIL,
E = VIL,
IOUT = 0mA
Min.
Typ
Max.
Unit
70ns
25
mA
85ns
20
mA
70ns
15
mA
85ns
12
mA
80MHz
35
mA
66MHz
30
mA
ICC2 (1)
Operating Current:
Initial Access,
Burst Read/Write
ICC3R(1)
Operating Current:
Continuous Burst Read
80MHz
18
mA
66MHz
15
mA
ICC3W(1)
Operating Current:
Continuous Burst Write
80MHz
35
mA
66MHz
30
mA
ISB(2)
VCC Standby Current
VIN = VCCQ or 0V,
E = VIH
120
µA
ILI
Input Leakage Current
0V ≤VIN ≤VCC
1
µA
ILO
Output Leakage Current
G = VIH or E = VIH
1
µA
IZZ(3)
Deep-Power Down
Current
VIH
Input High Voltage
1.4
VCCQ + 0.2
V
VIL
Input Low Voltage
–0.2
0.4
V
VOH
Output High Voltage
IOH = –0.2mA
VOL
Output Low Voltage
IOL = 0.2mA
10
VIN = VIH or VIL
µA
0.8VCCQ
V
0.2VCCQ
V
Note: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to
drive the output capacitance expected in the actual system.
2. ISB(Max) values are measured with RCR2 to RCR0 bits set to ‘000’ (full array refresh) and RCR6 to RCR5 bits set to ‘11’ (temperature compensated refresh threshold at +85°C). In order to achieve low standby current, all inputs must be driven either to VCCQ
or VSS. ISB may be slightly higher for up to 500 ms after power-up or when entering Standby mode.
3. The Operating Temperature is +25°C.
23/48
M69KB096AA
Table 14. PAR and TCSR Specifications and Conditions
Symbol
ISB
(1)
Parameter
Test
Condition
Maximum
VIN = VIH or
Standby Current
VIL,
in TCSR and
E = VIH
PAR Modes
Maximum Operating Temperature(2)
Refreshed
Unit
Memory
+15°C
+45°C
+70°C
+85°C
Areas
RCR[6-5]=10 RCR[6-5]=01 RCR[6-5]=00 RCR[6-5]=11
Full
70
85
105
120
1/2
65
80
100
115
1/4
60
75
95
110
1/8
57
70
90
105
0
50
55
60
70
µA
Note: 1. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB may be slightly higher for up to 500 ms
after power-up or when entering Standby mode.
2. RCR values for 85°C are 100 percent tested. TCR values for 15°C, 45°C and 70°C are sampled only.
Figure 15. Asynchronous Random Read AC Waveforms
tAVAX
A0-A21
VALID ADDRESS
tAVQV
L
tEHEL
tEHQZ
E
tELQV
tBHQZ
LB/UB
tBLQV
tGHQZ
G
tGHQX
tGLQV
W
DQ0-DQ15
Hi-Z
tGLQX
tBLQX
tELQX
tELTV
WAIT
Hi-Z
VALID
OUTPUT
Hi-Z
tEHTZ
Hi-Z
AI06780b
24/48
M69KB096AA
Figure 16. L Controlled Asynchronous Random Read AC Waveforms
A0-A21
VALID
ADDRESS
tAVQV
tAVLH
tLHAX
tLHLL
L
tLLQV
tLLLH
tEHEL
tELLH
tEHQZ
tELQV
tBHQZ
E
LB/UB
tGHQZ
tBLQV
G
tGHQX
tGLQV
W
DQ0-DQ15
Hi-Z
tGLQX
tBLQX
tELQX
tELTV
WAIT
Hi-Z
VALID
OUTPUT
Hi-Z
tEHTZ
Hi-Z
AI06781b
25/48
M69KB096AA
Figure 17. Asynchronous Page Read AC Waveforms
tAVAX
VALID ADDRESS
A4-A21
A1-A3
VALID ADDRESS
VALID
VALID
VALID
tAVAV
tAVQV
L
tEHEL
tEHEL
tEHQZ
E
tELQV
tBHQZ
LB/UB
tBLQV
tGHQZ
G
tGHQX
tGLQV
W
tAVQV1
tGLQX
tBLQX
DQ0-DQ15
Hi-Z
tAVQX
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Hi-Z
tELQX
WAIT
tELTV
Hi-Z
tEHTZ
Hi-Z
AI06782b
26/48
M69KB096AA
Table 15. Asynchronous Read AC Characteristics
M69KB096AA
Symbol
Alt.
Parameter
70ns
Min
tAVQV
tAA
tLLQV
tAADV
tAVQV1
85ns
Max
Min
Unit
Max
Address Valid to Output Valid
70
85
ns
L Low to Output Valid
70
85
ns
tAPA
Page Access Time
20
25
ns
tLHAX
tAVH
L High to Address Transition
5
5
tAVLH
tAVS
Address Valid to L High
10
10
tBLQV
tBA
Upper/Lower Byte Enable Low to Output
Valid
70
85
ns
tBHQZ(4)
tBHZ
Upper/Lower Byte Enable High to Output HiZ
8
8
ns
tBLQX(3)
tBLZ
Upper/Lower Byte Enable Low to Output
Transition
10
10
ns
tEHEL
tCBPH
Chip Enable High between Subsequent
Mixed-Mode Read Operations
5
5
ns
tELEH(2)
tCEM
Maximum Chip Enable Pulse Width
tELTV
tCEW
Chip Enable Low to WAIT Valid
tEHTZ
8
1
7.5
1
8
µs
7.5
ns
Chip Enable high to WAIT High-Z
8
8
ns
70
85
ns
tELQV
tCO
Chip Enable Low to Output Valid (Chip
Select Access Time)
tELLH
tCVS
Chip Enable Low to L High
tEHQZ(4)
tHZ
Chip Enable High to Output Hi-Z
tELQX(3)
tLZ
Chip Enable Low to Output Transition
tGLQV
tOE
Output Enable Low to Output Valid
tGHQX
tOH
Output Enable High to Output Transition
5
5
ns
tAVQX
tOHA
Data Hold from Address Change
5
5
ns
tGHQZ(4)
tOHZ
Output Enable High to Output Hi-Z
tGLQX(3)
tOLZ
Output Enable Low to Output Transition
5
5
tAVAV
tPC
Page Cycle Time
20
25
tAVAX
tRC
Read Cycle Time
70
85
ns
tLLLH
tVP
L Pulse Width Low
10
10
ns
tLHLL
tVPH
L Pulse Width High
10
10
ns
10
10
8
10
ns
8
10
20
ns
20
8
ns
8
ns
ns
ns
Note: 1. All the tests are performed with the outputs configured in “Full drive” strength (BCR5=’0’).
2. The timing is related to Asynchronous Page mode only.
3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The transition timings measure a
transition of 100mV between the High-Z level (VCCQ/2) and VOH or VOL.
4. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The High-Z timings measure a
transition of 100mV between VOH or VOL and VCCQ/2.
27/48
M69KB096AA
Figure 18. Single Access Synchronous Burst Read AC Waveforms
tKHKH
tKHKL
K
tAVKH
tKHAX
ADDRESS
VALID
A0-A21
tAVLH
L
tLLKH
tKHLH
tKHEH
tEHQZ
tKHQV1
tELKH
E
tGHQZ
tGLQV
G
W
tWHKH
tKHWX
tBLKH
tKHBX
tGLQX
LB/UB
WAIT
Hi Z
tELTV
tKHTV
Hi Z
tKHQV2
DQ0-DQ15
Hi-Z
tKHQX2
VALID
OUTPUT
Burst Read Identified
(W = High)
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay.
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
28/48
Hi-Z
AI06783
M69KB096AA
Figure 19. Synchronous Burst Read (4-word) AC Waveforms
tKHKH
tKHKL
K
tAVKH
tKHAX
VALID
ADDRESS
A0-A21
tAVLH
tLLKH
tKHLH
L
tKHEH
tELKH
tKHQV1
tEHEL
E
tEHQZ
tGLQV
G
tWHKH
tKHWX
tGHQZ
tGLQX
W
tBLKH
tKHBX
LB/UB
tKHTX
tELTV
WAIT
Hi-Z
Hi-Z
tKHQZ
D0-D15
Hi-Z
tKHQX2
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
READ Burst Identified
(W = High)
AI06784
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay.
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
29/48
M69KB096AA
Figure 20. LB/UB Controlled, Synchronous Burst Read (4-word) AC Waveforms
tKHKH
tKHKL
K
tAVKH
tKHAX
VALID
ADDRESS
A0-A21
tAVLH
tKHLH
tLLKH
L
tELKH
tKHEH
tKHQV1
tEHEL
E
tEHQZ
tGLQV
G
tWHKH tKHWX
tGHQZ
tGLQX
W
tBLKH tKHBX
LB/UB
tELTV
WAIT
tKHTX
Hi-Z
Hi-Z
tKHQZ
DQ0-DQ15
Hi-Z
tKHQX2
VALID
OUTPUT
tKHQZ
VALID
OUTPUT
tKHQX1
Hi-Z
tKHQZ
VALID
OUTPUT
READ Burst Identified
(W = High)
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay.
2. The Burst Length bits BCR0 to BR2 are set to ‘001’ (4 Words).
3. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
30/48
AI06785
M69KB096AA
Figure 21. Synchronous Burst Read Suspend and Resume Waveforms
tKLKL
tAVKH
tKHKL
tKHAX
Valid
Address
0-A21
Valid
Address
tLLKH
tAVLH
tKH
L
tLLKH
tKHLH
tEHQZ
tELKH
tEHEL
tGHQZ
tWHKH
tGHQZ
tGLQV
tGLQX
tKHWX
W
tBLKH
tKHBX
tGLQX
B/UB
tGLQV
WAIT
0-D15
Hi-Z
Hi-Z
Hi-Z
Valid
Output
tKHQV1
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
tKHQX2
AI08760c
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay.
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
31/48
M69KB096AA
Figure 22. Continuous Burst Read Showing an Output Delay for End-of-Row Condition (BCR8=0,1)
tKLKH
K
tKHKH
A0-A21
tF
DON'T CARE
DON'T CARE
L
LB/UB
(4)
E
G
W
DON'T CARE
DON'T CARE
tKHTV
tKHTX
WAIT
DQ0-DQ15
(3)
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tKHQV2
VALID
OUTPUT
tKHQX2
WAIT CONFIGIGURED WITH BCR8 = '0'
WAIT CONFIGIGURED WITH BCR8 = '1'
AI06787b
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low, WAIT asserted during delay; Burst Wrap bit BCR3 set
to ‘0’ (wrap).
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
3. WAIT will be asserted for a maximum of 2xLC Cycles (LC being the Latency code set through BCR[13-11]).
4. E must not remain Low longer that tELEH.
32/48
M69KB096AA
Table 16. Synchronous Burst Read AC Characteristics
M69KB096AA
Symbol
Alt.
Parameter
80MHz
Min
tKHQV1
tABA
Burst Access Time
tKHQV2
tACLK
Delay From Clock High to Output Valid
tAVLH
tAVS
Address Valid to L High
tGLQV
tBOE
Delay From Output Enable Low to Output Valid in Burst mode
tEHEL(5)
tCBPH
Chip Enable High between Subsequent Mixed-Mode Read
Operations
5
tELTV
1
Max
66MHz
Min
Unit
Max
46.5
56
ns
9
11
ns
10
10
20
ns
20
5
ns
ns
tCEW
Chip Enable Low to WAIT Valid
(5)
tCEM
Maximum Chip Enable Low Pulse
tKHKH(4)
tCLK
Clock Period
12.5
20
tELKH
tCSP
Chip Enable Low to Clock High
4.5
20
tKHAX
tKHBX
tKHWX
tKHEH
tKHLH
tHD
Hold Time From Active Clock Edge
tEHQZ(2)
tHZ
Chip Enable High to Output Hi-Z
tR
tF
tKHKL
Clock Rise Time
Clock Fall Time
tKHTV
tKHTX
tKHTL
Clock High to WAIT Valid
Clock High to WAIT Transition
tKHQZ
tKHZ
Clock High to Output Hi-Z
3
8
tKHQX1
tKLZ
Clock High to Output Transition
2
5
tKHQX2
tKOH
Output Hold from Clock High
2
2
ns
tKHKL
tKLKH
tKP
Clock High to Clock Low
Clock Low to Clock High
4
5
ns
tGHQZ(2)
tOHZ
Output Enable High to Output Hi-Z
tGLQX(3)
tOLZ
Output Enable Low to Output Transition
5
5
ns
tAVKH
tLLKH
tBLKH
tWHKH
tCHKH
tSP
Set-up Time to Active Clock Edge
3
3
ns
tELEH
7.5
1
7.5
ns
8
ns
15
20
ns
5
20
ns
8
2
2
ns
8
8
ns
1.8
2.0
ns
9
11
ns
3
8
ns
2
5
ns
8
8
ns
Note: 1. All the tests are performed with the outputs configured in “Full drive” strength (BCR5=’0’).
2. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The High-Z timings measure a
transition of 100mV between VOH or VOL and VCCQ/2.
3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The transition timings measure a
transition of 100mV between the High-Z level (VCCQ/2) and VOH or VOL.
4. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
5. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every tELEH. A refresh opportunity is
satisfied by either of the following two conditions: E = VIH during Clock input K rising edge or E = VIH for longer than 15ns.
33/48
M69KB096AA
Figure 23. Chip Enable Controlled, Asynchronous Write AC Waveforms
tAVAX
A0-A21
VALID ADDRESS
tAVWH
tWHAX
L
tELEH,
tELWH
tAVEL
E
tBLBH
LB/UB
G
tWHWL
tWLWH
W
tDVEH tEHDX
DQ0-DQ15
Hi-Z
VALID INPUT
tELTV
WAIT
tEHTZ
Hi-Z
Hi-Z
AI06788c
Figure 24. LB/UB Controlled, Asynchronous Write AC Waveforms
tAVAX
A0-A21
VALID ADDRESS
tAVWH
tWHAX
L
tELEH, tELWH
E
tBLBH
LB/UB
G
tWHWL
tWLWH
W
tDVEH
DQ0-DQ15
Hi-Z
tELTV
WAIT
Hi-Z
tEHDX
VALID INPUT
tBHTZ
Hi-Z
AI06789d
34/48
M69KB096AA
Figure 25. Write Enable Controlled, Asynchronous Write AC Waveforms
tAVAX
A0-A21
VALID ADDRESS
tWHAX
tAVWH
L
tELEH, tELWH
E
tBLBH
LB/UB
G
tWLWH
tWHWL
W
tAVWL
DQ0-DQ15
Hi-Z
tELTV
WAIT
Hi-Z
tDVEH
tEHDX
VALID INPUT
tWHTZ
Hi-Z
AI06790c
35/48
M69KB096AA
Figure 26. L Controlled, Asynchronous Write AC Waveforms
A0-A21
VALID ADDRESS
tAVLH
tLHAX
tLLWH
tLHLL
tLLLH
L
tAVWH
tELEH, tELWH
E
tBLBH
LB/UB
G
tWLWH
tWHWL
W
tDVEH
DQ0-DQ15
Hi-Z
tELTV
WAIT
36/48
Hi-Z
tEHDX
VALID INPUT
tWHTZ
Hi-Z
AI06791c
M69KB096AA
Figure 27. Configuration Register Write in Asynchronous Mode Followed by Read Operation
K
A0-A21
except A19
ADDRESS
OPCODE
tAVLH
Select Control Register
ADDRESS
A19
CR
tAVLH
tLHLL
L
tEHEL
tLLVH
E
G
Initiate Control Register Access
tELWH
tWLWH
Write Address Bus Value
to Control Register
W
LB/UB
DQ0-DQ15
DATA VALID
AI06778
Note: 1. Non default BCR Register settings: Latency code two (three clocks); WAIT active Low; Hold data one clock; WAIT asserted during
delay.
2. A19 = VIL to load RCR; A19 = VIH to load BCR.
37/48
M69KB096AA
AI11317
tKHQX2
tKHQZ
tKHBX
tKHWX
tKHQV1
tDVWH
tWHDX
VALID
OUTPUT
D0-D15
WAIT
W
LB/UB
tBLLH
tWLDV
Hi-Z
VALID
OUTPUT
tBLWH
tWLWH
G
E
L
tAVWL
tELWH
tLLWL
tLLWH
tLLLH
tAVWH
tLHLL
tWHWL
tEHEL
(2)
tELTV
tBLKH
tWHKH
tELKH
tWHAX
tLHAX
VALID
ADDRESS
VALID
ADDRESS
A0-A21
K
tAVLH
tAVAX
tAVAX
tAVKH
tLLKH
VALID
ADDRESS
tKHLH
tKHAX
tKHKH
tGLQV
VALID
OUTPUT
VALID
OUTPUT
tKHKL
VALID
OUTPUT
VALID
OUTPUT
Hi-Z
tGHQZ
Figure 28. Asynchronous Write Followed by Synchronous Burst Read (4-word) AC Waveforms
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay.
2. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every tELEH. A refresh opportunity is
satisfied by either of the following two conditions: E = VIH during Clock input K rising edge or E = VIH for longer than 15ns.
3. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
38/48
M69KB096AA
AI11318
tEHDX
tDVEH
tBLBH
tWLWH
tKHQV2
VALID
OUTPUT
tKHQX2
tELTV
tKHTV
tGHQZ
tGLQX
tGLQV
tKHEH
Hi-Z
DQ0-DQ15
WAIT
Hi Z
LB/UB
W
tBLKH
tWHKH
G
E
tELKH
Burst Read Identified
(W = High)
tELTV
tKHBX
tKHWX
tKHLH
tLLKH
L
A0-A21
K
tKHQV1
tLHLL
ADDRESS
VALID
tKHAX
tAVKH
tKHKH
(1)
tEHEL
tEHQZ
tAVWL
tELWL
tELEH, tELWH
tLLWH
tLLLH
VALID ADDRESS
tAVLH
tWHTZ
VALID INPUT
Hi-Z
tLHAX
tWHWL
Figure 29. Synchronous Burst Read (4-word) Followed by Asynchronous Write AC Waveforms
Note: 1. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every tELEH. A refresh opportunity is
satisfied by either of the following two conditions: E = VIH during Clock input K rising edge or E = VIH for longer than 15ns.
39/48
M69KB096AA
Table 17. Asynchronous Write AC Characteristics
M69KB096AA
Symbol
Alt.
Parameter
70ns
Min
85ns
Max
Min
Unit
Max
tAVEL
tAVWL
tAVBL
tLLWL
tELWL
tAS
Address Setting Time
0
0
µs
tLHAX
tAVH
L High to Address Transition
5
5
ns
tAVLH
tAVS
Address Valid to L High
10
10
ns
tAVWH
tAVBH
tAW
Address Valid to Write Enable High
Address Valid to Upper/Lower Byte Enable Transition
70
85
ns
tBLBH
tBLEH
tBLWH
tBW
Upper/Lower Byte Enable Low to End of Write Operation
70
85
ns
tELTV
tCEW
Chip Enable Low to WAIT Valid
1
tAXCH
tCKA
In Mixed-Mode Operation: Delay between Address
Transition in Asynchronous Write mode and Clock High in
Burst Read mode
70
85
ns
tEHEL
tCPH
Chip Enable High between Subsequent Asynchronous
Operations
5
5
ns
tELLH
tBLLH
tCVS
Chip Enable Low to L High
10
10
ns
tELBH
tELWH
tCW
Chip Enable Low to End of Write Operation
70
85
ns
tEHDX
tWHDX
tBHDX
tDH
Input Hold from End of Write Operation
0
0
ns
tDVEH
tDVBH
tDVWH
tDW
Data to Write Time Overlap
23
23
ns
tLLLH
tVP
L Pulse Width Low
10
10
ns
tLHLL
tVPH
L Pulse Width High
10
10
ns
tLLWH
tVS
L Low to Write Enable High
70
85
ns
tAVAX
tWHWH
tWC
Write Cycle Time
70
85
ns
tWLBH
tWLEH
tWLWH
tWP
Write Pulse Width
46
55
ns
tWHWL
tWPH
Write Enable Pulse Width High
10
10
ns
tWHAX
tWR
Write Enable High to Address Transition
0
0
ns
tWLDV
tWHZ
Write Enable Low to Data Valid
40/48
7.5
8
1
7.5
8
ns
ns
M69KB096AA
M69KB096AA
Symbol
Alt.
Parameter
70ns
Min
85ns
Max
Min
Unit
Max
tAVEL
tAVWL
tAVBL
tLLWL
tELWL
tAS
Address Setting Time
0
0
µs
tLHAX
tAVH
L High to Address Transition
5
5
ns
tEHTZ
tBHTZ
tWHTZ
tHZ
Chip Enable High to WAIT Hi-Z
LB/UB High to WAIT Hi-Z
Write Enable High to WAIT Hi-Z
8
8
ns
Note: 1. WE# LOW time must be limited to tCEM (8 µs).
2. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14. The transition timings measure a
transition of 100 mV between the High-Z level (VCCQ/2) and VOH or VOL.
3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14. The High-Z timings measure a transition of 100 mV between VOH or VOL and VCCQ/2.
Figure 30. Synchronous Burst Write AC Waveform
tKHKH
K
VALID
ADDRESS
A0-A21
tAVKH
tLLKH
tKHLH
L
tBLKH
tKHBH
LB/UB
tKHEH
tELKH
tELEH
tEHEL
E
G
tWHKH
tKHWH
W
tKHTV
tELTV
WAIT
D0-D15
Hi-Z
Hi-Z
tDVKH tKHDX
Hi-Z
VALID
INPUT
VALID
INPUT
VALID
INPUT
VALID
INPUT
WRITE Burst Identified
(W = Low)
AI06792b
Note: 1. Non default BCR Register settings: Latency code two (three clocks); WAIT active Low; WAIT asserted during delay.
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
41/48
M69KB096AA
Figure 31. Continuous Burst Write Showing an Output Delay for End-of-R ow Condition (BCR8=0)
tKLKH
K
tKHKH
A0-A21
tF
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
L
LB/UB
E
G
W
tKHTV
tKHTX
(3)
WAIT
tDVKH tKHDX
DQ0-DQ15
VALID
INPUT D[n]
VALID
INPUT D[n+1]
VALID
INPUT D[n+2]
VALID
INPUT D[n+3]
VALID
INPUT D[n+4]
End of Row
AI06793b
Note: 1.
2.
3.
4.
42/48
Non default BCR Register settings: 3 clock cycle latency; WAIT active Low, Burst Wrap bit BCR3 set to ‘0’ (wrap).
Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
WAIT will be asserted for a maximum of (2xLC)+1 cycles (LC being the Latency Code set through BCR[13-11])
Taking E high or L Low will abort the Burst operation and the writing of the first data.
M69KB096AA
Figure 32. Synchronous Burst Write Followed by Read AC Waveforms (4 Words)
tKHKH
tKLKH
K
tKHAX
tKHKL
tKHAX
tAVKH
tAVKH
Addr.
tKHLH
tLLKH
tKHLH
tKHLL
L
tELKH
tKHEH
tKHEH
tEHEL
E
(2)
tELKH
tGLQX
tGHQZ
G
tWLKH
tWHKH
tKHWL
W
tKHWH
UB, LB
tKHTX
tKHTX
WAIT
tDVKH
DQ0DQ15
tKHDX
DIN0
DIN1 DIN2
DIN3
tKHQX2
DO0
DO1
DO2
DO3
ai11313
Note: 1. The Latency type can set to fixed or variable mode. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal
is active Low (BCR10=0), and is asserted during delay (BCR8=0). In fixed Latency mode, row boundary crossing
2. E can remain Low between the Burst Read and Burst Write operation, but it must not be held Low for longer than tELEH.
43/48
M69KB096AA
Figure 33. Configuration Register Write in Synchronous Mode Followed by Read Operation
K
Latch Control Register Value
A0-A21
except A19
ADDRESS
OPCODE
tAVKH
Latch Control Register Address
ADDRESS
A19
tRHKH
tKHRL
tCHKH
tKHLH
CR
L
tEHEL
tELKH
E
G
tWLKH
tKHLH
W
LB/UB
WAIT
tELTV
Hi-Z
Hi-Z
DQ0-DQ15
AI06779b
Note: 1. Non default BCR Register settings: Latency code two (three clocks); WAIT active Low; Hold data one clock; WAIT asserted during
delay.
2. A19 = VIL to load RCR; A19 = VIH to load BCR.
44/48
M69KB096AA
Table 18. Synchronous Burst Write AC Characteristics
M69KB096AA
Symbol
Alt.
Parameter
80MHz
Min
66MHz
Max
Min
Unit
Max
tEHEL(1)
tCBPH
Chip Enable High between Subsequent Mixed-Mode Read
Operations
5
tELTV
tCEW
Chip Enable Low to WAIT Valid
1
7.5
1
7.5
ns
tCLK
Clock Period
12.5
20
15
20
ns
tELKH
tCSP
Chip Enable Low to Clock High
4.5
20
5
20
ns
tKHAX
tKHBH
tKHWH
tKHEH
tKHLH
tKHRL
tHD
Hold Time From Active Clock Edge
tR
tF
tKHKL
Clock Rise Time
Clock Fall Time
tKHTV
tKHTL
Clock High to WAIT Valid
tKHKL
tKP
Clock High to Clock Low
tAVKH
tBLKH
tWHKH
tWLKH
tCHKH
tRHKH
tSP
tELEH(1)
tCEM
tKHKH
(2)
5
2
Set-up Time to Active Clock Edge
ns
2
ns
1.8
2.0
ns
9
11
ns
4
5
ns
3
3
ns
Maximum Chip Enable Pulse Width
8
8
µs
Note: 1. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every tELEH. A refresh opportunity is
satisfied by either of the following two conditions: E = VIH during Clock input K rising edge or E = VIH for longer than 15ns.
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.
Figure 34. Power-Up AC Waveforms
E
tVCHEL
VCC, VCCQ
1.7V
Device Ready For Normal Operation
Device Initialization
AI06794
Table 19. Power-Up AC Characteristics
M69KB096AA
Symbol
Alt.
Parameter
70ns
Min
tVCHEL
tPU
Initialization delay
85ns
Max
150
Min
Unit
Max
150
µs
45/48
M69KB096AA
PART NUMBERING
Table 20. Ordering Information Scheme
Example:
M69KB096 A
A
70
C
W
8
Device Type
M69 = PSRAM
Mode
K =Tested Die
Operating Voltage
B = VCC = 1.7 to 1.95V, Burst, Address/Data Bus Standard x16
Array Organization
096 = 64 Mbit (4Mb x16)
Option
A = 1 Chip Enable
Die Revision
A = Revision A
Speed Class
70 = 70ns
85 = 85ns
Maximum Clock Frequency
A= 66 MHz Max Clock Frequency in Burst Read Mode
C= 80MHz Max Clock Frequency in Burst Read Mode
Package
W = Unsawn Wafer
Operating Temperature
8 = –30 to 85 °C
The notation used for the device number is as shown in Table 20.. Not all combinations are necessarily
available. For a list of available options (speed, package, etc.) or for further information on any aspect of
this device, please contact your nearest STMicroelectronics Sales Office.
46/48
M69KB096AA
REVISION HISTORY
Table 21. Document Revision History
Date
Rev.
13-Oct-2004
0.1
First Issue.
0.2
ISB current for Standard Leakage option added in FEATURES SUMMARY.
ISB current for Standard Leakage option added in Table 13., DC Characteristics and test
conditions updated. ITCR current for Standard Leakage option added in Table
14., Temperature Compensated Refresh Specifications and Conditions. IPAR current for
Standard Leakage option added in Table 15., Partial Array Refresh Specifications and
Conditions.
Standard Leakage option added in Table 20., Ordering Information Scheme.
29-Apr-2005
1.0
Root Part Number changed to M69KB096AA.
104MHz maximum clock frequency and Low Leakage option removed.
Temperature range updated to –30°C to +85°C.
Clock Input (K). definition updated. Figure 3., Block Diagram modified.
Bus Modes Tables 2, 3 and Synchronous Burst Mode paragraph updated.
Output Impedance Bit (BCR5) renamed Driver Strength and definition updated.
R1 and R2 updated in Table 13., DC Characteristics and Refresh Specifications and
Conditions tables merged into Table 14..
Figures 15, 16, and 17 describing Asynchronous Read AC waveforms updated.
Figures 18, 19, 20, 21 and 22 describing Synchronous Read AC waveforms updated.
Figures 23, 24, and 25, describing Asynchronous Write AC waveforms updated. tAVWL and
tAVBL added in Table 17., Asynchronous Write AC Characteristics.
Figures 28 and 29 added.
Figures 30, 31, and 32, describing Synchronous Write AC waveforms updated. Figure
32., Synchronous Burst Write Followed by Read AC Waveforms (4 Words) added. tRHKH
and tKHRL added in Table 18., Synchronous Burst Write AC Characteristics
Table 21., Bond Pad Location and Identification modified to express the pad coordinates
from the center of the die.
16-June-2005
2.0
, FEATURES SUMMARY, OPERATING MODES and Figure 5., Synchronous Burst Write
Mode (4-word burst) modified.
18-Aug-2005
3.0
Updated Note 2 in Table 13., page 23, added notes to Table 14., page 24 and Table
17., page 40. Deleted Note 5 from Table 15., page 27.
12-Dec-2005
4
Clock rate added in datasheet title.
Test conditions for ICC1, ICC1P, ICC2, ICC3R, ICC3W and ISB updated in Table 13., DC
Characteristics.
19-Jan-2006
5
Section Wafer and die specifications removed.
11-Feb-2005
Revision Details
47/48
M69KB096AA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
48/48