CYU01M16ZCC MoBL3™ PRELIMINARY 16-Mbit (1M x 16) Pseudo Static RAM Features • Wide voltage range: 2.2V–3.6V • Access Time: 70 ns • Ultra-low active power — Typical active current: 3 mA @ f = 1 MHz — Typical active current: 18 mA @ f = fmax • Ultra low standby power • 16-word Page Mode • Automatic power-down when deselected • CMOS for optimum speed/power • Deep Sleep Mode • Offered in a Lead-Free 48-ball BGA Package • Operating Temperature: –40°C to +85°C Functional Description[1] The CYU01M16ZCC is a high-performance CMOS Pseudo Static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device Logic Block Diagram Reading from the device is accomplished by taking Chip Enables (CE LOW) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a complete description of read and write modes. Deep Sleep Mode is enabled by driving ZZ LOW. See the Truth Table for a complete description of Read, Write, and Deep Sleep mode. 1M × 16 RAM Array SENSE AMPS A11 A12 A13 A14 A15 A16 A17 A18 A19 Writing to the device is accomplished by taking Chip Enable (CE LOW) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). DATA IN DRIVERS ROW DECODER A8 A9 A10 can be put into standby mode when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A6 A5 A4 A3 A2 A1 A0 A7 BHE WE CE OE BLE Power-Down Circuit BHE BLE CE ZZ Refresh/Power-down Circuit Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05602 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 16, 2006 CYU01M16ZCC MoBL3™ PRELIMINARY Pin Configuration[2, 3] 48-Ball VFBGA Top View 4 3 1 2 BLE OE A0 I/O8 BHE I/O9 5 6 A1 A2 ZZ A A3 A4 CE I/O0 B I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Product Portfolio[4] Power Dissipation Product CYU01M16ZCC Speed (ns) VCC Range (V) Min. Typ.[4] Max. 2.2 3.0 3.6 Low-Power Modes At power-up, all four sections of the die are activated and the PSRAM enters into its default state of full memory size and refresh space. This device provides four different Low-Power Modes. 1. Reduced Memory Size Operation 2. Partial Array Refresh 3. Deep Sleep Mode 4. Temperature Controlled Refresh Reduced Memory Size Operation In this mode, the 16-Mb PSRAM can be operated as a 12-Mbit, 8-Mbit and 4-Mbit memory block. Please refer to “Variable Address Space Register (VAR)” on page 4 for the protocol to turn on/off sections of the memory. The device remains in RMS mode until changes to the Variable Address Space register are made to revert back to a complete 16-Mbit PSRAM. Partial Array Refresh The Partial Array Refresh mode allows customers to turn off sections of the memory block in the Stand-by mode (with ZZ 70 Operating ICC (mA) f = 1MHz f = fmax Standby ISB2 (µA) Typ.[4] Max. Typ.[4] Max. Typ.[4] Max. 3 5 18 25 55 70 tied LOW) to reduce standby current. In this mode the PSRAM will only refresh certain portions of the memory in the Stand-By Mode, as configured by the user through the settings in the Variable Address Register. Once ZZ returns HIGH in this mode, the PSRAM goes back to operating in full address refresh. Please refer to “Variable Address Space Register (VAR)” on page 4 for the protocol to turn off sections of the memory in Stand-By mode. If the VAR register is not updated after the power up, the PSRAM will be in its default state. In the default state the whole memory array will be refreshed in the Stand-By Mode. The 16-Mbit MoBL3™ is divided into four 4-Mbit sections allowing certain sections to be active (i.e., refreshed). Deep Sleep Mode In this mode, the data integrity in the PSRAM is not guaranteed. This mode can be used to lower the power consumption of the PSRAM in an application. This mode can be enabled and disabled through VAR similar to the RMS and PAR mode. Deep Sleep Mode is activated by driving ZZ LOW. The device stays in the deep sleep mode until ZZ is driven HIGH. Notes: 2. Ball H6 and E3 can be used to upgrade to a 32M and a 64M density respectively. 3. NC “no connect” - not connected internally to the die. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25°C. Tested initially and after any design changes that may affect the parameter. Document #: 38-05602 Rev. *F Page 2 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY Variable Address Mode Register (VAR) Update[5, 6] tWC ADDRESS Lower-order address (A0-A4) Low Power Modes CE tAW tHA t BW BHE / BLE t SA t WE t PWE ZZWE ZZ tZZMIN Deep Sleep Mode—Entry/Exit[7] tZZMIN ZZ Deep Sleep Mode tR tCDR CE VAR Update and Deep Sleep Mode Timing[5, 6] Parameter Description tZZWE ZZ LOW to Write Start tCDR Chip deselect to ZZ LOW tR[7] Operation Recovery Time (Deep Sleep Mode only) tZZMIN Deep Sleep Mode Time Min. Max. Unit 1 µs 0 ns 200 µs 8 µs Notes: 5. OE and the data pins are in a don’t care state while the device is in variable address mode. 6. All other timing parameters are as shown in the data sheets. 7. tR applies only in the deep sleep mode. Document #: 38-05602 Rev. *F Page 3 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY Variable Address Space Register (VAR) A19 – A5 A4 A3 A2 A1 A0 Memory Array Selection 00 – 16M(Default) 01 – 12M 10 – 8M 11 – 4M Top/Bottom Half Selection Reserved (RFU) 0 – Bottom (Default) 1 – Top Array On/Off on ZZ ZZ Enable/Disable 0 – PAR Mode (Default) 1 – RMS Mode 0 – Deep Sleep Enabled (Default) 1 – Deep Sleep Disabled Variable Address Space—Address Patterns Partial Array Refresh Mode (A3=0, A4=1) A2 A1, A0 Size Density 0 11 1/4th of the array Refresh Section 00000h - 3FFFFh (A19 = A18 = 0) Address 256K x 16 4M 0 10 1/2th of 00000h - 7FFFFh (A19 = 0) 512K x 16 8M 0 01 3/4th of the array 00000h - BFFFFh (A19:A18 not equal to 11) 768K x 16 12M 1 11 1/4th of the array C0000h - FFFFFh (A19 = A18 = 1) 256K x 16 4M 1 10 1/2th of the array 80000h - FFFFFh (A19 = 1) 512K x16 8M 01 3/4th of 40000h - FFFFFh (A19:A18 not equal to 00) 786K x16 12M 1 the array the array Reduced Memory Size Mode (A3=1, A4=1) 0 11 1/4th of the array 00000h - 3FFFFh (A19 = A18= 0) 256K x 16 4M 0 10 1/2th of the array 00000h - 7FFFFh (A19 = 0) 512K x 16 8M 0 01 3/4th of the array 00000h - BFFFFh (A19:A18 not equal to 1 1) 768K x 16 12M 0 00 Full array 00000h - FFFFFh (Default) 1M x 16 16M 1 11 1/4th of C0000h - FFFFFh (A19 = A18 = 1) 256K x 16 4M 1 10 1/2th of the array 80000h - FFFFFh (A19 = 1) 512K x 16 8M 1 01 3/4th of 40000h - FFFFFh (A19:A18 not equal to 00) 768K x 16 12M 1 00 Full array 1M x 16 16M the array the array 00000h - FFFFFh (Default) Page Mode This device can be operated in a page read mode. This is accomplished by initiating a normal read of the device. In order to operate the device in page mode, the upper order address bits should be fixed for four-word page access operation, all address bits except for A1 and A0 should be fixed until the page access is completed. For an eight-word page access, all address bits, except for A2, A1, and A0, Page Mode Feature should be fixed. For a sixteen-word page mode all address bits, except for A3, A2, A1, and A0, should be fixed. The supported page lengths are four, eight, and sixteen words. Random page read is supported for all three four, eight, and sixteen-word page read options. Therefore, any address can be used as the starting address. Please refer to the table below for an overview of the page read modes. 4-Word Mode 8-Word Mode 16-Word Mode Page Length 4 words 8 words 16 words Page Read Corresponding Addresses A1, A0 A2, A1, A0 A3, A2, A1, A0 Page Read Start Address Don't Care Don't Care Don’t Care Page Direction Don't Care Don't Care Don’t Care Document #: 38-05602 Rev. *F Page 4 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY Power-up Characteristics The initialization sequence is shown in the figure below. Chip Select (CE) should be HIGH for at least 200 µs after VCC has reached a stable value. No access must be attempted during this period of 200 µs. ZZ is high (H) for the duration of power-up. Stable Power VCC (LOGIC HIGH) ZZ First Access Tpu CE Parameter Description Min. Tpu Chip Enable Low After Stable VCC 200 Document #: 38-05602 Rev. *F Typ. Max. Unit µs Page 5 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY DC Input Voltage[8, 9, 10] .................. –0.3V to VCCMAX + 0.3V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... > 200 mA Supply Voltage to Ground Potential ..............................–0.3V to VCCMAX + 0.3V DC Voltage Applied to Outputs in High Z State[8, 9, 10] ......................–0.3V to VCCMAX + 0.3V Device Range CYU01M16ZCC Industrial Operating Temperature (TA) VCC –40°C to +85°C 2.2V to 3.6V DC Electrical Characteristics (Over the Operating Range) [8, 9, 10] CYU01M16ZCC-70 ns Parameter Description Test Conditions VCC Supply Voltage VOH Output HIGH Voltage IOH = –0.1 mA VCC= 2.2V to 3.6V VOL Output LOW Voltage IOL = 0.1 mA, VCC= 2.2V to 3.6V Min. Typ.[4] Max. Unit 2.2 3.0 3.6 V VCC – 0.2 V 0.2 V VIH Input HIGH Voltage VCC= 2.2V to 3.6V 0.8 * VCC VCC + 0.3V V VIL Input LOW Voltage VCC= 2.2V to 3.6V –0.3 0.2 * VCC V IIX Input Leakage Current GND < VIN < VCC –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC –1 +1 µA ICC VCC Operating Supply Current f = fMAX = 1/tRC VCC= VCCmax IOUT = 0 mA CMOS levels 18 25 mA f = 1MHz 3 5 mA ISB1 Automatic CE Power-Down Current — CMOS Inputs CE > VCC – 0.2V, VIN > VCC – 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = 3.60V, ZZ >= VCC – 0.2V 55 70 µA ISB2 Automatic CE CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN Power-Down < 0.2V, f = 0, VCC = VCCMAX, Current — CMOS Inputs ZZ >= VCC – 0.2V Deep Sleep Current VCC = VCCMAX, ZZ <0.2V, CE = HIGH or BHE and BLE = HIGH 55 70 µA 10 µA IZZ Capacitance[11] Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max. Unit 8 pF Notes: 8. VIL(MIN) = –0.5V for pulse durations less than 20 ns. 9. VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns. 10. Overshoot and undershoot specifications are characterized and are not 100% tested. 11. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05602 Rev. *F Page 6 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY Thermal Resistance[11] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions V FBGA Unit 56 °C/W 11 °C/W Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA / JESD51. AC Test Loads and Waveforms R1 VCC OUTPUT VCC GND 30 pF INCLUDING JIG AND SCOPE R2 10% Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH Parameters 3.0V (VCC) Unit R1 26000 Ω R2 26000 Ω RTH 13000 Ω VTH 1.50 V Document #: 38-05602 Rev. *F Page 7 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY Switching Characteristics Over the Operating Range[12, 13, 14, 15, 18] 70 ns Parameter Description Min. Max. Unit 40000 ns Read Cycle tRC [17] Read Cycle Time 70 tCD Chip Deselect Time CE, BLE/BHE High Pulse Time 15 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns tLZOE ns 70 [13, 14, 16] OE LOW to Low Z 5 ns 5 [13, 14, 16] ns ns tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z[13, 14, 16] tHZCE CE HIGH to High Z[13, 14, 16] 25 ns tDBE BLE/BHE LOW to Data Valid 70 ns 25 ns 40000 ns 35 ns 40000 ns Z[13, 14, 16] tLZBE BLE/BHE LOW to Low tHZBE BLE/BHE HIGH to High Z[13, 14, 16] 25 10 ns ns 5 ns Page Read Cycle tPC Page Mode Read Cycle Time tPA Page Mode Address Access 35 Write Cycle[15] tWC Write Cycle Time 70 tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tCD Chip Deselect Time CE, BLE/BHE High Pulse Time 15 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 50 ns tBW BLE/BHE LOW to Write End 60 ns tSD Data Set-Up to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE WE LOW to High-Z[13, 14, 16] tLZWE Low-Z[13, 14, 16] WE HIGH to 25 10 ns ns Notes: 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section. 13. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V) 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write 16. High-Z and Low-Z parameters are characterized and are not 100% tested. 17. If invalid address signals shorter than min.tRC are continuously repeated for 40us, the device needs a normal read timing (tRC) or needs to enter standby state at least once in every 40 µs. 18. In order to achieve 70-ns performance, the read access must be CE controlled. That is, the addresses must be stable prior to CE going active. Document #: 38-05602 Rev. *F Page 8 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY Switching Waveforms Read Cycle 1 (Address Transition Controlled)[20, 21] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Read Cycle 2 (OE Controlled)[19, 21] ADDRESS tRC CE tCD tHZCE tACE BHE/BLE tLZBE tDBE tHZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT 50% 50% ICC ISB Notes: 19. Whenever CE, BHE / BLE are taken inactive, they must remain inactive for a minimum of 15ns. 20. Device is continuously selected. OE, CE = VIL. 21. WE is HIGH for Read Cycle. Document #: 38-05602 Rev. *F Page 9 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY Switching Waveforms (continued) Page Read Cycle (ZZ = WE = VIH, 16 word access)[17, 21] t RC A4-A19 tOHA tAA A0-A3 t PC CE t ACE tHZBE t DOE OE t HZCE BHE/BLE tDBE t PAA t LZCE DATA OUT DATA VALID High Z DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID DATA VALID Write Cycle 1 (WE Controlled)[15, 16, 19, 23] t WC ADDRESS tSCE CE tCD tSA tAW tPWE tHA WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA DON’T CARE tHZOE Notes: 22. Data I/O is high-Impedance if OE > VIH. 23. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05602 Rev. *F Page 10 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY Switching Waveforms (continued) Write Cycle 2 (CE Controlled)[15, 16, 19, 22, 23] t WC ADDRESS tSCE CE tSA tHA tAW tPWE WE tBW BHE/BLE OE tSD t HZOE DATA I/O tHD VALID DATA DON’T CARE Write Cycle 3 (WE Controlled, OE LOW)[19, 23] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tSA tHA tPWE WE tSD DATAI/O DON’T CARE VALID DATA tHZWE Document #: 38-05602 Rev. *F tHD tLZWE Page 11 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY Switching Waveforms (continued) Write Cycle 4 (BHE/BLE Controlled, OE LOW)[15, 19, 22, 23] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DON’T CARE DATA I/O tHD VALID DATA Truth Table[24,25] ZZ CE WE OE BHE BLE Inputs/Outputs Mode Power H H X X X X High Z Deselect/Power-down Standby (ISB) H X X X H H High Z Deselect/Power-down Standby (ISB) H L X X H H High Z Deselect/Power-down H L H L L L Data Out (I/O0–I/O15) Read Active (ICC) H L H L H L Data Out (I/O0–I/O7); Read I/O8–I/O15 in High Z Active (ICC) H L H L L H Data Out (I/O8–I/O15); Read I/O0–I/O7 in High Z Active (ICC) H L H H L L High Z Output Disabled Active (ICC) H L H H H L High Z Output Disabled Active (ICC) H L H H L H High Z Output Disabled Active (ICC) H L L X L L Data In (I/O0–I/O15) Write (Upper Byte and Lower Active (ICC) Byte) H L L X H L Data In (I/O0–I/O7); I/O8–I/O15 in High Z Write (Lower Byte Only) Active (ICC) H L L X L H Data In (I/O8–I/O15); I/O0 –I/O7 in High Z Write (Upper Byte Only) Active (ICC) L L L X L L Data In (A0 - A4) Write (Variable Address Mode Register) Active (ICC) L H X X X X High Z Deep Power-down / PAR Deep Sleep (IZZ) / Standby Standby (ISB) Notes: 24. H = Logic HIGH, L = Logic LOW, X = Don’t Care. 25. During ZZ = L and CE = H, Mode depends on how the VAR is set up either in PAR or Deep Sleep Modes. Document #: 38-05602 Rev. *F Page 12 of 14 CYU01M16ZCC MoBL3™ PRELIMINARY Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 70 CYU01M16ZCCU-70BVXI BV48 48-ball Fine Pitch VFBGA (6 mm × 8 mm × 1 mm) Lead-Free Industrial Please contact your local Cypress Sales representative for availability of other parts. Package Diagram 48-Lead VFBGA (6 x 8 x 1 mm) BV48 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 4 5 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 6.00±0.10 0.10 C 0.21±0.05 0.25 C 0.55 MAX. B 0.15(4X) 51-85150-*D C 1.00 MAX 0.26 MAX. SEATING PLANE MoBL is a registered trademark and MoBL3 and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05602 Rev. *F Page 13 of 14 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CYU01M16ZCC MoBL3™ Document History Page Document Title: CYU01M16ZCC MoBL3™ 16-Mbit (1M x 16) Pseudo Static RAM Document Number: 38-05602 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 278869 See ECN SYT New Data Sheet *A 280850 See ECN REF Updated the Ordering information to show lead-free offering. *B 314034 See ECN PCI Corrected Part Number Added Operating Range in Features Section Moved address lines A8 - A10 from Column decoder to Row decoder in the Logic Block Diagram Changed Pin Configuration Diagram Name from FBGA to VFBGA Modified description on Deep Sleep Mode Changed tZZWE description Changed ΘJA and ΘJC from 55 and 17 °C/W to 56 and 11°C/W respectively Changed R1, R2 and RTH from 22000, 22000 and 11000 Ω to 26000, 26000 and 13000 Ω respectively Modified Test Condition for IIX and IOZ Removed note # 18 from *A rev Changed VCC(typ) to VCC in note # 12 Changed VOL Max., to 0.2 from 0.2 * VCC Changed tOHA from 10 ns to 5 ns Changed tSCE, tAW and tBW from 45 to 50 ns Changed tRC and tWC from 6000 ns to 40000 ns Changed tPC and tPA from 15 ns to 20 ns Added Parameter tCD in AC Table and its corresponding footnote in Notes Section Parameter tCD added in Read Cycle 2 and Write Cycle 1 Timing Diagrams Changed from Advance Information to Preliminary *C 351766 See ECN PCI Modified Logic Block Diagram Modified description on Deep Sleep Mode Deleted Page Write in the Page Mode Feature Table Added CE, BHE and BLE in test conditions for IZZ in DC Table Modified condition in the third row of the Truth Table for ZZ Pin from X to H *D 386551 See ECN PCI Changed tPC and tPA from 20 to 25 ns Replaced TBDs with appropriate values *E 406266 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court”. Removed 55 ns Speed Bin. Removed BHE, BLE in the DPD entry waveform on page #3. Included ZZ in power-up characteristics on page #5. Added ISB1 specification in the DC characteristics table on page #6. Added test condition ZZ>= VCC-0.2V for ISB2 Updated the Truth Table for DPD / PAR and Write (Variable Address Mode Register) Modes. *F 420604 See ECN HRT Changed TCD value to 15 ns from 5 ns on Read and Write Cycles Changed TPC and TPAA values to 35 ns from 25 ns Included “Chip Enable Access” footnote in AC Parameters Changed Isb2 value from 60µA to 70µA Document #: 38-05602 Rev. *F Page 14 of 14