Application Note 9520 Using the HS-26C(T)32RH Radiation Hardened RS-422 Line Receiver Description VDD The HS-26C(T)32RH is a radiation hardened RS-422 line receiver which is pin and functional compatible with commercial 2632 types. The HS-26C32RH has CMOS enable pin input levels and the HS-26CT32RH accepts TTL-level enable signals. The two circuits are identical except for the configuration of the logic input buffers. The HS-26C32RH has the same input characteristics (impedance, hysteresis, fail-safe) as commercial types. R0 42k DIODE D6 R3 2.24k DIODE D7 R4 2.8k IN+ R5 10.6k GND Pinout VDD HS-26C(T)32RH TOP VIEW AIN 1 16 VDD AIN 2 15 BIN AOUT 3 14 BIN D11 R16 2.24k DIODE D16 R15 2.8k INR12 10.6k R17 42k 13 BOUT ENABLE 4 COUT 5 12 ENABLE CIN 6 11 DOUT CIN 7 10 DIN GND 8 9 DIN The HS-26C(T)32RH presents a resistive impedance of approximately 10kΩ to the line. This impedance is the composite of the input divider network. No protection devices are present on the line side; there are internal protection devices at the inner end of the input resistor but these do not become active under normal power-up or down conditions. The input network is fully isolated from the substrate. There are no parasitic junctions. When the device is powered off the input remains at 10kΩ. The line inputs allow current to be fed from the line into device power and VDD rails. However, this current is not enough to activate the device with VDD off or open; under worst case conditions with both inputs at 5V, the VDD rail will power up to less than 400mV and the output will remain high impedance (off). There is no possibility of the line providing sufficient supply voltage to activate the ’32 or attached logic. Figure 1 is the schematic of the HS-26C(T)32RH input structure. 1 GND GND FIGURE 1. HS-26C(T)32RH LINE INPUT STRUCTURE Cross-Strapping Line Input Characteristics August 25, 2015 AN9520.4 DIODE In space systems it is vital to have a data communications bus structure which provides resistance to single point failures. One common technique is the use of redundant bus drivers and receivers in parallel, sometimes called cross-strapping. In this arrangement one driver and receiver are active and another pair is quiescent. The desire to minimize power leads to the need to power down the redundant circuits. This poses a problem for typical CMOS output structures and input protection circuits. The parasitic diodes in the P-Channel output drivers and the input clamp diodes will tend to clamp the signal unless the supply voltage to the quiescent parts remains above the bus signal range. The HS-26C(T)31RH transmitter provides RS-422 compliant output characteristics, including power-off isolation. The output stage presents a high impedance to the line with power off (VDD < 3V). This prevents any significant amount of current flow over an output voltage range of 0.25V to 6V with respect to device ground. The use of a BiCMOS output stage provides an output characteristic very similar to LSTTL devices and superior to standard CMOS. Figure 2 shows what the NPN, NMOS and PMOS device physical structures look like. Figure 3 illustrates the four standard output topologies and their associated parasitic diodes. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2007, 2008, 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 9520 NMOS NPN E (N) D (N) PMOS S (N) B (P) D (P) S (P) B (P) S (N) C/S (N) S (N) FIGURE 2. NPN, NMOS AND PMOS DEVICE PHYSICAL STRUCTURES The standard P-well CMOS structure presents an undesirable characteristic to the line when the supply is at 0V. This is due to the P-Channel driver’s parasitic drain-body diode, which becomes forward-biased at voltages above ground. (See Figure 3A.). N-Channel source-follower high-side drivers and NPN-based output drivers have parasitic diodes which remain reverse-biased with VDD at 0V and output voltages above ground. These output types will not conduct until the E-B or S-B diodes break down, typically above 7V. (See Figures 3B and 3C.) The HS-26C31RH line driver is produced in a radiation hardened CMOS process but uses a NPN bipolar output driver to provide both high output drive and power-off output isolation. The output can be run from ground to over 6V without significant leakage, with the supply off, unlike standard CMOS logic types. This allows VDD M4 PMOS NMOS S S A curve tracer can demonstrate the difference in behavior between a standard CMOS input and output with power off and the HS-26C31/32RH devices’ line inputs and outputs. The inactive CMOS devices clamp whatever line they are attached to at less than a volt, drawing many milliamperes. The line pins of the Intersil RS-422 chip set are well-behaved, acting as a three-state output and a 10kΩ input. VDD M49 D12 LINE OK D11 GND The HS-26C32RH line receiver has an input structure which provides a ±10V maximum input signal range with respect to device ground. The input impedance of the receiver is typically 10,000Ω, with no clamping devices at the pin. A powered-down device simply adds its input impedance in parallel to the other devices on the line. VDD M5 STANDARD CMOS OUTPUT STAGE the outputs of active and inactive drivers to be paralleled without complications. (See Figure 3D.) GND NMOS S D50 LINE M21 D10 D9 GND FORWARD BIASED VO > 0V NMOS S GND NMOS ONLY OUTPUT STAGE VDD UP VDD = GND PARASITIC DIODES OK D17 FIGURE 3A. GND OK D55 D25 GND VDD UP VDD = GND PARASITIC DIODES FIGURE 3B. VDD VDD Q53 D54 Q52 D31 GND STANDARD LSTTL OUTPUT STAGE VDD OK D28 GND VDD UP Q58 LINE VDD = GND PARASITIC DIODES OK D56 NMOS S D59 M44 D43 GND INTERSIL BiCMOS OUTPUT STAGE FIGURE 3C. GND LINE OK OK D57 D45 GND VDD UP VDD = GND PARASITIC DIODES FIGURE 3D. FIGURE 3. FOUR STANDARD OUTPUT TOPOLOGIES Submit Document Feedback 2 AN9520.4 August 25, 2015 Application Note 9520 System Noise Another primary benefit of a balanced, differential line standard such as RS-422 is the cancellation of radiated EMI from the data lines. A shielded twisted-pair data line has primary EMI cancellation by virtue of the anti-phase signals and Faraday shielding as well. In applications where sensitive analog circuitry has to reside near the data bus, this type of bus standard can significantly improve system noise levels and signal quality. Using this chip set, a 10MHz, low power, quiet bus system with cross-strapped redundant data paths can be implemented easily. The Intersil radiation-hardened CMOS solution cuts power compared to bipolar chip sets and allows configurations not possible with standard CMOS logic. Fail-safe operation depends on a true high impedance condition at the inputs. Some circuit or termination schemes may mask or reduce effectiveness of the fail-safe mechanism if they produce a low impedance across the input terminals. The minimum impedance permissible for adequate fail-safe operation is that which results in an input differential voltage of 400mV, the worst case VTH(in). The relationship between input fail-safe differential voltage and external input impedance is shown below. In order to produce an acceptable differential under an open-line fault condition, any input network external to the chip must present no less than 10kΩ to the line inputs. See plot in Figure 4. 1.00 The large voltage swings, low typical line impedance and differential bus also provide superior immunity to both supply and radiatively-coupled noise. The normal signal span is 8V (+4 to -4) for the HS-26C31/32RH, less than 5V for standard single-ended CMOS and less than 4V for LSTTL. In addition, the HS-26C32RH can tolerate differences between driver and receiver ground levels which would render standard logic either unreliable or completely nonfunctional. For example, an LSTTL or CMOS input whose ground supply is more than 1V below the driving device’s may never switch because its VIL(min) level cannot be met. The HS-26C32RH functions properly with its inputs 7V from device ground. This also minimizes the chances of ground bounce or supply spikes causing false logic states. Substrate Connection The substrate of the HS-26C(T)32RH circuits is connected internally to the VDD pin. If the ’32 is used in die form for hybrid applications, the die should be mounted to an electrically isolated surface. If there is any electrical connection to the back side of the die there will be a low value resistance to the VDD pin. However, the value of the resistance of the substrate and mounting material are not necessarily low or well enough controlled to use as a supply feed. 0.80 0.60 VTH(IN) 400mV MAX 0.40 VTH(IN) 200mV TYP 0.20 0.0 101 102 103 104 105 FIGURE 4. INPUT FAIL SAFE DIFFERENTIAL vs ZIN (OPEN) The practice of simple resistor shunt termination (100Ω across lines) will inhibit fail-safe operation because the shunt resistor will mask the open line condition. If a shunt termination scheme is to be used, it becomes necessary to design a termination which restores the differential bias to the front end. The schematic on the next page shows one possible implementation. Figure 5 produces too small an input differential voltage in the open-line fault condition. The internal input bias network is shunted by the termination resistor. Power Dissipation R21 100 The HS-26C(T)32RH dissipates about 15mA IDD current at standby. About half of this is used by the divider network and the balance by the input comparators’ analog circuitry. INP R23 100 Operating current at frequency is the sum of the standby current and the dynamic operating current given by (CPD) (VDD) (frequency). For the HS-26C(T)32RH the CPD (per active channel) is 40pF. This is equivalent to other ’32 types. INM 26C32MIN + - OUT R22 100 FIGURE 5. INCORRECT RESISTOR INPUT STRUCTURE Input Fail Safe . The HS-26C(T)32RH is designed to produce a logic “1” output state when the transmission line inputs are open. This is a special case fault tolerance feature. The fail-safe works by a designed imbalance in the input resistor structure, which produces an inherent error voltage when the inputs are high impedance. The error voltage must be greater than the minimum input differential signal. Submit Document Feedback 3 AN9520.4 August 25, 2015 Application Note 9520 Figure 6 produces an adequate input differential voltage in the open-line fault condition. The internal input bias network is supplemented externally to compensate for the termination resistor. R19 1000 INP R11 100 INM R20 1000 26C32MIN + - OUT R15 1000 GND FIGURE 6. RESISTOR INPUT STRUCTURE FOR ADEQUATE INPUT DIFFERENTIAL VOLTAGE The active signal amplitude will be reduced by about 25%, due to the resistive division, but the amplitude will still be about 5x to 8x V TH(min), assuring adequate noise margin and speed. The HS-26C(T)31RH and HS-26C(T)32RH have been fully characterized to 300kRAD total dose. A sample of each wafer lot is evaluated to 300kRAD (Si) total dose, and all post rad electricals (in accordance with the datasheet) must pass. In addition, Single Event Upset (SEU) and Single Event Latch-up (SEL) testing on these two parts demonstrate that the SEU and SEL thresholds are each >80MEV/mg/cm2. The testing was performed by NASA Goddard Space Flight Center, and is published in the 1994 IEEE Radiation Effects Data Workshop. (IEEE publication # 94TH06841, “Single Event Effect Proton and Heavy Ion Test Results for Candidate Spacecraft Electronics”, by K. LaBel et al). Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the document is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 4 AN9520.4 August 25, 2015