Radiation Hardened, High Performance Industry Standard Single-Ended Current Mode PWM Controller ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH The ISL7884xASEH is a high performance, radiation hardened drop-in replacement for the popular 28C4x and 18C4x PWM controllers suitable for a wide range of power conversion applications including boost, flyback, and isolated output configurations. Its fast signal propagation and output switching characteristics make this an ideal product for existing and new designs. Features Features include up to 13.2V operation, low operating current, 90µA typical start-up current, adjustable operating frequency to 1MHz, and high peak current drive capability with 50ns rise and fall times. • 35ns Propagation Delay Current Sense to Output PART NUMBER • Electrically Screened to DLA SMD # 5962-07249 • QML Qualified Per MIL-PRF-38535 Requirements • 1A MOSFET Gate Driver • 90µA Typical Start-up Current, 125µA Max • Fast Transient Response with Peak Current Mode Control • 9V to 13.2V Operation • Adjustable Switching Frequency to 1MHz RISING UVLO MAX. DUTY CYCLE ISL78840ASEH 7.0 100% ISL78841ASEH 7.0 50% • Trimmed Timing Capacitor Discharge Current for Accurate Deadtime/Maximum Duty Cycle Control ISL78843ASEH 8.4V 100% • 1.5MHz Bandwidth Error Amplifier ISL78845ASEH 8.4V 50% • Tight Tolerance Voltage Reference Over Line, Load and Temperature Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the ordering information must be used when ordering. Detailed Electrical Specifications for the ISL788xASEH are contained in SMD 5962-07249. A “hot-link” is provided on our website for downloading. Applications • 50ns Rise and Fall Times with 1nF Output Load • ±3% Current Limit Threshold • Pb-Free Available (RoHS Compliant) • Radiation Environment: - High Dose Rate (50 - 300rad(Si)/s). . . . . . . . . 100 krad(Si) - Low Dose Rate (0.01rad(Si)/s). . . . . . . 100 krad(Si) (Note) NOTE: Product capability established by initial characterization. The “EH” version is acceptance tested on a wafer by wafer basis to 50 krad(Si) at low dose rate. • Current Mode Switching Power Supplies • Isolated Buck and Flyback Regulators • Boost Regulators • Direction and Speed Control in Motors • Control of High Current FET Drivers Pin Configurations ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH (8 LD SBDIP) TOP VIEW ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH (8 LD FLATPACK) TOP VIEW COMP 1 8 VREF FB 2 7 VDD CS 3 6 OUT RTCT 4 5 GND May 29, 2012 FN7952.0 1 COMP 1 8 VREF FB 2 7 VDD CS 3 6 OUT RTCT 4 5 GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH Ordering Information PART NUMBER (Notes 1, 2) ORDERING NUMBER TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # 5962R0724905VPC ISL78840ASEHVD -55 to +125 8 Ld SBDIP D8.3 5962R0724906VPC ISL78841ASEHVD -55 to +125 8 Ld SBDIP D8.3 5962R0724907VPC ISL78843ASEHVD -55 to +125 8 Ld SBDIP D8.3 5962R0724908VPC ISL78845ASEHVD -55 to +125 8 Ld SBDIP D8.3 5962R0724905VXC ISL78840ASEHVF -55 to +125 8 Ld Flatpack K8.A 5962R0724906VXC ISL78841ASEHVF -55 to +125 8 Ld Flatpack K8.A 5962R0724907VXC ISL78843ASEHVF -55 to +125 8 Ld Flatpack K8.A 5962R0724908VXC ISL78845ASEHVF -55 to +125 8 Ld Flatpack K8.A 5962R0724905V9A ISL78840ASEHVX -55 to +125 Die 5962R0724906V9A ISL78841ASEHVX -55 to +125 Die 5962R0724907V9A ISL78843ASEHVX -55 to +125 Die 5962R0724908V9A ISL78845ASEHVX -55 to +125 Die NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH. For more information on MSL please see techbrief TB363. 2 FN7952.0 May 29, 2012 Functional Block Diagram + - VREF VREF 5V START/STOP UV COMPARATOR ENABLE VDD OK VREF FAULT +- + 2.5V A 4.65V 4.80V +- 3 VREF UV COMPARATOR GND A = 0.5 PWM COMPARATOR +- CS 100mV 2R + - FB VF TOTAL = 1.15V ERROR AMPLIFIER + - 1.1V CLAMP ONLY ISL78841A, ISL78845A R Q T COMP Q OUT S Q 36k R Q RESET DOMINANT VREF 100k 2.9V 1.0V ON 150k OSCILLATOR COMPARATOR <10ns + RTCT 8.4mA ON CLOCK FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH VDD Typical Application - 48V Input Dual Output Flyback +3.3V C21 T1 + C16 R21 VIN+ R3 + C15 +1.8V C4 CR4 4 C2 C17 CR2 C5 + C22 + C20 C19 RETURN CR6 R1 36V TO 75V R16 C6 C1 C3 R17 Q1 R4 R18 R19 U2 C14 R28 R22 VIN- U3 R27 C13 R15 R20 U4 R26 COMP VREF CS V DD FB OUT RTCT GND ISL7884xASEH R6 R10 CR1 Q3 C12 VR1 C8 R13 C11 FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH CR5 Typical Application - Boost Converter C10 CR1 L1 VIN+ +VOUT + C2 C3 5 RETURN R4 Q1 R5 R9 C9 C1 R1 R2 U1 FB CS C4 RTCT ISL7884xASEH COMP R7 VREF VIN+ VDD OUT GND R3 C5 C7 VIN- C6 C8 R6 FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH R8 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH Absolute Maximum Ratings Thermal Information Supply Voltage VDD Without Beam . . . . . . . . . . . . . . .GND -0.3V to +30.0V Supply Voltage VDD Under Beam . . . . . . . . . . . . . . . . .GND -0.3V to +14.7V OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VDD + 0.3V Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 6.0V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld Flatpack Package (Notes 3, 4) 140 15 8 Ld SBDIP Package (Notes 3, 4) 98 15 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Maximum Total Dose Dose Rate = 50 - 100radSi/s . . . . . . . . . . . . . . . . . . . . . . . 100 krads (Si) Dose Rate = 0.01rad(Si)/s (Note 6). . . . . . . . . . . . . . . . . . . . . 100 krad (Si) SEB (No Burnout) (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 80Mev/mg/cm2 SEL (No latchup) (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 80Mev/mg/cm2 SET (Regulated VOUT within ±3%) (Note 9) . . . . . . . . . . . . 40Mev/mg/cm2 Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Supply Voltage (Typical Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 13.2V Radiation Information CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For θJC, the "case temp" location is the center of the ceramic on the package underside. 5. All voltages are with respect to GND. 6. Product capability established by initial characterization. The “EH” version is acceptance tested on a wafer by wafer basis to 50 krad(Si) at low dose rate. Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic on page 3 and page 4. VDD = 13.2V, RT = 10kΩ, CT = 3.3nF, TA = -55 to +125°C. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -55 to +125°C. PARAMETER TEST CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNITS UNDERVOLTAGE LOCKOUT START Threshold STOP Threshold Hysteresis Start-up Current, IDD ISL78840A, ISL78841A 6.5 7.0 7.5 V ISL78843A, ISL78845A 8.0 8.4 9.0 V ISL78840A, ISL78841A 6.1 6.6 6.9 V ISL78843A, ISL78845A 7.3 7.6 8.0 V ISL78840A, ISL78841A - 0.4 - V ISL78843A, ISL78845A - 0.8 - V VDD < START Threshold - 90 125 µA VDD < START Threshold, 100krad - 300 500 µA Operating Current, IDD (Note 7) - 2.9 4.0 mA Operating Supply Current, ID Includes 1nF GATE loading - 4.75 5.5 mA 4.925 5.000 5.050 V REFERENCE VOLTAGE Overall Accuracy Over line (VDD = 9V to 13.2V), load of 1mA and 10mA, temperature Long Term Stability TA = +125°C, 1000 hours (Note 8) - 5 - mV Current Limit, Sourcing -20 - - mA Current Limit, Sinking 5 - - mA CURRENT SENSE Input Bias Current VCS = 1V Input Signal, Maximum 6 -1.0 - 1.0 µA 0.97 1.00 1.03 V FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic on page 3 and page 4. VDD = 13.2V, RT = 10kΩ, CT = 3.3nF, TA = -55 to +125°C. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -55 to +125°C. (Continued) PARAMETER TEST CONDITIONS Gain, ACS = ΔVCOMP/ΔVCS 0 < VCS < 910mV, VFB = 0V CS to OUT Delay MIN (Note 10) TYP MAX (Note 10) UNITS 2.75 2.82 3.15 V/V - 35 55 ns ERROR AMPLIFIER Open Loop Voltage Gain (Note 8) - 90 - dB Unity Gain Bandwidth (Note 8) - 1.5 - MHz Reference Voltage, VREF VFB = VCOMP 2.475 2.500 2.530 V FB Input Bias Current, FBIIB VFB = 0V -1.0 -0.2 1.0 µA COMP Sink Current VCOMP = 1.5V, VFB = 2.7V 1.0 - - mA COMP Source Current VCOMP = 1.5V, VFB = 2.3V -0.4 - - mA COMP VOH VFB = 2.3V 4.80 - VREF V COMP VOL VFB = 2.7V 0.4 - 1.0 V PSRR Frequency = 120Hz, VDD = 9V to 13.2V (Note 8) - 80 - dB 48 51 53 kHz 0.2 1.0 % OSCILLATOR Frequency Accuracy Initial, TA = +25°C Frequency Variation with VDD TA= +25°C, (f13.2V - f9V)/f12V - Temperature Stability (Note 8) - 5 - % Amplitude, Peak-to-Peak Static Test - 1.75 - V RTCT Discharge Voltage (Valley Voltage) Static Test - 1.0 - V Discharge Current RTCT = 2.0V 6.5 7.8 8.5 mA - 1.0 2.0 V OUTPUT Gate VOH VDD to OUT, IOUT = -100mA Gate VOL OUT to GND, IOUT = 100mA - 1.0 2.0 V Peak Output Current COUT = 1nF (Note 8) - 1.0 - A Rise Time COUT = 1nF - 35 60 ns Fall Time COUT = 1nF - 20 40 ns OUTPUT OFF state leakage VDD = 5V - - 50 µA PWM Maximum Duty Cycle (ISL78840A, ISL78843A) COMP = VREF 94.0 96.0 - % Maximum Duty Cycle (ISL78841A, ISL78845A) COMP = VREF 47.0 48.0 - % Minimum Duty Cycle COMP = GND - - 0 % NOTES: 7. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current. 8. Limits established by characterization and are not production tested. 9. SEE tests performed with VREF bypass capacitor of 0.22µF and FSW = 200kHz. SEB/L tests done on a standalone open loop configuration. SET tests done in a closed loop configuration. For SEL no hard latch requiring manual intervention were observed. For more information see: ISL7884xASRH SEE Test Report. 10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7 FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH Typical Performance Curves NORMALIZED FREQUENCY 1.01 1.001 NORMALIZED VREF 1.000 1.00 0.99 0.98 -60 -40 -20 0 20 40 60 80 0.999 0.998 0.997 0.996 0.995 -60 100 120 140 TEMPERATURE (°C) FREQUENCY (kHz) NORMALIZED EA REFERENCE 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 103 1.001 1.000 0.998 0.997 -20 0 20 40 60 80 100 120 140 220pF 330pF 470pF 1.0nF 10 1 -40 100pF 100 2.2nF 3.3nF 4.7nF 6.8nF 1 TEMPERATURE (°C) Pin Descriptions RTCT - This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to GND. The oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The charge time, tC, the discharge time, tD, the switching frequency, f, and the maximum duty cycle, DMAX, can be approximated from Equations 1 through 4: t C ≈ 0.533 ⋅ RT ⋅ CT (EQ. 1) 0.008 ⋅ RT – 3.83 t D ≈ – RT ⋅ CT ⋅ In ⎛ --------------------------------------------- ⎞ ⎝ 0.008 ⋅ RT – 1.71 ⎠ (EQ. 2) f = 1 ⁄ (t (EQ. 3) +t ) D D = tC ⋅ f (EQ. 4) The formulae have increased error at higher frequencies due to propagation delays. Figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given switching frequency for the ISL78841ASEH, ISL78845ASEH. The value for the ISL78840ASEH, ISL78843ASEH will be twice that shown in Figure 4. 8 10 RT (kΩ) 100 FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN FIGURE 3. EA REFERENCE vs TEMPERATURE C -20 FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE FIGURE 1. FREQUENCY vs TEMPERATURE 0.996 -60 -40 COMP - COMP is the output of the error amplifier and the input of the PWM comparator. The control loop frequency compensation network is connected between the COMP and FB pins. FB - The output voltage feedback is connected to the inverting input of the error amplifier through this pin. The non-inverting input of the error amplifier is internally tied to a reference voltage. CS - This is the current sense input to the PWM comparator. The range of the input signal is nominally 0V to 1.0V and has an internal offset of 100mV. GND - GND is the power and small signal reference ground for all functions. OUT - This is the drive output to the power switching device. It is a high current output capable of driving the gate of a power MOSFET with peak currents of 1.0A. This GATE output is actively held low when VDD is below the UVLO threshold. VDD - VDD is the power connection for the device. The total supply current will depend on the load applied to OUT. Total IDD current is the sum of the operating current and the average output current. Knowing the operating frequency, f, and the MOSFET gate charge, Qg, the average output current can be calculated from Equation 5: I OUT = Qg × f (EQ. 5) FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. VREF - The 5.00V reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. The recommended bypass to GND cap is in the range 0.1µF to 0.22µF. A typical value of 0.15µF can be used. Functional Description Features The ISL7884xASEH current mode PWM makes an ideal choice for low-cost flyback and forward topology applications. With its greatly improved performance over industry standard parts, it is the obvious choice for new designs or existing designs which require updating. Oscillator The ISL7884xASEH has a sawtooth oscillator with a programmable frequency range to 2MHz, which can be programmed with a resistor from VREF and a capacitor to GND on the RTCT pin. (Please refer to Figure 4 for the resistor and capacitance required for a given frequency). Soft-Start Operation Soft-start must be implemented externally. One method, illustrated below, clamps the voltage on COMP. COMP Q1 GND C1 ISL7884xASEH R1 Slope Compensation For applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. The amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. For applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. Slope compensation may be accomplished by summing an external ramp with the current feedback signal or by subtracting the external ramp from the voltage feedback error signal. Adding the external ramp to the current feedback signal is the more popular method. From the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, Fm, without slope compensation is calculated in Equation 6: 1 Fm = -----------------Sntsw (EQ. 6) where Sn is the slope of the sawtooth signal and tsw is the duration of the half-cycle. When an external ramp is added, the modulator gain becomes Equation 7: 1 1 Fm = ------------------------------------- = -------------------------( Sn + Se )tsw m c Sntsw VREF D1 resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET’s input capacitance. TID environment of >50krads requires the use of a bleeder resistor of 10k from the OUT pin to GND. FIGURE 5. SOFT-START (EQ. 7) where Se is slope of the external ramp and becomes Equation 8: Se m c = 1 + ------Sn (EQ. 8) The criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at the switching frequency. The double-pole will be critically damped if the Q-factor is set to 1, over-damped for Q < 1, and under-damped for Q > 1. An under-damped condition may result in current loop instability. 1 Q = ------------------------------------------------π ( m c ( 1 – D ) – 0.5 ) (EQ. 9) The COMP pin is clamped to the voltage on capacitor C1 plus a base-emitter junction by transistor Q1. C1 is charged from VREF through resistor R1 and the base current of Q1. At power-up C1 is fully discharged, COMP is at ~0.7V, and the duty cycle is zero. As C1 charges, the voltage on COMP increases, and the duty cycle increases in proportion to the voltage on C1. When COMP reaches the steady state operating point, the control loop takes over and soft-start is complete. C1 continues to charge up to VREF and no longer affects COMP. During power-down, diode D1 quickly discharges C1 so that the soft-start circuit is properly initialized prior to the next power-on sequence. ⎞ ------------⎛ ⎛ --⎞ e = S n ⎝ ⎝ π + 0.5⎠ 1 – D – 1⎠ Gate Drive 1 1 V e = V n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞ ⎠1 –D ⎝⎝π ⎠ The ISL7884xASEH is capable of sourcing and sinking 1A peak current. To limit the peak current through the IC, an optional external resistor may be placed between the totem-pole output of the IC (OUT pin) and the gate of the MOSFET. This small series where Vn is the change in the current feedback signal (ΔI) during the on-time and Ve is the voltage that must be added by the external ramp. 9 where D is the percent of on-time during a switching cycle. Setting Q = 1 and solving for Se yields Equation 10: 1 1 (EQ. 10) Since Sn and Se are the on-time slopes of the current ramp and the external ramp, respectively, they can be multiplied by tON to obtain the voltage change that occurs during tON. (EQ. 11) FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH For a flyback converter, Vn can be solved in terms of input voltage, current transducer components, and primary inductance, yielding Equation 12: Assuming the designer has selected values for the RC filter (R6 and C4) placed on the CS pin, the value of R9 required to add the appropriate external ramp can be found by superposition. D ⋅ T SW ⋅ V IN ⋅ R CS 1 1 V e = ---------------------------------------------------- ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞ ⎠1 –D ⎝⎝π ⎠ Lp 2.05D ⋅ R 6 V e = ---------------------------R6 + R9 V (EQ. 12) where RCS is the current sense resistor, Tsw is the switching period, Lp is the primary inductance, VIN is the minimum input voltage, and D is the maximum duty cycle. The current sense signal at the end of the ON time for CCM operation is Equation 13: ( 1 – D ) ⋅ VO ⋅ T ⎞ N S ⋅ R CS ⎛ sw V CS = ------------------------ ⎜ I O + ----------------------------------------------⎟ NP 2L s ⎝ ⎠ (EQ. 13) V where VCS is the voltage across the current sense resistor, Ls is the secondary winding inductance, and IO is the output current at current limit. Equation 13 assumes the voltage drop across the output rectifier is negligible. Since the peak current limit threshold is 1.00V, the total current feedback signal plus the external ramp voltage must sum to this value when the output load is at the current limit threshold as: (EQ. 14) V e + V CS = 1V The factor of 2.05 in Equation 16 arises from the peak amplitude of the sawtooth waveform on RTCT minus a base-emitter junction drop. That voltage multiplied by the maximum duty cycle is the voltage source for the slope compensation. Rearranging to solve for R9 yields Equation 17: ( 2.05D – V e ) ⋅ R 6 R 9 = ---------------------------------------------Ve R6 + R9 R′ CS = --------------------- ⋅ R CS R9 (EQ. 18) VIN = 12V VO = 48V Ls = 800µH Substituting Equations 12 and 13 into Equation 14 and solving for RCS yields Equation 15: Lp = 8.0µH Adding slope compensation is accomplished in the ISL7884xASEH using an external buffer transistor and the RTCT signal. A typical application sums the buffered RTCT signal with the current sense feedback and applies the result to the CS pin as shown in Figure 6. (EQ. 17) Example: Ns/Np = 10 (EQ. 15) Ω The value of RCS determined in Equation 15 must be rescaled so that the current sense signal presented at the CS pin is that predicted by Equation 13. The divider created by R6 and R9 makes this necessary. shown in Equation 14. 1 R CS = --------------------------------------------------------------------------------------------------------------------------------------------------------1 - + 0.5 ⎞ N ( 1 – D ) ⋅ V O ⋅ T sw⎞ D ⋅ T sw ⋅ V IN ⎛ -⎛ π --------------------------------- ⋅ ⎜ ------------------ – 1⎟ + ------s- ⋅ ⎜ I O + ---------------------------------------------⎟ ⎜ 1–D ⎟ N ⎝ Lp 2L s ⎠ p ⎝ ⎠ (EQ. 16) V IO = 200mA Switching Frequency, fsw = 200kHz Duty Cycle, D = 28.6% R6 = 499Ω Solve for the current sense resistor, RCS, using Equation 15. RCS = 295mΩ Determine the amount of voltage, Ve, that must be added to the current feedback signal using Equation 12. Ve = 92.4mV Using Equation 17, solve for the summing resistor, R9, from CT to CS. VREF CS R6 ISL78843ASEH R9 RTCT C4 FIGURE 6. SLOPE COMPENSATION 10 R9 = 2.67kΩ Determine the new value of RCS (R’CS) using Equation 18. R’CS = 350mΩ Additional slope compensation may be considered for design margin. The above discussion determines the minimum external ramp that is required. The buffer transistor used to create the external ramp from RTCT should have a sufficiently high gain (>200) so as to minimize the required base current. Whatever base current is required reduces the charging current into RTCT and will reduce the oscillator frequency. FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH Fault Conditions A Fault condition occurs if VREF falls below 4.65V. When a Fault is detected, OUT is disabled. When VREF exceeds 4.80V, the Fault condition clears, and OUT is enabled. Ground Plane Requirements Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. VDD should be bypassed directly to GND with good high frequency capacitors. References [1] Ridley, R., “A New Continuous-Time Model for Current Mode Control”, IEEE Transactions on Power Electronics, Vol. 6, No. 2, April 1991. 11 FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH Package Characteristics Weight of Packaged Device 8 Ld Mini DIP: 0.7004 Grams 8 Ld Flatpack: 0.3605 Grams Die Characteristics Die Dimensions SUBSTRATE Silicon BACKSIDE FINISH Silicon PROCESS 0.6µM BiCMOS Junction Isolated ASSEMBLY RELATED INFORMATION 2030µm x 2030µm (80 mils x 80 mils) Thickness: 482µm ± 25.4µm (19.0 mils ± 1 mil) Interface Materials Substrate Potential Unbiased ADDITIONAL INFORMATION GLASSIVATION Type: Silicon Oxide and Silicon Nitride Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm TOP METALLIZATION Worst Case Current Density < 2 x 105 A/cm2 Transistor Count 1278 Type: AlCu (99.5%/0.5%) Thickness: 2.7µm ±0.4µm Die Map 12 FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE May 4, 2012 REVISION CHANGE FN7952.0 Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php 13 FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH Package Outline Drawing K8.A 8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE Rev 2, 12/10 0.015 (0.38) 0.008 (0.20) PIN NO. 1 ID OPTIONAL 1 2 0.050 (1.27 BSC) 0.005 (0.13) MIN 4 PIN NO. 1 ID AREA 0.022 (0.56) 0.015 (0.38) 0.115 (2.92) 0.070 (1.18) 0.265 (6.73) 0.245 (6.22) TOP VIEW 0.045 (1.14) 0.026 (0.66) 0.09 (0.23) 0.04 (0.10) 6 0.265 (6.75) 0.245 (6.22) -D- -H- -C0.180 (4.57) 0.170 (4.32) SEATING AND BASE PLANE 0.370 (9.40) 0.250 (6.35) 0.03 (0.76) MIN SIDE VIEW 0.007 (0.18) 0.004 (0.10) NOTES: LEAD FINISH 0.009 (0.23) BASE METAL 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) MAX 0.022 (0.56) 0.015 (0.38) 2. If a pin one identification mark is used in addition to a tab, the limits of the tab dimension do not apply. 3. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 4. Measure dimension at all four corners. 3 SECTION A-A 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab may be used to identify pin one. 5. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 6. Dimension shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 7. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 8. Controlling dimension: INCH. 14 FN7952.0 May 29, 2012 ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH Ceramic Dual-In-Line Metal Seal Packages (SBDIP) c1 -A- BASE METAL E -BC A-B S INCHES SECTION A-A D S D BASE PLANE Q S2 -C- SEATING PLANE A L S1 eA A A b2 b ccc M C A - B S e eA/2 c aaa M C A - B S D S D S MILLIMETERS (c) b1 M (b) M bbb S D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C) 8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE LEAD FINISH -D- NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. SYMBOL MIN MAX MIN MAX A - 0.200 b 0.014 0.026 0.36 b1 0.014 0.023 b2 0.045 0.065 b3 0.023 c 0.008 c1 D - 5.08 - 0.66 2 0.36 0.58 3 1.14 1.65 - 0.045 0.58 1.14 4 0.018 0.20 0.46 2 0.008 0.015 0.20 - 0.405 E 0.220 e 0.310 5.59 0.100 BSC NOTES 0.38 3 10.29 - 7.87 - 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - N 8 5. Dimension Q shall be measured from the seating plane to the base plane. 0.038 8 2 8 Rev. 0 4/94 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN7952.0 May 29, 2012