TM No. AN9738 Intersil Multimedia September 1997 Video Module Interface (VMI) for ICs Author: Keith Jack Introduction VMI does not define a specific pixel clock rate. However, most rectangular pixel applications sample each line of video at 13.5MHz, generating 720 active samples of 24-bit 4:4:4 YCbCr data, as shown in Figures 3 and 4. This is converted to 16-bit 4:2:2 YCbCr data, resulting in 720 active samples of Y per line, and 360 active samples each of Cb and Cr per line. The Y data and the CbCr data are multiplexed, and the 13.5MHz sample clock rate is increased by two to 27MHz. VMI was developed in cooperation with several multimedia IC companies in order to standardize the video interfaces between devices such as MPEG decoders, NTSC/PAL decoders, and GUI accelerators. It is primarily based on the output interface and timing of the Philip's SAA7111 NTSC/PAL decoder. VMI also does not define any horizontal or vertical blanking intervals, using instead a programmable blanking signal (VACTIVE). For most rectangular pixel applications, the vertical blanking intervals will be as shown in Figures 5 and 6. Note that active resolutions other than 720 x 486 and 720 x 576 may be supported (effectively cropping the image) by adjusting the timing of VACTIVE. Video Data Format An 8-bit 4:2:2 YCbCr interface is normally used, similar to that used by the BT.656 parallel interface. However, the EAV and SAV sequences that BT.656 uses are not present. The 4:2:2 YCbCr data is multiplexed into an 8-bit stream: Cb0Y0Cr0Y1Cb2Y2Cr2, etc. Figures 1 and 2 illustrate the format for 525/60 and 625/50 video systems, respectively, using 8-bit YCbCr data. Square Pixel Variation A variation using square pixels may also be used. Instead of a 27MHz clock, a 24.54MHz clock is used for 525/60 video systems (640 x 480 active resolution), and a 29.5MHz clock is used for 625/50 video systems (768 x 576 active resolution). The stream of active data words always begins with a Cb sample. In the multiplexed sequence, the co-sited samples (those that correspond to the same point on the picture) are grouped as Cb, Y, Cr. VACTIVE CONTROL SIGNAL NEXT LINE START OF DIGITAL ACTIVE LINE BLANKING 8 0 1 0 8 0 1 0 8 0 1 0 8 0 1 0 CO-SITED 8 0 1 0 8 0 1 0 8 0 1 0 C B Y C R CO-SITED Y C B Y C R Y C Y R 8 0 DIGITAL VIDEO STREAM 1440 1716 FIGURE 1. TYPICAL VMI 8-BIT DATA FORMAT FOR RECTANGULAR PIXEL 525/60 VIDEO SYSTEMS 1-888-INTERSIL or 321-724-7143 1 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved Application Note 9738 VACTIVE CONTROL SIGNAL NEXT LINE START OF DIGITAL ACTIVE LINE BLANKING 8 0 1 0 8 0 1 0 8 0 1 0 8 0 1 0 CO-SITED 8 0 1 0 8 0 1 0 8 0 1 0 C B Y C R CO-SITED Y C B Y C R Y C Y R 8 0 DIGITAL VIDEO STREAM 1440 1728 FIGURE 2. TYPICAL VMI 8-BIT DATA FORMAT FOR RECTANGULAR PIXEL 625/50 VIDEO SYSTEMS T = 1/13.5MHz T = 1/13.5MHz 12T 16T 50% SYNC LEVEL 50% SYNC LEVEL DIGITAL BLANKING DIGITAL ACTIVE LINE 138T (720-857) 720T (0-719) DIGITAL BLANKING DIGITAL ACTIVE LINE 144T (720-863) 720T (0-719) TOTAL LINE TOTAL LINE 864T (0-863) 858T (0-857) FIGURE 3. TYPICAL VMI HORIZONTAL TIMING RELATIONSHIP FOR RECTANGULAR PIXEL 525/60 VIDEO SYSTEMS FIGURE 4. TYPICAL VMI HORIZONTAL TIMING RELATIONSHIP FOR RECTANGULAR PIXEL 625/50 VIDEO SYSTEMS Figures 7 and 8 illustrate the data format, Figures 9 and 10 illustrate the typical horizontal timing relationships, and Figures 11 and 12 show the typical vertical blanking intervals. VREF and HREF can be considered to be VSYNC and HSYNC signals, respectively. If HREF is high during the falling edge of VREF, the field is odd. If HREF is low during the falling edge of VREF, the field is even. Thus, even/odd field detection is done using the trailing edge of VREF, rather than the leading edge, as with most video systems. Figures 15 and 16 illustrate the HREF and VREF timing for 525/60 and 65/50 video systems, respectively. 16-Bit YCbCr Variation Although not a part of the VMI specification, a variation using 16-bit 4:2:2 YCbCr data is common, as shown in Figures 13 and 14. In this instance, the PIXCLK signal is one-half the normal clock rate: 13.5MHz, 12.27MHz (square pixel 525/60 video systems) or 14.75MHz (square pixel 625/50 video systems). VACTIVE can be considered a blanking signal, and indicates that valid pixel data is being transmitted across the YCbCr bus. If a DVALID signal is also used, valid pixel data is present when both VACTIVE and DVALID are asserted. Video Timing Signals For 8-bit YCbCr interfaces, PIXCLK is a 2x pixel clock. For 16-bit YCbCr interfaces, PIXCLK is a 1x pixel clock. In addition to the pixel data, there are four video timing signals, consisting of VREF, HREF, VACTIVE, and PIXCLK. To support video sources that do not generate a line-locked clock, a Data Valid signal (DVALID) is also commonly used. 2 Application Note 9738 LINE 1 (VACTIVE = 0) LINE 4 BLANKING LINE 20 (VACTIVE = 1) ODD FIELD FIELD 1 ACTIVE VIDEO LINE 264 (VACTIVE = 0) LINE 266 BLANKING LINE 283 (VACTIVE = 1) EVEN FIELD FIELD 2 ACTIVE VIDEO LINE NUMBER FIELD VACTIVE 1-3 1 0 4-19 0 0 21-263 0 1 264-265 0 0 266-282 1 0 283-525 1 1 LINE 525 (VACTIVE = 1) LINE 3 VACTIVE =0 VACTIVE =1 FIGURE 5. TYPICAL VMI VERTICAL BLANKING INTERVALS FOR RECTANGULAR PIXEL 525/60 VIDEO SYSTEMS LINE 1 LINE 1 (VACTIVE = 0) BLANKING LINE 23 (VACTIVE = 1) ODD FIELD LINE NUMBER FIELD 1 ACTIVE VIDEO LINE 311 (VACTIVE = 0) LINE 313 BLANKING LINE 336 (VACTIVE = 1) FIELD 2 ACTIVE VIDEO EVEN FIELD FIELD VACTIVE 1-22 0 0 23-310 0 1 311-312 0 0 313-335 1 0 336-623 1 1 624-625 1 0 LINE 624 (VACTIVE = 0) BLANKING LINE 625 VACTIVE =0 VACTIVE =1 FIGURE 6. TYPICAL VMI VERTICAL BLANKING INTERVALS FOR RECTANGULAR PIXEL 625/50 VIDEO SYSTEMS 3 Application Note 9738 VACTIVE CONTROL SIGNAL NEXT LINE START OF DIGITAL ACTIVE LINE BLANKING 8 0 1 0 8 0 1 0 8 0 1 0 8 0 1 0 CO-SITED 8 0 1 0 8 0 1 0 8 0 1 0 C B Y C R CO-SITED Y C B Y C R Y C Y R 8 0 DIGITAL VIDEO STREAM 1280 1560 FIGURE 7. TYPICAL VMI DATA FORMAT FOR SQUARE PIXEL 525/60 VIDEO SYSTEMS VACTIVE CONTROL SIGNAL NEXT LINE START OF DIGITAL ACTIVE LINE BLANKING 8 0 1 0 8 0 1 0 8 0 1 0 8 0 1 0 CO-SITED 8 0 1 0 8 0 1 0 8 0 1 0 C B Y C R CO-SITED Y C B Y C R Y C Y 8 R 0 DIGITAL VIDEO STREAM 1536 1888 FIGURE 8. TYPICAL VMI DATA FORMAT FOR SQUARE PIXEL 625/50 VIDEO SYSTEMS T = 1/14.75MHz T = 1/12.27MHz 12T 16T 50% SYNC LEVEL 50% SYNC LEVEL DIGITAL BLANKING DIGITAL ACTIVE LINE 140T (640-779) 640T (0-639) DIGITAL BLANKING DIGITAL ACTIVE LINE 176T (768-943) 768T (0-767) TOTAL LINE TOTAL LINE 944T (0-943) 780T (0-779) FIGURE 9. TYPICAL VMI HORIZONTAL TIMING RELATIONSHIP FOR SQUARE PIXEL 525/60 VIDEO SYSTEMS FIGURE 10. TYPICAL VMI HORIZONTAL TIMING RELATIONSHIP FOR SQUARE PIXEL 625/50 VIDEO SYSTEMS 4 Application Note 9738 LINE 1 (VACTIVE = 0) LINE 4 BLANKING LINE 23 (VACTIVE = 1) ODD FIELD FIELD 1 ACTIVE VIDEO LINE 263 (VACTIVE = 0) LINE 266 BLANKING LINE 286 (VACTIVE = 1) EVEN FIELD FIELD 2 ACTIVE VIDEO LINE NUMBER FIELD VACTIVE 1-3 1 0 4-22 0 0 23-262 0 1 263-265 0 0 266-285 1 0 286-525 1 1 LINE 525 (VACTIVE = 1) LINE 3 VACTIVE =0 VACTIVE =1 FIGURE 11. TYPICAL VMI VERTICAL BLANKING INTERVALS FOR SQUARE PIXEL 525/60 VIDEO SYSTEMS LINE 1 LINE 1 (VACTIVE = 0) BLANKING LINE 23 (VACTIVE = 1) ODD FIELD FIELD 1 ACTIVE VIDEO LINE 311 (VACTIVE = 0) LINE 313 BLANKING LINE 336 (VACTIVE = 1) FIELD 2 ACTIVE VIDEO EVEN FIELD LINE NUMBER FIELD VACTIVE 1-22 0 0 23-310 0 1 311-312 0 0 313-335 1 0 336-623 1 1 624-625 1 0 LINE 624 (VACTIVE = 0) BLANKING LINE 625 VACTIVE =0 VACTIVE =1 FIGURE 12. TYPICAL VMI VERTICAL BLANKING INTERVALS FOR SQUARE PIXEL 625/50 VIDEO SYSTEMS 5 Application Note 9738 VACTIVE CONTROL SIGNAL NEXT LINE START OF DIGITAL ACTIVE LINE BLANKING 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Y Y Y Y Y Y Y Y Y Y 1 0 DIGITAL VIDEO STREAM C B C R C B C R DIGITAL VIDEO STREAM 720 858 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 C B C R C B C R C C B R 8 0 FIGURE 13. TYPICAL VMI 16-BIT DATA FORMAT FOR RECTANGULAR PIXEL 525/60 VIDEO SYSTEMS VACTIVE CONTROL SIGNAL NEXT LINE START OF DIGITAL ACTIVE LINE BLANKING 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Y Y Y Y Y Y Y Y Y Y 1 0 DIGITAL VIDEO STREAM C B C R C B C R DIGITAL VIDEO STREAM 720 864 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 8 0 C B C R C B C R C C B R 8 0 FIGURE 14. TYPICAL VMI 16-BIT DATA FORMAT FOR RECTANGULAR PIXEL 625/50 VIDEO SYSTEMS 6 Application Note 9738 523 524 525 1 2 3 4 5 6 7 8 9 10 21 HREF VREF 261 262 263 264 265 266 267 268 269 270 271 272 283 273 HREF VREF FIGURE 15. HREF AND VREF TIMING FOR 525/60 VIDEO SYSTEMS 620 621 622 623 624 625 1 2 3 4 5 6 7 23 HREF VREF 308 309 310 311 312 313 314 315 316 317 318 HREF VREF FIGURE 16. HREF AND VREF TIMING FOR 625/50 VIDEO SYSTEMS 7 319 320 336 284 Application Note 9738 Data Limits Some video sources indicate sync timing by having Y data be a value of less than 16. However, most video ICs do not do this. In addition, to allow real-world video and test signals to be passed through with minimum disruption, many ICs now allow the Y data to have a value less than 16 during active video. Thus, receiver designs assuming sync timing will be present on the Y channel will no longer work. YCbCr and blanking data should not use the 8-bit values of 00H and FFH since those values are used for timing information in BT.656 systems. For 10-bit systems, the 10-bit values 000H–003H and 3FCH–3FFH should not be used to avoid contention with 8-bit BT.656 systems. During blanking intervals, Y values should be set to 10H (040H if a 10-bit system) and CbCr values set to 80H (200H if a 10-bit system). To support video sources that do not generate a line-locked clock, the Data Valid signal (DVALID) is commonly supported. When both VACTIVE and DVALID are asserted, valid pixel data is present. Implementation Considerations Video IC Sources Video IC Receivers HREF and VREF have some unique output hold timings thus, designers must be careful in designing VMI output interfaces. If these specifications are not met, there may be timing problems. Assumptions should not be made about the number of clock cycles per line or horizontal blanking interval. Otherwise, the implementation may not work with real-world video signal sources that use digital PLLs and proposed variations such as scaled video. Summary To ensure compatibility between various video sources, any horizontal counters should be reset by the leading edge of HREF, and not by the trailing edge of VACTIVE. Any vertical counters to count lines within a field should be reset by the leading edge of VREF. This Application Note presented some of the capabilities and issues of the Video Module Interface. Video ICs that support VMI, such as the HMP8115 NTSC/PAL decoder, ease system design by simplifying video interfacing issues. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. 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