LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TimerBlox: Monostable Pulse Generator (One Shot) Features Description Pulse Width Range: 1µs to 33.6 Seconds nn Configured with 1 to 3 Resistors nn Pulse Width Max Error: nn <2.3% for Pulse Width > 512µs nn <3.4% for Pulse Width of 8µs to 512µs nn <4.9% for Pulse Width of 1µs to 8µs nn Four LTC6993 Options Available: nn Rising-Edge or Falling-Edge Trigger nn Retriggerable or Non-Retriggerable nn Configurable for Positive or Negative Output Pulse nn Fast Recovery Time nn 2.25V to 5.5V Single Supply Operation nn 70µA Supply Current at 10µs Pulse Width nn 500µs Start-Up Time nn CMOS Output Driver Sources/Sinks 20mA nn –55°C to 125°C Operating Temperature Range nn Available in Low Profile (1mm) SOT-23 (ThinSOT™) and 2mm × 3mm DFN The LTC®6993 is a monostable multivibrator (also known as a “one-shot” pulse generator) with a programmable pulse width of 1µs to 33.6 seconds. The LTC6993 is part of the TimerBlox® family of versatile silicon timing devices. nn Applications Watchdog Timer Frequency Discriminators nn Missing Pulse Detection nn Envelope Detection nn High Vibration, High Acceleration Environments nn Portable and Battery-Powered Equipment nn nn L, LT, LTC, LTM, Linear Technology, TimerBlox and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. A single resistor, RSET, programs an internal master oscillator frequency, setting the LTC6993’s time base. The output pulse width is determined by this master oscillator and an internal clock divider, NDIV , programmable to eight settings from 1 to 221. NDIV • RSET • 1µs, NDIV = 1, 8, 64,...,221 50kΩ The output pulse is initiated by a transition on the trigger input (TRIG). Each part can be configured to generate positive or negative output pulses. The LTC6993 is available in four versions to provide different trigger signal polarity and retrigger capability. tOUT = DEVICE LTC6993-1 LTC6993-2 LTC6993-3 LTC6993-4 INPUT POLARITY Rising-Edge Rising-Edge Falling-Edge Falling-Edge RETRIGGER No Yes No Yes The LTC6993 also offers the ability to dynamically adjust the width of the output pulse via a separate control voltage. For easy configuration of the LTC6993, download the TimerBlox Designer tool at www.linear.com/timerblox. Typical Application Envelope Detector MODULATED CARRIER TRIG OUT LTC6993-2 GND 80kHz CARRIER SIGNAL ENVELOPE 3.3V V+ 16µs 0.1µF RSET 800k SET TRIG 2V/DIV DIV OUT 2V/DIV 69931234 TA01a 50µs/DIV 69931234 TA01b 69931234fc For more information www.linear.com/LTC6993-1 1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Absolute Maximum Ratings (Note 1) Supply Voltage (V+) to GND.........................................6V Maximum Voltage on Any Pin .................................. (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V) Operating Temperature Range (Note 2) LTC6993C.............................................–40°C to 85°C LTC6993I..............................................–40°C to 85°C LTC6993H........................................... –40°C to 125°C LTC6993MP........................................ –55°C to 125°C Specified Temperature Range (Note 3) LTC6993C................................................. 0°C to 70°C LTC6993I..............................................–40°C to 85°C LTC6993H........................................... –40°C to 125°C LTC6993MP........................................ –55°C to 125°C Junction Temperature............................................ 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) S6 Package........................................................ 300°C Pin Configuration TOP VIEW V+ 1 DIV 2 TOP VIEW 6 OUT 7 5 GND TRIG 1 6 OUT GND 2 5 V+ SET 3 4 DIV 4 TRIG SET 3 DCB PACKAGE 6-LEAD (2mm × 3mm) PLASTIC DFN S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 64°C/W, θJC = 10.6°C/W EXPOSED PAD (PIN 7) CONNECTED TO GND, PCB CONNECTION OPTIONAL TJMAX = 150°C, θJA = 192°C/W, θJC = 51°C/W Order Information Lead Free Finish TAPE AND REEL (MINI) PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6993CDCB-1#TRMPBF LTC6993CDCB-1#TRPBF LDXH 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C LTC6993IDCB-1#TRMPBF LDXH 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C LTC6993HDCB-1#TRMPBF LTC6993HDCB-1#TRPBF LDXH 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C LTC6993CDCB-2#TRMPBF LTC6993CDCB-2#TRPBF LDXK 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C LTC6993IDCB-2#TRMPBF LDXK 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C LTC6993HDCB-2#TRMPBF LTC6993HDCB-2#TRPBF LDXK 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C LTC6993CDCB-3#TRMPBF LTC6993CDCB-3#TRPBF LFMJ 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C LTC6993IDCB-3#TRMPBF LFMJ 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C LTC6993HDCB-3#TRMPBF LTC6993HDCB-3#TRPBF LFMJ 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C LTC6993CDCB-4#TRMPBF LTC6993CDCB-4#TRPBF LFMM 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C LTC6993IDCB-4#TRMPBF LFMM 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C LTC6993HDCB-4#TRMPBF LTC6993HDCB-4#TRPBF LFMM 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C LTC6993CS6-1#TRMPBF LTC6993CS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 0°C to 70°C LTC6993IS6-1#TRMPBF LTC6993IS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6993HS6-1#TRMPBF LTC6993HS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 –40°C to 125°C 2 TAPE AND REEL LTC6993IDCB-1#TRPBF LTC6993IDCB-2#TRPBF LTC6993IDCB-3#TRPBF LTC6993IDCB-4#TRPBF 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Order Information Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6993CS6-2#TRMPBF LTC6993CS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 0°C to 70°C LTC6993IS6-2#TRMPBF LTC6993IS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6993HS6-2#TRMPBF LTC6993HS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 –40°C to 125°C LTC6993CS6-3#TRMPBF LTC6993CS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 0°C to 70°C LTC6993IS6-3#TRMPBF LTC6993IS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6993HS6-3#TRMPBF LTC6993HS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 –40°C to 125°C LTC6993CS6-4#TRMPBF LTC6993CS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 0°C to 70°C LTC6993IS6-4#TRMPBF LTC6993IS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 –40°C to 85°C LTC6993HS6-4#TRMPBF LTC6993HS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 –40°C to 125°C LTC6993MPS6-1#TRMPBF LTC6993MPS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 –55°C to 125°C LTC6993MPS6-2#TRMPBF LTC6993MPS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 –55°C to 125°C LTC6993MPS6-3#TRMPBF LTC6993MPS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 –55°C to 125°C LTC6993MPS6-4#TRMPBF LTC6993MPS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 –55°C to 125°C TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted. SYMBOL PARAMETER tOUT Output Pulse Width ∆tOUT Pulse Width Accuracy (Note 4) CONDITIONS MIN TYP MAX UNITS 33.55 sec ±1.7 ±2.3 ±3.0 % % ±2.4 ±3.4 ±4.4 % % ±3.6 ±4.9 ±6.0 % % ±4.0 ±5.3 ±6.4 % % 1µ NDIV ≥ 512 l 8 ≤ NDIV ≤ 64 l NDIV = 1 (LTC6993-1 or LTC6993-2) l NDIV = 1 (LTC6993-3 or LTC6993-4) l ∆tOUT/∆T Pulse Width Drift Over Temperature NDIV ≥ 512 NDIV ≤ 64 l l ±0.006 ±0.008 Pulse Width Change With Supply V+ = 4.5V to 5.5V NDIV ≥ 512 V+ = 2.25V to 4.5V l l –0.6 –0.4 –0.2 –0.1 V+ = 4.5V to 5.5V 8 ≤ NDIV ≤ 64 V+ = 2.7V to 4.5V V+ = 2.25V to 2.7V l l l –0.9 –0.7 –1.1 –0.2 –0.2 –0.1 %/°C %/°C % % 0.4 0.9 % % % 69931234fc For more information www.linear.com/LTC6993-1 3 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Electrical Characteristics The l denotes the specifications which apply over the full operating + temperature range, otherwise specifications are at TA = 25°C. Test conditions are V = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted. SYMBOL tS PARAMETER CONDITIONS Pulse Width Jitter (Note 10) V+ = 5.5V NDIV = 1 V+ = 2.25V MIN 0.85 0.45 %P-P %P-P NDIV = 8 0.20 %P-P NDIV = 64 0.05 %P-P NDIV = 512 0.20 %P-P NDIV = 4096 0.03 %P-P Pulse Width Change Settling Time (Note 9) tMASTER = tOUT/NDIV TYP MAX 6 • tMASTER UNITS µs Power Supply V+ IS(IDLE) Operating Supply Voltage Range l Power-On Reset Voltage l Supply Current (Idle) 2.25 5.5 V 1.95 V RL = ∞, RSET = 50k, NDIV ≤ 64 V+ = 5.5V V+ = 2.25V l l 165 125 200 160 µA µA RL = ∞, RSET = 50k, NDIV ≥ 512 V+ = 5.5V V+ = 2.25V l l 135 105 175 140 µA µA RL = ∞, RSET = 800k, NDIV ≤ 64 V+ = 5.5V V+ = 2.25V l l 70 60 110 95 µA µA RL = ∞, RSET = 800k, NDIV ≥ 512 V+ = 5.5V V+ = 2.25V l l 65 55 100 90 µA µA 1.00 1.03 V Analog Inputs VSET Voltage at SET Pin ∆VSET/∆T VSET Drift Over Temperature l RSET Frequency-Setting Resistor l VDIV DIV Pin Voltage ∆VDIV/∆V+ DIV Pin Valid Code Range (Note 5) l DIV Pin Input Current ±75 µV/°C 50 800 kΩ 0 V+ V l ±1.5 % l ±10 nA l Deviation from Ideal VDIV/V+ = (DIVCODE + 0.5)/16 0.97 Digital I/O TRIG Pin Input Capacitance VIH 2.5 TRIG Pin Input Current TRIG = 0V to V+ High Level TRIG Pin Input Voltage (Note 6) ±10 l VIL Low Level TRIG Pin Input Voltage (Note 6) IOUT(MAX) Output Current V+ = 2.7V to 5.5V VOH High Level Output Voltage (Note 7) V+ = 5.5VIOUT = –1mA IOUT = –16mA l l V+ = 3.3VIOUT = –1mA IOUT = –10mA VOL 4 Low Level Output Voltage (Note 7) pF 0.7 • V+ nA V 0.3 • V+ l V ±20 mA 5.45 4.84 5.48 5.15 V V l l 3.24 2.75 3.27 2.99 V V V+ = 2.25VIOUT = –1mA IOUT = –8mA l l 2.17 1.58 2.21 1.88 V V V+ = 5.5VIOUT = 1mA IOUT = 16mA l l 0.02 0.26 0.04 0.54 V V V+ = 3.3VIOUT = 1mA IOUT = 10mA l l 0.03 0.22 0.05 0.46 V V V+ = 2.25VIOUT = 1mA IOUT = 8mA l l 0.03 0.26 0.07 0.54 V V 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Electrical Characteristics The l denotes the specifications which apply over the full operating + temperature range, otherwise specifications are at TA = 25°C. Test conditions are V = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted. SYMBOL PARAMETER CONDITIONS tPD Trigger Propagation Delay V+ = 5.5V V+ = 3.3V V+ = 2.25V MIN TYP 11 17 28 MAX UNITS ns ns ns tWIDTH Minimum Recognized TRIG Pulse Width V+ = 3.3V 5 ns –4 ns 10 50 ns ns tARM Recovery Time (LTC6993-1/LTC6993-3) tRETRIG Time Between Trigger Signals (LTC6993-2/LTC6993-4) NDIV = 1 NDIV > 1 tr Output Rise Time (Note 8) V+ = 5.5V V+ = 3.3V V+ = 2.25V 1.1 1.7 2.7 ns ns ns tf Output Fall Time (Note 8) V+ = 5.5V V+ = 3.3V V+ = 2.25V 1.0 1.6 2.4 ns ns ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6993C is guaranteed functional over the operating temperature range of –40°C to 85°C. Note 3: The LTC6993C is guaranteed to meet specified performance from 0°C to 70°C. The LTC6993C is designed, characterized and expected to meet specified performance from –40°C to 85°C but it is not tested or QA sampled at these temperatures. The LTC6993I is guaranteed to meet specified performance from –40°C to 85°C. The LTC6993H is guaranteed to meet specified performance from –40°C to 125°C. The LTC6993MP is guaranteed to meet specified performance from –55°C to 125°C. Note 4: Pulse width accuracy is defined as the deviation from the tOUT equation, assuming RSET is used to program the pulse width. Note 5: See Operation section, Table 1 and Figure 2 for a full explanation of how the DIV pin voltage selects the value of DIVCODE. V+ = 3.3V V+ = 3.3V Note 6: The TRIG pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V+. Typical values can be estimated at any supply voltage using: VTRIG(RISING) ≈ 0.55 • V+ + 185mV and VTRIG(FALLING) ≈ 0.48 • V+ – 155mV Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrarily given a negative value. Note 8: Output rise and fall times are measured between the 10% and the 90% power supply levels with 5pF output load. These specifications are based on characterization. Note 9: Settling time is the amount of time required for the output to settle within ±1% of the final pulse width after a 0.5× or 2× change in ISET . Note 10: Jitter is the ratio of the deviation of the output pulse width to the mean of the pulse width. This specification is based on characterization and is not 100% tested. 69931234fc For more information www.linear.com/LTC6993-1 5 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Typical Performance Characteristics V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted. tOUT Drift vs Temperature (NDIV ≤ 64) 1.5 1.5 RSET = 50k 3 PARTS 1.0 1.5 RSET = 200k 3 PARTS 1.0 0.5 DRIFT (%) 0 0 –0.5 –0.5 –1.0 –1.0 –1.0 50 25 75 0 TEMPERATURE (°C) 100 –1.5 –50 –25 125 50 25 75 0 TEMPERATURE (°C) 100 69931234 G01 1.5 1.5 0.5 0 0 –0.5 –0.5 –0.5 –1.0 –1.0 –1.0 50 25 75 0 TEMPERATURE (°C) 100 –1.5 –50 –25 125 50 25 75 0 TEMPERATURE (°C) 100 1.0 0.6 1.0 1.0 0.6 0.6 0.2 0.2 0.2 –0.2 2 3 4 SUPPLY (V) 5 69931234 G07 –1.0 –0.6 RSET = 50k RSET = 200k RSET = 800k –0.8 6 0 –0.2 –0.4 –0.6 RSET = 50k RSET = 200k RSET = 800k –0.8 6 0 –0.4 –0.6 –1.0 DRIFT (%) 0.4 DRIFT (%) 0.4 –0.4 125 REFERENCED TO V+ = 4V 0.8 0.4 –0.2 100 tOUT Drift vs Supply Voltage (NDIV > 1) LTC6993-3/LTC6993-4 DIVCODE = 0 REFERENCED TO V+ = 4V 0.8 0 50 25 75 0 TEMPERATURE (°C) 69931234 G06 tOUT Drift vs Supply Voltage (NDIV = 1, Falling Edge) LTC6993-1/LTC6993-2 DIVCODE = 0 REFERENCED TO V+ = 4V 0.8 –1.5 –50 –25 125 69931234 G05 69931234 G04 tOUT Drift vs Supply Voltage (NDIV = 1, Rising Edge) 125 RSET = 800k 3 PARTS 1.0 DRIFT (%) DRIFT (%) DRIFT (%) 1.5 0.5 0.5 –1.5 –50 –25 100 tOUT Drift vs Temperature (NDIV ≥ 512) RSET = 200k 3 PARTS 1.0 0 50 25 75 0 TEMPERATURE (°C) 69931234 G03 tOUT Drift vs Temperature (NDIV ≥ 512) RSET = 50k 3 PARTS 1.0 –1.5 –50 –25 125 69931234 G02 tOUT Drift vs Temperature (NDIV ≥ 512) DRIFT (%) 0 –0.5 –1.5 –50 –25 RSET = 800k 3 PARTS 1.0 0.5 DRIFT (%) 0.5 DRIFT (%) tOUT Drift vs Temperature (NDIV ≤ 64) tOUT Drift vs Temperature (NDIV ≤ 64) 2 3 4 SUPPLY (V) 5 RSET = 50k, NDIV = 8 RSET = 50k TO 800k, NDIV ≥ 512 RSET = 800k, NDIV = 8 –0.8 6 69931234 G08 –1.0 2 3 4 SUPPLY (V) 5 6 69931234 G09 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Typical Performance Characteristics + V = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted. tOUT Error vs RSET (NDIV = 1, Rising Edge) 5 4 5 3 PARTS 4 2 2 1 1 1 ERROR (%) –1 ERROR (%) 3 2 0 0 –1 –2 –3 –3 –3 –4 –4 –4 –5 –5 200 RSET (kΩ) 400 800 100 50 200 RSET (kΩ) 400 5 5 3 3 2 1 1 1 ERROR (%) 2 0 0 –1 –2 –2 0 –1 –2 –3 –3 –3 –4 –4 –4 –5 50 100 200 RSET (kΩ) 400 –5 800 0 2 4 6 8 10 DIVCODE 12 69931234 G13 VSET Drift vs Supply Voltage 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 DRIFT (mV) 1.0 0 –0.2 –0.6 –0.6 0 5 10 ISET (µA) 15 20 69931234 G16 4 6 8 10 DIVCODE 14 3 PARTS 1.010 1.005 1.000 0.995 0.990 –0.8 –1.0 12 1.015 0 –0.4 –1.0 2 VSET vs Temperature 1.020 –0.2 –0.4 REFERENCED TO ISET = 10µA 0 69931234 G15 VSET (V) VSET Drift vs ISET –0.8 –5 14 69931234 G14 1.0 800 LTC6993-3/LTC6993-4 RSET = 50k 3 PARTS 4 2 –1 400 tOUT Error vs DIVCODE (Falling Edge) LTC6993-1/LTC6993-2 RSET = 50k 3 PARTS 4 ERROR (%) ERROR (%) 3 200 RSET (kΩ) 69931234 G12 tOUT Error vs DIVCODE (Rising Edge) LTC6993-3/LTC6993-4 DIVCODE = 0 3 PARTS 4 100 50 69931234 G11 tOUT Error vs RSET (NDIV = 1, Falling Edge) 5 –5 800 69931234 G10 VSET (mV) –1 –2 100 3 PARTS 0 –2 50 tOUT Error vs RSET (NDIV ≥ 512) 4 3 3 ERROR (%) 5 LTC6993-1/LTC6993-2 DIVCODE = 0 3 PARTS tOUT Error vs RSET (8 ≤ NDIV ≤ 64) 0.985 REFERENCED TO V+ = 4V 2 3 4 SUPPLY (V) 6 5 69931234 G17 0.980 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 69931234 G18 69931234fc For more information www.linear.com/LTC6993-1 7 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Typical Performance Characteristics V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted. 2 LOTS DFN AND SOT-23 1274 UNITS 150 100 50 0 0.98 0.996 1.004 VSET (V) 0.988 1.012 “ACTIVE” = 50% TIMING DUTY CYCLE 250 RSET = 50k ÷1, ACTIVE 200 RSET = 50k ÷1, IDLE 150 RSET = 100k, ÷8, ACTIVE 100 RSET = 100k, ÷8, IDLE 50 0 1.02 RSET = 800k, ÷512 CLOAD = 5pF RLOAD = ∞ 2 3 5V TRIG RISING 3.3V TRIG RISING 3.3V TRIG FALLING 50 CLOAD = 5pF RLOAD = ∞ 0 0.2 0.6 0.4 VTRIG/V+ (V/V) 0.8 POWER SUPPLY CURRENT (µA) POWER SUPPLY CURRENT (µA) 250 100 0 1.0 RSET = 100k, ÷8, ACTIVE 100 RSET = 100k, ÷8, IDLE 50 –25 RSET = 800k, ÷512 0 25 50 75 TEMPERATURE (°C) ÷1 ÷8 150 ÷64 ÷512 100 50 V+ = 5V CLOAD = 5pF RLOAD = ∞ 0 0.01 0.001 250 ACTIVE IDLE 0.1 1 tOUT (ms) 10 100 0.9 3.0 0.8 POSITIVE GOING 2.5 PEAK-TO-PEAK tOUT VARIATION MEASURED OVER 30s INTERVALS ÷1, 5.5V 125 ACTIVE CURRENT MEASURED WITH TRIGGER PERIOD = 2 • tOUT (50% DUTY CYCLE) 200 150 ÷1 ÷8 100 50 V+ = 2.5V CLOAD = 5pF RLOAD = ∞ 0 0.01 0.001 ÷64 ÷512 ACTIVE IDLE 0.1 1 tOUT (ms) 10 100 69931234 G24 Typical ISET Current Limit vs V+ Peak-to-Peak Jitter vs tOUT 1.0 100 69931234 G21 69931234 G23 3.5 1000 SET PIN SHORTED TO GND 800 0.7 NEGATIVE GOING 1.5 0.6 0.5 0.4 0.3 1.0 ISET (µA) 2.0 JITTER (%P-P) RST PIN VOLTAGE (V) RSET = 50k, ÷1, IDLE Supply Current vs tOUT (2.5V) ACTIVE CURRENT MEASURED WITH TRIGGER PERIOD = 2 • tOUT (50% DUTY CYCLE) 200 TRIG Threshold Voltage vs Supply Voltage ÷1, 2.25V 0.1 2 3 4 5 SUPPLY VOLTAGE (V) 6 69931234 G25 0 0.001 600 400 ÷8, 5.5V ÷512 0.2 0.5 8 150 0 –50 6 69931234 G22 0 RSET = 50k, ÷1, ACTIVE Supply Current vs tOUT (5V) 250 150 200 69931234 G20 Supply Current vs TRIG Pin Voltage 5V TRIG FALLING “ACTIVE” = 50% TIMING DUTY CYCLE CLOAD = 5pF RLOAD = ∞ 4 5 SUPPLY VOLTAGE (V) 69931234 G19 200 Supply Current vs Temperature 250 POWER SUPPLY CURRENT (µA) 200 NUMBER OF UNITS Supply Current vs Supply Voltage 300 POWER SUPPLY CURRENT (µA) Typical VSET Distribution POWER SUPPLY CURRENT (µA) 250 ÷8, 2.25V 0.01 ÷64 0.1 1 tOUT (ms) 200 ÷4096 10 100 69931234 G26 0 2 3 4 5 SUPPLY VOLTAGE (V) 6 69931234 G27 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Typical Performance Characteristics V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted. 30 3.0 CLOAD = 5pF 45 20 15 10 OUTPUT RESISTANCE (Ω) RISE/FALL TIME (ns) PROPAGATION DELAY (ns) 50 CLOAD = 5pF 2.5 25 2.0 tRISE 1.5 tFALL 1.0 0.5 5 0 Output Resistance vs Supply Voltage Rise and Fall Time vs Supply Voltage Trigger Propagation Delay (tPD) vs Supply Voltage 2 3 4 5 SUPPLY VOLTAGE (V) 6 0 40 35 OUTPUT SOURCING CURRENT 30 25 20 OUTPUT SINKING CURRENT 15 10 5 2 3 4 5 SUPPLY VOLTAGE (V) 6 6990 G29 0 2 3 4 5 SUPPLY VOLTAGE (V) 6 69931234 G30 69931234 G28 69931234fc For more information www.linear.com/LTC6993-1 9 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Pin Functions (DCB/S6) V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply should be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1µF capacitor. tolerance and 50ppm/°C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor may be used. DIV (Pin 2/Pin 4): Programmable Divider and Polarity Input. The DIV pin voltage (VDIV) is internally converted into a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V+ and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) determines the polarity of the OUT pins. When POL = 0 the output produces a positive pulse. When POL = 1 the output produces a negative pulse. Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less than 100pF maintains the stability of the feedback circuit regulating the VSET voltage. SET (Pin 3/Pin 3): Pulse Width Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current range is 1.25µA to 20µA. The output pulse will continue indefinitely if ISET drops below approximately 500nA, and will terminate when ISET increases again. A resistor connected between SET and GND is the most accurate way to set the pulse width. For best performance, use a precision metal or thin film resistor of 0.5% or better TRIG (Pin 4/Pin 1): Trigger Input. Depending on the version, a rising or falling edge on TRIG will initiate the output pulse. LTC6993-1 and LTC6993-2 are rising-edge sensitive. LTC6993-3 and LTC6993-4 are falling-edge sensitive. The LTC6993-2 and LTC6993-4 are retriggerable, allowing the pulse width to be extended by additional trigger signals that occur while the output is active. The LTC6993‑1/ LTC6993-3 will ignore additional trigger inputs until the output pulse has terminated. GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground plane for best performance. OUT (Pin 6/Pin 6): Output. The OUT pin swings from GND to V+ with an output resistance of approximately 30Ω. When driving an LED or other low impedance load a series output resistor should be used to limit source/ sink current to 20mA. V+ TRIG OUT LTC6993 GND SET RSET 10 V+ V+ C1 0.1µF R1 DIV 69931234 PF R2 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Block Diagram (S6 package pin numbers shown) 5 V+ R1 4 DIV 4-BIT A/D CONVERTER POL DIGITAL FILTER R2 1 TRIG TRIGGER/ RETRIGGER LOGIC S MASTER OSCILLATOR V 1µs tMASTER = • SET 50kΩ ISET Q MCLK OUTPUT POLARITY OUT 6 PROGRAMMABLE DIVIDER ÷1, 8, 64, 512, 4096, 215, 218, 221 tOUT R POR HALT OSCILLATOR IF ISET < 500nA ISET + – VSET = 1V 1V + – GND SET 3 ISET 2 69931234 BD RSET 69931234fc For more information www.linear.com/LTC6993-1 11 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Operation The LTC6993 is built around a master oscillator with a 1µs minimum period. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1µs/50kΩ conversion factor that is accurate to ±1.7% under typical conditions. 1µs VSET tMASTER = • 50kΩ ISET A feedback loop maintains VSET at 1V ±30mV, leaving ISET as the primary means of controlling the pulse width. The simplest way to generate ISET is to connect a resistor (RSET) between SET and GND, such that ISET = VSET/RSET . The master oscillator equation reduces to: tMASTER = 1µs • DIVCODE The DIV pin connects to an internal, V+ referenced 4-bit A/D converter that determines the DIVCODE value. DIVCODE programs two settings on the LTC6993: 1.DIVCODE determines the frequency divider setting, NDIV . 2.DIVCODE determines the polarity of OUT pin, via the POL bit. VDIV may be generated by a resistor divider between V+ and GND as shown in Figure 1. 2.25V TO 5.5V V+ RSET 50kΩ DIV From this equation, it is clear that VSET drift will not affect the pulse width when using a single program resistor (RSET). Error sources are limited to RSET tolerance and the inherent pulse width accuracy ∆tOUT of the LTC6993. RSET may range from 50k to 800k (equivalent to ISET between 1.25µA and 20µA). A trigger signal (rising or falling edge on TRIG pin) latches the output to the active state, beginning the output pulse. At the same time, the master oscillator is enabled to time the duration of the output pulse. When the desired pulse width is reached, the master oscillator resets the output latch. The LTC6993 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 215, 218 or 221. This extends the pulse width duration by those same factors. The divider ratio NDIV is set by a resistor divider attached to the DIV pin. tOUT = NDIV VSET • • 1µs 50kΩ ISET 12 NDIV • RSET • 1µs 50kΩ R2 GND 69931234 F01 Figure 1. Simple Technique for Setting DIVCODE Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the corresponding NDIV and POL values for the recommended resistor pairs. Other values may be used as long as: 1. The VDIV/V+ ratio is accurate to ±1.5% (including resistor tolerances and temperature effects). 2. The driving impedance (R1||R2) does not exceed 500kΩ. If the voltage is generated by other means (i.e., the output of a DAC) it must track the V+ supply voltage. The last column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: With RSET in place of VSET/ISET the equation reduces to: tOUT = R1 LTC6993 VDIV DIVCODE + 0.5 = ± 1.5% 16 V+ For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint. 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Operation Table 1. DIVCODE Programming DIVCODE POL NDIV Recommended tOUT R1 (k) R2 (k) VDIV /V+ 0 0 1 1µs to 16µs Open Short ≤ 0.03125 ±0.015 1 0 8 8µs to 128µs 976 102 0.09375 ±0.015 2 0 64 64µs to 1.024ms 976 182 0.15625 ±0.015 3 0 512 512µs to 8.192ms 1000 280 0.21875 ±0.015 4 0 4,096 4.096ms to 65.54ms 1000 392 0.28125 ±0.015 5 0 32,768 32.77ms to 524.3ms 1000 523 0.34375 ±0.015 6 0 262,144 262.1ms to 4.194sec 1000 681 0.40625 ±0.015 7 0 2,097,152 2.097sec to 33.55sec 1000 887 0.46875 ±0.015 8 1 2,097,152 2.097sec to 33.55sec 887 1000 0.53125 ±0.015 9 1 262,144 262.1ms to 4.194sec 681 1000 0.59375 ±0.015 10 1 32,768 32.77ms to 524.3ms 523 1000 0.65625 ±0.015 11 1 4,096 4.096ms to 65.54ms 392 1000 0.71875 ±0.015 12 1 512 512µs to 8.192ms 280 1000 0.78125 ±0.015 13 1 64 64µs to 1.024ms 182 976 0.84375 ±0.015 14 1 8 8µs to 128µs 102 976 0.90625 ±0.015 15 1 1 1µs to 16µs Short Open ≥ 0.96875 ±0.015 POL BIT = 0 POL BIT = 1 10000 7 6 1000 9 10 5 100 tOUT (ms) 8 11 4 10 12 3 1 13 2 0.1 1 0.01 0.001 14 0 0V 15 0.5•V+ INCREASING VDIV V+ 69931234 F02 Figure 2. Pulse Width Range and POL Bit vs DIVCODE 69931234fc For more information www.linear.com/LTC6993-1 13 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Operation Monostable Multivibrator (One Shot) Negative Trigger Versions The LTC6993 is a monostable multivibrator. A trigger signal on the TRIG input will force the output to the active (unstable) state for a programmable duration. This type of circuit is commonly referred to as a one-shot pulse generator. In addition to the retrigger option, the LTC6993 family also includes negative input (falling-edge) versions. These four combinations are detailed in Table 2. Table 2. Retrigger and Input Polarity Options DEVICE LTC6993-1 LTC6993-2 LTC6993-3 LTC6993-4 Figures 3 details the basic operation. A rising edge on the TRIG pin initiates the output pulse. The pulse width (tOUT) is determined by the NDIV setting and by the resistor (RSET) connected to the SET pin. Subsequent rising edges on TRIG have no affect until the completion of the one shot and for a short rearming time (tARM) thereafter. To ensure proper operation, positive and negative TRIG pulses should be at least tWIDTH wide. INPUT POLARITY Rising-Edge Rising-Edge Falling-Edge Falling-Edge RETRIGGER No Yes No Yes Output Polarity (POL Bit) Each variety of LTC6993 also offers the ability to invert the output, producing negative pulses. This option is programmed, along with NDIV, by the choice of DIVCODE. (The previous section describes how to program DIVCODE using the DIV pin). The LTC6993-2 and LTC6993-4 allow the output pulse to be “retriggered”. As shown in Figure 4, the output pulse will stay high until tOUT after the last rising-edge on TRIG. Successive trigger signals can extend the pulse width indefinitely. Consecutive trigger signals must be separated by tRETRIG to be recognized. tWIDTH TRIG tPD tPD tARM OUT tOUT tOUT 69931234 F03 tOUT Figure 3. Non-Retriggering Timing Diagram (LTC6993-1, POL = 0) t WIDTH t RETRIG TRIG tPD tPD tPD tPD OUT tOUT tOUT tOUT 69931234 F04 Figure 4. Retriggering Timing Diagram (LTC6993-2, POL = 0) 14 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Operation Changing DIVCODE After Start-Up Start-Up Time Following start-up, the A/D converter will continue monitoring VDIV for changes. Changes to DIVCODE will be recognized slowly, as the LTC6993 places a priority on eliminating any “wandering” in the DIVCODE. The typical delay depends on the difference between the old and new DIVCODE settings and is proportional to the master oscillator period. When power is first applied, the power-on reset (POR) circuit will initiate the start-up time, tSTART . The OUT pin is held low during this time. The typical value for tSTART ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV): tDIVCODE = 16 • (∆DIVCODE + 6) • tMASTER A change in DIVCODE will not be recognized until it is stable, and will not pass through intermediate codes. A digital filter is used to guarantee the DIVCODE has settled to a new value before making changes to the output. However, if the output pulse is active during the transition, the pulse width can take on a value between the two settings. DIV 500mV/DIV 512µs TRIG 2V/DIV tSTART(TYP) = 500 • tMASTER During start-up, the DIV pin A/D converter must determine the correct DIVCODE before an output pulse can be generated. The start-up time may increase if the supply or DIV pin voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will properly track V+. Less than 100pF will not extend the start-up time. The DIVCODE setting is recognized at the end of the startup up. If POL = 1, the output will transition high. Otherwise (if POL = 0) OUT simply remains low. At this point, the LTC6993 is ready to respond to rising/falling edges on the TRIG input. 4µs OUT 2V/DIV V+ 256µs LTC6993-1 V+ = 3.3V RSET = 200k 69931234 F05a 200µs/DIV TRIG Figure 5a. DIVCODE Change from 0 to 2 tSTART (TRIG IGNORED) OUT DIV 500mV/DIV POL = 0 POL = 1 tOUT 69931234 F06 512µs Figure 6. Start-Up Timing Diagram TRIG 2V/DIV 4µs OUT 2V/DIV 256µs LTC6993-1 V+ = 3.3V RSET = 200k 200µs/DIV 69931234 F05b Figure 5b. DIVCODE Change from 2 to 0 69931234fc For more information www.linear.com/LTC6993-1 15 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Applications Information Basic Operation Step 4: Calculate and Select RSET. The simplest and most accurate method to program the LTC6993 is to use a single resistor, RSET , between the SET and GND pins. The design procedure is a four step process. Alternatively, Linear Technology offers the easy-to-use TimerBlox Designer tool to quickly design any LTC6993 based circuit. Download the free TimerBlox Designer software at www.linear.com/timerblox. The final step is to calculate the correct value for RSET using the following equation: Step 1: Select the POL Bit Setting. Example: Design a one-shot circuit that satisfies the following requirements: The LTC6993 can generate positive or negative output pulses, depending on the setting of the POL bit. The POL bit is the DIVCODE MSB, so any DIVCODE ≥ 8 has POL = 1 and produces active-low pulses. Step 2: Select LTC6993 Version. Two input-related choices dictate the proper LTC6993 for a given application: • Is TRIG a rising or falling-edge input? As explained earlier, the voltage on the DIV pin sets the DIVCODE which determines both the POL bit and the NDIV value. For a given output pulse width (tOUT), NDIV should be selected to be within the following range: (1) To minimize supply current, choose the lowest NDIV value. However, in some cases a higher value for NDIV will provide better accuracy (see Electrical Characteristics). Table 1 can also be used to select the appropriate NDIV values for the desired tOUT . With POL already chosen, this completes the selection of DIVCODE. Use Table 1 to select the proper resistor divider or VDIV/V+ ratio to apply to the DIV pin. 16 Select the standard resistor value closest to the calculated value. • tOUT = 100µs • Negative Output Pulse • Rising-Edge Trigger Input • Retriggerable Input • Minimum power consumption Step 1: Select the POL Bit Setting. A rising-edge retriggerable input requires the LTC6993‑2. Step 3: Select the NDIV Frequency Divider Value. (2) Step 2: Select the LTC6993 Version. Use Table 2 to select a particular variety of LTC6993. 50k tOUT • 1µs NDIV For inverted (negative) output pulse, choose POL = 1. • Should retriggering be allowed? tOUT t ≤ NDIV ≤ OUT 16µs 1µs RSET = Step 3: Select the NDIV Frequency Divider Value. Choose an NDIV value that meets the requirements of Equation (1), using tOUT = 100µs: 6.25 ≤ NDIV ≤ 100 Potential settings for NDIV include 8 and 64. NDIV = 8 is the best choice, as it minimizes supply current by using a large RSET resistor. POL = 1 and NDIV = 8 requires DIVCODE = 14. Using Table 1, choose R1 = 102k and R2 = 976k values to program DIVCODE = 14. Step 4: Select RSET . Calculate the correct value for RSET using Equation (2): RSET = 50k 100µs • = 625k 1µs 8 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Applications Information Since 625k is not available as a standard 1% resistor, substitute 619k if a –0.97% shift in tOUT is acceptable. Otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. TRIG OUT V+ LTC6993 GND The completed design is shown in Figure 7. RMOD VCTRL SET V+ 69931234 F08 2.25V TO 5.5V Figure 8. Voltage-Controlled Pulse Width V+ 0.1µF SET R1 102k Digital Pulse Width Control DIVCODE = 14 DIV RSET 625k R2 976k The control voltage can be generated by a DAC (digital-toanalog converter), resulting in a digitally-controlled pulse width. Many DACs allow for the use of an external reference. If such a DAC is used to provide the VCTRL voltage, the VSET dependency can be eliminated by buffering VSET and using it as the DAC’s reference voltage, as shown in Figure 9. The DAC’s output voltage now tracks any VSET variation and eliminates it as an error source. The SET pin cannot be tied directly to the reference input of the DAC because the current drawn by the DAC’s REF input would affect the pulse width. 69931234 F07 Figure 7. 100µs Negative Pulse Generator Voltage-Controlled Pulse Width With one additional resistor, the LTC6993 output pulse width can be manipulated by an external voltage. As shown in Figure 8, voltage VCTRL sources/sinks a current through RMOD to vary the ISET current, which in turn modulates the pulse width as described in Equation (3). tOUT = R2 OUT LTC6993-2 GND NDIV • RMOD 1µs • R V 50kΩ 1+ MOD – CTRL RSET VSET (3) TRIG OUT V+ LTC6993 0.1µF V+ + SET DIN CLK CS/LD V VCC GND 69931234 F09 N •R tOUT = DIV MOD • 50kΩ VOUT R1 R2 REF LTC1659 C1 0.1µF DIV – + 0.1µF V+ GND 1/2 LTC6078 µP R1 DIV RSET TRIG C1 0.1µF RMOD DIN = 0 TO 4095 1µs RMOD DIN 1+ – RSET 4096 RSET Figure 9. Digitally Controlled Pulse Width 69931234fc For more information www.linear.com/LTC6993-1 17 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Applications Information ISET Extremes (Master Oscillator Frequency Extremes) Coupling Error When operating with ISET outside of the recommended 1.25µA to 20µA range, the master oscillator operates outside of the 62.5kHz to 1MHz range in which it is most accurate. The current sourced by the SET pin is used to bias the internal master oscillator. The LTC6993 responds to changes in ISET almost immediately, which provides excellent settling time. However, this fast response also makes the SET pin sensitive to coupling from digital signals, such as the TRIG input. The oscillator will still function with reduced accuracy for ISET < 1.25µA. At approximately 500nA, the oscillator will stop. Under this condition, the output pulse can still be initiated, but will not terminate until ISET increases and the master oscillator starts again. At the other extreme, it is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. Settling Time Following a 2× or 0.5× step change in ISET , the output pulse width takes approximately six master clock cycles (6 • tMASTER) to settle to within 1% of the final value. An example is shown in Figure 10, using the circuit in Figure 8. Even an excellent layout will allow some coupling between TRIG and SET. Additional error is included in the specified accuracy for NDIV = 1 to account for this. Figure 11 shows that ÷1 supply variation is dependent on coupling from rising or falling trigger inputs and, to a lesser extent, output polarity. A very poor layout can actually degrade performance further. The PCB layout should avoid routing SET next to TRIG (or any other fast-edge, wide-swing signal). 1.0 0.8 0.6 LTC6993-1 POL = 1 0.4 DRIFT (%) VCTRL 2V/DIV TRIG 5V/DIV OUT 5V/DIV 0.2 0 –0.2 LTC6993-3 POL = 0 –0.4 –0.6 PULSE WIDTH 2µs/DIV RSET = 50k NDIV = 1 –0.8 LTC6993-1 V+ = 3.3V DIVCODE = 0 RSET = 200k RMOD = 464k tOUT = 3µs AND 6µs 20µs/DIV 69931234 F10 LTC6993-1 POL = 0 –1.0 2 3 LTC6993-3 POL = 1 4 SUPPLY (V) 5 6 69931234 F11 Figure 11. tOUT Drift vs Supply Voltage Figure 10. Typical Settling Time 18 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Applications Information Power Supply Current The Electrical Characteristics table specifies the supply current while the part is idle (waiting to be triggered). IS(IDLE) varies with the programmed tOUT and the supply voltage. Once triggered, the instantaneous supply current increases to IS(ACTIVE) while the timing circuit is active. IS(ACTIVE) = IS(IDLE) + ∆IS(ACTIVE) The average increase in supply current ∆IS(ACTIVE) depends on the output duty cycle (or negative duty cycle, if POL = 1), since that represents the percentage of time that the circuit is active. IS(IDLE) and ∆IS(ACTIVE) can be estimated using the equations in Table 2. Figure 12 shows how the supply current increases from IS(IDLE) as the input frequency increases. The increase is smaller at higher NDIV settings. POWER SUPPLY CURRENT (µA) 250 V+ = 3.3V DUTY CYCLE = fIN • tOUT 200 ÷1, RSET = 50k 150 ÷8, RSET = 50k ÷1, RSET = 100k 100 ÷1, RSET = 800k 50 CLOAD = 5pF RLOAD = ∞ 0 IDLE 20 60 40 DUTY CYCLE (%) 80 100 69931234 F12 Figure 12. IS(ACTIVE) vs Output Duty Cycle Table 2. Typical Supply Current CONDITION TYPICAL IS(IDLE) NDIV ≤ 64 V+ • (NDIV • 7pF + 4pF ) V+ + + 2.2 •ISET + 50µA tOUT 500kΩ NDIV ≥ 512 V+ V+ • NDIV • 7pF + + 1.8 •ISET + 50µA tOUT 500kΩ TYPICAL ∆IS(ACTIVE)* V+ • Duty Cycle • (NDIV • 5pF + 18pF + CLOAD ) tOUT V+ • Duty Cycle • CLOAD tOUT *Ignoring resistive loads (assumes RLOAD = ∞) 69931234fc For more information www.linear.com/LTC6993-1 19 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Applications Information Supply Bypassing and PCB Layout Guidelines The LTC6993 is an accurate monostable multivibrator when used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper PCB layout are important to ensure this. Figure 13 shows example PCB layouts for both the SOT-23 and DCB packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6993. These layouts are a guide and need not be followed exactly. 1. Connect the bypass capacitor, C1, directly to the V+ and GND pins using a low inductance path. The connection from C1 to the V+ pin is easily done directly on the top layer. For the DCB package, C1’s connection to GND is also simply done on the top layer. For the SOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that, C1’s GND connection can be accomplished through multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the TRIG C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1µF ceramic capacitor. 2. Place all passive components on the top side of the board. This minimizes trace inductance. 3. Place RSET as close as possible to the SET pin and make a direct, short connection. The SET pin is a current summing node and currents injected into this pin directly modulate the output pulse width. Having a short connection minimizes the exposure to signal pickup. 4. Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 6. Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling. OUT LTC6993 GND SET V+ V+ C1 0.1µF R1 DIV RSET R2 V+ R1 R2 V+ C1 C1 V+ OUT TRIG OUT DIV GND GND V+ SET TRIG SET DIV R1 RSET RSET R2 69931234 F13 DCB PACKAGE TSOT-23 PACKAGE Figure 13. Supply Bypassing and PCB Layout 20 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Typical Applications Missing Pulse Detector TRIG 25kHz INPUT OUT LTC6993-2 TRIG 2V/DIV 3.3V 0.1µF V+ GND R1 102k SET RSET 402k 64µs OUT 2V/DIV DIV R2 976k DIVCODE = 14 (NDIV = 8, POL = 1) 69931234 TA02b 50µs/DIV 69931234 TA02a Use retriggerable one shot with output inverted. Output remains low as long as retrigger occurs within tOUT = 64µs. 1.5ms Radio Control Servo Reference Pulse Generator 5V 20ms FRAME RATE GENERATOR R7 10k RST RESET = OPEN RUN = GND (CLOSED) 1.5ms REFERENCE PULSE 20ms PERIOD TRIG OUT LTC6991 5V V+ GND SET R4 976k C1 0.01µF 1.5ms PULSE 5V V+ GND R1 1M DIV R3 121k OUT LTC6993-1 SET DIV R8 143k R5 102k R6 10k C2 0.01µF R2 280k 69931234 TA03 1.5ms CAL TRIM Pulse Delay Generator 100µs DELAY GENERATOR TRIG PULSE IN TRIG OUT LTC6993-1 GND 10µs OUTPUT PULSE GENERATOR LTC6993-1 5V V+ R4 182k SET R6 78.7k OUT GND C1 0.01µF 5V V+ R1 976k DIV SET R5 976k OUT R3 61.9k C2 0.1µF DIV R2 102k 10µs PULSE IN 100µs DELAY 10µs PULSE OUT 69931234fc For more information www.linear.com/LTC6993-1 21 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Typical Applications RC Servo Pulse Generator Controlled Retrigger Lockout Time Interval TRIGGER 1.5ms PULSE GENERATOR R9 10k TRIG OUT PULSE OUT LTC6993-1 M1 2N7002 5V GND V+ SET DIV C2 0.1µF R1 1M R3 147k TRIGGER PULSE IN R2 280k 1.5ms PULSE OUT 20ms RETRIGGER LOCKOUT INTERVAL OUT R5 100k 5V 20ms RETRIGGER LOCKOUT TRIG RETRIGGER LOCKOUT TIME LTC6993-1 0.1µF R6 1M V+ GND DIV SET R4 243k R7 392k 69931234 TA05 Staircase Generator with Reset R8 4.99k R7 10k PULSE FREQUENCY-TO-VOLTAGE CONVERTER 5V 0.1µF 5V 0.1µF – PULSES IN U2 LT1490 R10 10k – D1 1N4148 R11 2k + + C1 1µF R6 20k R9 100k U4 2N7002 RESET RETRIGGERABLE STAIRCASE RESET PULSE GENERATOR TRIG R3 147k STAIRCASE RESET OUT LTC6993-2 22 STAIRCASE OUT VOUT U3 LT1490 GND V+ SET DIV STAIRCASE OUT 5V R1 280k C2 0.1µF PULSES IN RESET RAMP RESETS AFTER 1.5ms IF NO PULSES APPLIED 69931234 TA06 R2 1M 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Typical Applications Pulse Stretcher 5V R4 4.99k U2 LT1009 2.5V VOLTAGE VARIABLE OUTPUT PULSE WIDTH R1 10k Q4 2N2219A TRIG LTC6993-3 5V 0.1µF Q1 2N2907 – Q2 2N2907 R6 C1 10k 2200pF Q3 2N2219A R16 140k U4 LT1638 + RAMP OUT R13 113k GND V+ SET DIV PULSE OUT STRETCHED PULSE OUT R14 976k C4 0.1µF 5V R15 102k R7 10k RAMP VOLTAGE PROPORTIONAL TO INPUT PULSE WIDTH PULSE IN TRIG 1µs TO 10µs INPUT PULSE WIDTH OUT LTC6993-1 R3 392k GND V+ SET DIV 500µs RAMP RESET TIMER 5V R2 182k C2 0.1µF R5 976k 69931234 TA07 69931234fc For more information www.linear.com/LTC6993-1 23 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Typical Applications On-Time Programmable Pulsed Solenoid Driver 24V 5 SECONDS ON TRIGGER IN OFF TRIG TRIGGER OUT LTC6993-1 GND R3 118k SET 100mA SOLENOID DANFOSS 042 N024D TYPE AK024D D1 1N4004 R4 2k Q1 2N2219A Safety Time-Out Relay Driver RESET TRIG ENABLE PULSES OUT LTC6993-2 5V R1 1M DIV R2 887k GND C2 0.1µF C D1 1N4148 R4 10k NO Q1 2N2219A R3 118k SET 1 COTO 1022 RELAY 9001-12-01 5V V+ R1 1M 69931234 TA08 24 L RUN + V 12V TIMED (5s) TURN-OFF AFTER LOSS OF INPUT PULSES C2 0.1µF DIV R2 887k 69931234 TA09 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Package Description Please refer to http://www.linear.com/product/LTC6993#packaging for the most recent package drawings. DCB DCBPackage Package 6-Lead 6-LeadPlastic PlasticDFN DFN(2mm (2mm×× 3mm) 3mm) (Reference (ReferenceLTC LTCDWG DWG##05-08-1715 05-08-1715 Rev A) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 (2 SIDES) 2.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 1.35 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP R = 0.05 TYP 2.00 ±0.10 (2 SIDES) 3.00 ±0.10 (2 SIDES) 0.40 ±0.10 4 6 1.65 ±0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 × 45° CHAMFER PIN 1 BAR TOP MARK (SEE NOTE 6) 3 0.200 REF 0.75 ±0.05 1 (DCB6) DFN 0405 0.25 ±0.05 0.50 BSC 1.35 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 69931234fc For more information www.linear.com/LTC6993-1 25 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Package Description Please refer to http://www.linear.com/product/LTC6993#packaging for the most recent package drawings. S6 Package 6-Lead Plastic TSOT-23 S6 Package (Reference LTC DWG # 05-08-1636) 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 26 0.01 – 0.10 1.00 MAX DATUM ‘A’ 1.90 BSC S6 TSOT-23 0302 69931234fc For more information www.linear.com/LTC6993-1 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Revision History REV DATE DESCRIPTION PAGE NUMBER A 7/11 Revised Description section Added text to Basic Operation paragraph in Applications Information section 1 to 3 15 B 1/12 Added MP-grade 1, 2, 3, 5 C 11/15 Web Links Added All Conditions for VOH Specification from V+ = 5.5V, IOUT = –16mA, changed to V+ = 3.3V, IOUT = –10mA 4 Correction to graph “tOUT vs Supply Voltage (NDIV –1, Rising Edge)”. Curves were offset low, and corrected upward. 6 Correction to circuit “Safety Time-Out Relay Driver”, R4 changed from 15k to 10k. 23 69931234fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC6993-1 27 LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 Typical Application Consecutive Test Sequencer START TEST SEQUENCE 5V R10 25k DELAY ADJUST 30s R9 274k 2s 2s TO 30s DELAY TEST 1 DELAY TEST 2 TRIG OUT TRIG OUT TRIG OUT LTC6994-1 LTC6993-1 LTC6993-3 GND V+ SET DIV R1 63.4k 5V 0.1µF R2 1000k R3 887k GND V+ SET DIV 5V 0.1µF R6 191k GND V+ SET DIV TEST 3 TRIG OUT LTC6993-3 5V 0.1µF GND V+ SET DIV 5V 0.1µF R5 1000k R8 191k R7 191k R4 681k 69931234 TA10 SHARED DIV PIN BIASING FOR EQUAL ONE-SHOT TIMERS START TEST 1 DELAY TEST 2 TEST 3 ONE SECOND DURATION SEQUENTIAL TEST PULSES AFTER AN ADJUSTABLE DELAY TIME Related Parts PART NUMBER DESCRIPTION COMMENTS LTC1799 1MHz to 33MHz ThinSOT Silicon Oscillator Wide Frequency Range LTC6900 1MHz to 20MHz ThinSOT Silicon Oscillator Low Power, Wide Frequency Range LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator Micropower, ISUPPLY = 35µA at 400kHz LTC6930 Fixed Frequency Oscillator, 32.768kHz to 8.192MHz 0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz LTC6990 TimerBlox: Voltage-Controlled Silicon Oscillator Fixed-Frequency or Voltage-Controlled Operation LTC6991 TimerBlox: Resettable Low Frequency Oscillator Clock Periods up to 9.5 hours LTC6992 TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) Simple PWM with Wide Frequency Range LTC6994 TimerBlox: Delay Block/Debouncer Delay Rising Edge, Falling Edge or Both Edges 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC6993-1 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC6993-1 69931234fc LT 1115 REV C • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2010