Transmission Digital Signal Processor IC for Infrared Spatial Digital Audio Communication CXD4016R Description The CXD4016R is an IC that processes the transmitted digital signals used for infrared spatial digital audio communication (based on the IEC61603-8-1 standard) in consumer products. This IC contains the digital-toanalog converter (DAC) and a PLL circuit for RF signal. RF signal is processed by digital signal processing, so the operation is stable without any adjustments. Features Performs all the transmitted digital signal processing on a single chip Supports the infrared spatial digital audio communication system formats for consumer uses Support the three audio sampling frequencies (32kHz, 44.1kHz, 48kHz) Direct output of RF signals enabled by on-chip DAC External RAM and PLL circuit not required < Audio I/F Block > Interfaces for various audio ADCs < Parity Generator Block > Automatic generation of Reed-Solomon parity for the infrared spatial digital audio communication system format < Modulator Block > Digital processing throughout enables the transmitted RF signals in the infrared spatial digital audio communication system formats to be processed directly External analog circuit can be simplified by on-chip digital filter and on-chip DAC for RF signal applications Generation of subcarrier processed digitally < Controller Block > Simple pin setting mode Serial interface provided by serial bus < PLL Block > On-chip analog PLL circuit for generating the clock signals (640fs) required by the infrared spatial digital audio communication system formats Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E03Z16D64 CXD4016R Package 64 pin LQFP (Plastic) Structure Silicon gate CMOS IC Absolute Maximum Ratings – 0.5 to + 3.0 V VI – 0.5 to VDD + 0.5 ( ≤ 3.0V) V Output voltage VO – 0.5 to VDD + 0.5 ( ≤ 3.0V) V Storage temperature Tstg – 55 to + 125 °C Supply voltage VDD Input voltage Recommended Operating Conditions Supply voltage VDD 2.5 ± 0.2 V D/A supply voltage VDA 2.5 ± 0.2 V PLL supply voltage VPLL 2.5 ± 0.2 V – 40 to + 85 °C Operating temperature Topr Within ± 0.1% Sampling frequency precision Input/Output Capacitance Input capacitance CIN 16 (max.) pF Output capacitance COUT 16 (max.) pF Input/Output capacitance CI/O 16 (max.) pF Note) Measurement conditions : Tj = 25°C, VDD = VI = 0V, f = 1MHz -2- CXD4016R APCPO APVGS APS PLVAR PLREF Block Diagram 36 37 41 42 43 44 APAVD PLL 45 APAVS OSCI 57 OSCO 59 38 APX Clock Generator CK12 53 Clock Selector 46 VCOT XRST 64 21 DAAOUT LRCK 49 22 DAAVD BCK 50 DTIN 48 ReedSolomon Parity Generator Audio I/F BCKOUT 51 Buffer RAM Modulator D/A Converter 23 DAAVS 24 DAVREF 25 DAVRO LRCKOUT 52 3 IFEXMD 4 IIFSEL1 5 IIFSEL0 6 EXCKSEL 7 CHNM_BL Controller 8 DIVCODE 9 PCMID 10 EMPIN 14 XSCEN 13 SCLK 15 SWDT * Test pins not shown. -3- VDD VDD VDD VDD VDD VSS VSS VSS VSS 11 19 26 39 56 VSS 12 20 27 40 55 58 VSS 16 CSOD CXD4016R DTIN DT2_INF VCOT APAVS APAVD APCPO APVGS APS VSS VDD APX PLVAR PLREF TEST7 TEST6 TEST5 Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CK12 53 28 TEST0 CSST 54 27 VSS VSS 55 26 VDD VDD 56 25 DAVRO OSCI 57 24 DAVREF VSS 58 23 DAAVS OSCO 59 22 DAAVD XTCK4 60 21 DAAOUT XSM 61 20 VSS MST 62 19 VDD XTST 63 18 DACK XRST 64 17 DAPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CSOD TEST1 SWDT 29 XSCEN 52 SCLK LRCKOUT VSS TEST2 VDD 30 EMPIN 51 PCMID BCKOUT DIVCODE TEST3 CHNM_BL 31 EXCKSEL 50 IIFSEL0 BCK IIFSEL1 TEST4 IFEXMD 32 SMCK 49 TESTMD LRCK -4- CXD4016R Pin Description Pin No. Symbol I/O Description 1 TESTMD I Test mode selector, normally fixed “L”. 2 SMCK I SCAN test pin, normally fixed “H”. 3 IFEXMD I IIF extension mode. (L : Normal mode, H : Extension mode) 4 IIFSEL1 I Audio input mode selection. 5 IIFSEL0 I Audio input mode selection. 6 EXCKSEL I Clock selection for modulation. (L : APX internal connection, H : VCOT pin input) 7 CHNM_BL I Half-band : Channel number selection. (L : 0ch, H : 1ch) Full-band : Bit length control. (L : Full bit, H : 16-bit limited) 8 DIVCODE I Full/Half-band mode selection. (L : Full-band, H : Half-band) 9 PCMID I Source_info pcm_id input, normally fixed “L”. (L : PCM data) 10 EMPIN I Source_info emphasis input, (L : No emphasis, H : Emphasis) 11 VDD — Digital power supply. 12 VSS — Digital GND. 13 SCLK I Serial interface data clock input. 14 XSCEN I Serial interface enable input (negative logic). 15 SWDT I Serial interface data write input. 16 CSOD O Chapter start delay output. 17 DAPD O Test pin. 18 DACK O Test pin. 19 VDD — Digital power supply. 20 VSS — Digital GND. 21 DAAOUT O RF DAC output. 22 DAAVD — Analog power supply for RF DAC. 23 DAAVS — Analog GND for RF DAC. 24 DAVREF I 25 DAVRO I/O RF DAC internal current setting. 26 VDD — Digital power supply. 27 VSS — Digital GND. 28 TEST0 O Test output pin. 29 TEST1 O Test output pin. 30 TEST2 O Test output pin. 31 TEST3 O Test output pin. 32 TEST4 O Test output pin. 33 TEST5 O Test output pin. 34 TEST6 O Test output pin. 35 TEST7 O Test output pin. 36 PLREF O PLL reference output. RF DAC reference voltage input, apply 1.1V (typ.) -5- CXD4016R Pin No. Symbol I/O Description 37 PLVAR O PLL frequency-divided output (APX output or VCOT input divided by 640). 38 APX O PLL VCO output, 640fs. 39 VDD — Digital power supply. 40 VSS — Digital GND. 41 APS I 42 APVGS — PLL guard band GND. 43 APCPO O PLL charge pump output. 44 APAVD — PLL power supply. 45 APAVS — PLL GND. 46 VCOT I External clock input for modulation. 47 DT2_INF I Test pin, normally fixed “L”. 48 DTIN I Audio data input. 49 LRCK I LR clock input. 50 BCK I Bit clock input. 51 BCKOUT O Bit clock output (3.072MHz). 52 LRCKOUT O LR clock output (48kHz). 53 CK12 O Frequency-divided clock output for master clock (12.288MHz). 54 CSST I Test pin, normally fixed “L”. 55 VSS — Digital GND. 56 VDD — Digital power supply. 57 OSCI 58 VSS 59 OSCO O Crystal oscillator circuit output for master clock (24.576MHz). 60 XTCK4 I Test pin, normally fixed “L”. 61 XSM I Test pin for SCAN, normally fixed “H”. 62 MST I Test pin for SCAN, normally fixed “L”. 63 XTST I Test pin for SCAN, normally fixed “H”. 64 XRST I Asynchronous reset input. While power supply is “ON”, be sure to reset by fixing “L” after power supply is stabilized. I PLL reset pin. Crystal oscillator circuit input for master clock (24.576MHz). Digital GND. -6- CXD4016R Electrical Characteristics 1. DC characteristics (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item Symbol Conditions Min. Typ. Max. High level input voltage VIH 1.7 — VDD + 0.3 Low level input voltage VIL – 0.3 — 0.7 VDD – 0.2 — VDD 0 — 0.2 – 4.0 — — 4.0 — — Unit Applicable pins *1 V High level output voltage VOH IOH = – 100µA Low level output voltage VOL IOL = 100µA High level output current IOH VOH = VDD – 0.4V Low level output current IOL VOL = 0.4V Input leakage current IL — — ±5 µA *1 PLL supply voltage VPLL 2.3 2.5 2.7 V *3 PLL charge pump output current ICPO µA *4 DAC supply voltage VDA 2.3 2.5 2.7 V *5 DAC reference voltage VREF 1.05 1.10 1.15 V *6 DAC full-scale adjusting resistor RREF Between DAVRO and DAAVS 2.4 2.7 kΩ *7 DAC output current IDAC VREF = 1.10V, RREF = 2.7kΩ Full-scale Zero-scale LSB-scale 4.67 0 5.194 2 20.3 5.71 20 mA µA µA *8 DAC load resistance RL Between DAAOUT and DAAVS 150 160 Ω *8 Supply current of digital block IDD VDD = 2.5V fs = 44.1kHz Full-band mode 12 mA *9 Supply current of D/A block IDA V (DAAVD) = 2.5V fs = 44.1kHz Full-band mode 6.5 mA *5 Supply current of PLL block IPLL V (APAVD) = 2.5V fs = 44.1kHz Full-band mode 3.5 mA *3 500 *2 *2 mA *2 Applicable pins *1 *2 *3 *4 *5 *6 *7 *8 *9 TESTMD, SMCK, IFEXMD, IIFSEL1, IIFSEL0, EXCKSEL, CHNM_BL, DIVCODE, PCMID, EMPIN, SCLK, XSCEN, SWDT, APS, VCOT, DT2_INF, DTIN, LRCK, BCK, CSST, XTCK4, XSM, MST, XTST, XRST CSOD, DAPD, DACK, TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7, PLREF, PLVAR, APX, BCKOUT, LRCKOUT, CK12 APAVD APCPO DAAVD DAVREF DAVRO DAAOUT VDD (Pins 11, 19, 26, 39, 56) -7- CXD4016R 2. AC characteristics (1) OSCI, OSCO pins (a) When using self-excited oscillation (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item Symbol Oscillation frequency Min. Typ. Max. Unit — 24.576 — MHz Min. Typ. Max. Unit fSYS (b) When inputting pulses to OSCI (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item Symbol Pulse frequency fSYS 24.330 24.576 24.600 MHz High level pulse width tWHX — 20.345 — ns Low level pulse width tWLX — 20.345 — ns Rise time/fall time t R , tF 2 ns tCX (1/fSYS) tWHX tWLX VIH VIH × 0.9 VDD/2 OSCI VIH × 0.1 VIL tF tR (2) VCOT pin (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item Symbol Min. Typ. Max. Unit 20.275 — 31.027 MHz Pulse frequency fCXR High level pulse width tWHXS 0.45 × tCXR — 0.55 × tCXR ns Low level pulse width tWLXR 0.45 × tCXR — 0.55 × tCXR ns tCXR (1/fCXR) tWHXR tWLXR VIH VIH × 0.9 VDD/2 VCOT VIH × 0.1 VIL tR tF -8- CXD4016R (3) SCLK, XSCEN, SWDT, SRDT pins (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item Symbol Min. Typ. Max. Unit Clock period tCW 200 — — ns Clock pulse width, high tCWH 100 — — ns Clock pulse width, low tCWL 100 — — ns Enable signal pulse width tCSWH 170 — — ns Enable signal setup time tCSS 0 — — ns Enable signal hold time tCSH 100 — — ns SWDT Setup time tWSU 20 — — ns SWDT Hold time tWHD 100 — — ns tCW tCSS tCWL tCSH tCSWH tCWH XSCEN SCLK tWSU tWHD SWDT (4) An example of data read phase CSOD pin (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item CSOD pulse width Symbol tCSOD Min. Typ. Max. Unit 260 — — µs Min. Typ. Max. Unit 100.0 — — ns CSOD tCSOD (5) XRST pin (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item XRST pulse width Symbol tXRST XRST tXRST -9- CXD4016R (6) BCK, DTIN, LRCK pins (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item Symbol Min. Typ. Max. Unit DTIN setup time tDTS 10 — — ns DTIN hold time tDTH 100 — — ns LRCK skew time tLRSK — — ± 20 ns BCK VDD/2 tDTS DTIN tDTH VDD/2 tLRSK VDD/2 LRCK - 10 - CXD4016R Description of Functions Description of clock generator 1. This LSI chip can generate the system clock pulse by connecting a 24.576MHz crystal oscillator to the OSCI pin and OSCO pin. Also, it incorporates 1MΩ (typ.) feedback resistor between the OSCI and OSCO pins. 2. It functions as the system clock by inputting a 24.576MHz external oscillation clock pulse to the OSCI pin while keeping the OSCO pin open. 3. Please keep the frequency precision for system clock within 24.576MHz ± 100ppm. Description of PLL circuit 1. In addition to supplying the system clock pulse using the OSCI pin, this LSI requires the modulation clock pulse which is provided by the PLL circuit. The PLL circuit provided on the LSI chip can be used for this purpose. 2. If the sampling frequency of the digital audio input signals is fs, then the modulation clock pulse provided by the PLL circuit has a frequency of 640fs. 3. When the PLL circuit on the LSI is used, input a low level to the EXCKSEL pin and VCOT pin. Furthermore, an external lag-lead filter must be connected to the LSI for the charge pump current output APCPO pin of the PLL circuit. Ensure that the wiring involved is kept as short as possible. 4. When the PLL circuit on the LSI is not used, the LSI chip must be provided with an external PLL circuit. Input a high level to the EXCKSEL pin and the modulation clock pulse to the VCOT pin. The reference signal of the PLL circuit for generating the clock pulses is output to the PLREF pin, and its frequency is set to fs. At this time, the frequency of the clock pulse which has been input to the VCOT pin is divided by 640 inside the LSI, and the pulse with the resulting frequency is output to the PLVAR pin. Pin setting/serial data interface The setting modes of this LSI can be broadly classified into two : the pin setting mode and the serial data interface mode. By setting serial data interface mode, switching between pin setting mode and serial data interface mode is enabled. For example, setting SCEN01 bit to “0” validate pin setting mode and setting it to “1” validate serial data interface setting mode during Address 01 in serial data interface mode. (See “(3) Serial setting command table” on the next page.) Followings are pins which can be set even in the serial data interface mode. EXCKSEL pin, DIVCODE pin, CHNM_BL pin, IFEXMD pin, IIFSEL1 pin, IIFSEL0 pin, PCMID pin, EMPIN pin. - 11 - CXD4016R Description of serial data interface 1. Serial data interface timings This LSI enables the various LSI operations to be changed by the SCLK pin, SWDT pin and XSCEN pin. The interface timing chart for each code group is presented below. Also, the SCLK pin should not be used with other devices. Normal communication cannot be performed. 2. XRST pin All the internal registers are initialized to “Default value” presented in the “Serial data interface setting command table” when reset by setting the XRST pin to low. XSCEN SCLK SWDT A7 A6 A5 A4 A3 A2 Internal registers A1 A0 Dn – 1 Dn – 2 Dn – 3 D2 D3 D2 D1 D0 Valid 3. Method for disabling the CXD4016R's FSLOCK signal The LRCK input to the CXD4016R must be a stable clock with no jitter. A PLL that uses LRCK as the reference is formed inside the CXD4016R, and this PLL generates a 640fs clock. However, the signal (FSLOCK) that indicates the PLL lock status is generated inside this LSI, and RF generation is temporarily stopped when the lock is lost. This lock detection logic has strict conditions, so if the LRCK jitter is large, the jitter of the clock generated by the PLL is also large, and the lock may be judged as lost. Using a LRCK with large jitter is not recommended, but when a LRCK with large jitter must be used, this LSI has a test mode that can reduce the RF generation stoppage frequency by disabling the FSLOCK signal as follows. FSLOCK can be enabled or disabled by sending the command indicated in the Serial Setting Command Table. At the default setting, FSLOCK operates according to the lock detection logic. To forcibly set the FSLOCK status, send address 71h and data 0Fh by the serial setting command. In addition, to return to the default setting, send address 71h and data 03h by the serial setting command. Performing this process is highly recommended. - 12 - CXD4016R 4. Serial setting command table Address (HEX) 01h 02h 03h 71h Default value 00h 40h 69h 03h Length [bit] 8 8 8 Signal name Signal length [bit] Value SCEN01 1 0 1 Invalidate serial setting of Address 01. Validate serial setting of Address 01. EXCKSEL 1 0 1 APX internal connection. VCOT pin input. DIVCODE 1 0 1 Full-band mode. Half-band mode. CHNM_BL 1 0 1 0ch/full-bit. 1ch/16-bit limited. IFEXMD 1 0 1 Normal mode. Extension mode. IIFSEL1 1 — Audio input interface mode select 1. IIFSEL0 1 — Audio input interface mode select 0. res. 1 0 Be sure to set the value to “0”. SCEN02 1 0 1 Invalidate serial setting mode of Address 02. Validate serial setting mode of Address 02. CRC_FLG 1 0 1 CRC off. CRC on (default). VALID_FLG 1 0 1 Source_block is error free. Source_block contains some errors. PCM_ID 1 0 1 Data is Linear PCM. Data is used for other purposes. CPRGT_FLG 1 0 1 Copyright is asserted. No copyright is asserted. EMPHASIS 1 0 1 No emphasis. Emphasis. res. 2 00 Reserved. CATEGORY 8 — Source_info Byte 3 category codes. res. 4 0000 FSLOCK_EN 1 0 1 Invalidate serial setting mode of FSLOCK. Validate serial setting mode of FSLOCK. FSLOCK 1 0 1 Set to unlocked logic forcibly. Set to locked logic forcibly. res. 2 11 Be sure to set the value to “11”. 8 - 13 - Effect Be sure to set the value to “0000”. CXD4016R Description of audio I/F 1. As shown below, the audio ADC can be directly coupled in this LSI. DTIN : Connect the data output from ADC BCK : Connect the bit clock output from ADC (64fs) LRCK : Connect the sample clock output from ADC (fs) The sampling frequencies (fs) which can correspond to this LSI are 32kHz, 44.1kHz, 48kHz. Also, the precision of fs is within ± 1000ppm. If it gets beyond this range even for a second, the normal operation might not be performed. So care should be taken. 2. This LSI has the LRCKOUT pin, BCKOUT pin and CK12 pin in order to use the audio ADC into which sample clock and bit clock are required to be input. LRCKOUT pin : sample clock (48kHz) BCKOUT pin : bit clock (48kHz × 64) CK12 pin : master clock (12.288MHz (48kHz × 256) ) Connect the LRCKOUT pin to the sample clock of ADC and the LRCK pin of this LSI. And connect the BCKOUT pin to the bit clock pin of ADC and the BCK pin of this LSI. 3. Sixty-four BCK cycles are contained in one LRCK cycle. 4. The DTIN input format can be changed by the setting of resistor with address 01h, or the IFEXMD pin, IIFSEL1 pin and IIFSEL0 pin. Name of iif_mode IFEXMD IIFSEL [1 : 0] Data input format mode-0 0 00 MSB first, Left Justified 24 bits mode-1 0 01 I2S 24 bits mode-2 0 10 LSB first, Right Justified 24 bits mode-3 0 11 MSB first, Right Justified 24 bits mode-4 1 00 MSB first, Right Justified 20 bits mode-5 1 01 MSB first, Right Justified 16 bits Note) 1. 2. When CHNM_BL is set to “1” by the CHNM_BL pin or address 01h of serial data interface, only high-order 16 bits are validated during Full-band mode. Only high-order 16 bits are validated during Half-band mode. - 14 - CXD4016R Timing charts covering what has been described above are presented below. Audio ADC interface timing charts LRCK Left channel BCK DAOUT MSB LSB mode-0 Left channel LRCK BCK DAOUT MSB LSB mode-1 LRCK Left channel BCK DAOUT LSB MSB mode-2 LRCK Left channel BCK DAOUT MSB LSB mode-3 LRCK Left channel BCK DAOUT MSB LSB mode-4 LRCK Left channel BCK DAOUT MSB mode-5 - 15 - LSB X'tal 24.576MHz APX VSS VDD APS APVGS APCPO EXCKSEL APAVD IIFSEL0 APAVS IIFSEL1 VCOT IFEXMD TEST2 30 TEST4 TEST3 31 32 64 XRST 63 XTST 62 MST 61 XSM 2 1 60 XTCK4 59 OSCO 58 VSS 57 OSCI 56 VDD 55 VSS 3 4 5 6 7 8 9 DAPD RREF RL 2.5VD LPF 2.5VA RF output 1.1V reference voltage C1 = 0.1µF R1 = 2.2kΩ C2 = 4700pF Rx = 4.7MΩ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 10 11 12 13 14 15 16 17 DACK 18 VDD 19 VSS 20 DAAOUT 21 DAAVD 22 DAAVS 23 DAVREF 24 DAVRO 25 VDD 26 VSS 27 CHNM_BL 54 CSST DIVCODE TEST0 28 EMPIN 53 CK12 PCMID TEST1 29 VDD 52 LRCKOUT TESTMD A/D converter PLVAR VSS DTIN 51 BCKOUT 50 BCK Rx PLREF SCLK 49 LRCK DT2_INF SMCK Audio C2 TEST7 XSCEN TEST5 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 C1 TEST6 SWDT - 16 CSOD Reset circuit R1 2.5VA CXD4016R Application Circuit CXD4016R Notes on Operation The loop filter portion of the PLL block is important for the characteristics. Therefore, the loop filter should be located as close to the IC pin as possible and surrounded by AGND. In addition, temperature compensation parts should be used for the loop filter capacitor and resistor. The CXD4016R generates a delay during transmission. Labeling the sampling frequency as fs, the delay time is 192/fs [s] in full-band mode. For example, when fs = 48kHz, the delay time is 4ms. In addition, in halfband mode the delay time is 384/fs [s]. In this case for example, when fs = 48kHz, the delay time is 8ms. Note that a delay is also generated during reception by the receive side IC CXD4017R. See the CXD4017R data sheet for details. CXD4016R Evaluation Board Description The CXD4016R evaluation board is a dedicated board designed to allow easy evaluation of the CXD4016R which was developed for transmission of infrared spatial digital audio communication. Optical digital and analog (pin jack) circuits are mounted, and can be switched by a switch. The input audio signal is converted to an infrared spatial digital audio communication system format RF signal by the CXD4016R, and output from a SMB connector. Features Supply voltage : + 5V single power supply Analog and optical digital audio input can be selected Operating Conditions Supply voltage : + 5V (typ.) Current consumption : 150mA (typ.) Input signal : Analog or optical digital audio signal Operation Method The CXD4016R evaluation board allows easy evaluation simply by providing the power supply and inputting an analog or optical digital audio signal. The evaluation procedure is as follows. 1. Connect the power supply to the power supply connection pin J5. 2. SW1 is the manual reset switch. A reset is applied automatically during power-on, but this switch is used to perform reset manually. 3. The DIVCODE pin can be set by DIP switch S2-1. The DIVCODE pin is set low when this switch is OFF, and high when ON. 4. The CHNM_BL pin can be set by DIP switch S2-2. The CHNM_BL pin is set low when this switch is OFF, and high when ON. 5. The IFEXMD pin can be set by DIP switch S2-4. The IFEXMD pin is set low when this switch is OFF, and high when ON 6. The IIFSEL1 pin can be set by DIP switch S2-5. The IIFSEL1 pin is set low when this switch is OFF, and high when ON. 7. The IIFSEL0 pin can be set by DIP switch S2-6. The IIFSEL0 pin is set low when this switch is OFF, and high when ON. 8. The audio signal can be selected by DIP switch S2-7. The optical digital audio signal is selected when this switch is OFF, and the analog audio signal when ON. 9. Connect the optical digital audio signal to the U8 square optical connector. 10. Connect the analog audio signal to the J1 pin jack. - 17 - CXD4016R 11. When the analog audio signal is selected, the sampling frequency can be changed by DIP switch S2-8. 48kHz is set when this switch is OFF, and 44.1kHz when ON. 12. Always set DIP switches other than noted above to OFF. The above contents are listed in the tables below for reference. S1 Mode 1 Always OFF 2 Always OFF 3 Always OFF 4 Always OFF 5 Always OFF 6 Always OFF 7 Always OFF 8 Always OFF S2 Mode 1 OFF : DIVCODE = L, ON : DIVCODE = H 2 OFF : CHNM_BL = L, ON : CHNM_BL = H 3 Always OFF 4 OFF : IFEXMD = L, ON : IFEXMD = H 5 OFF : IIFSEL1 = L, ON : IIFSEL1 = H 6 OFF : IIFSEL0 = L, ON : IIFSEL0 = H 7 OFF : Optical digital, ON : Analog 8 OFF : 48kHz, ON : 44.1kHz (only when the analog audio signal is selected) 13. Light emitting diode D1 is off when DIVCODE is low, and lighted when DIVCODE is high. 14. Light emitting diode D2 is off when CHNM_BL is low, and lighted when CHNM_BL is high. 15. Light emitting diodes D3 and D4 indicate the sampling frequency of the audio signal. This relationship is shown in the table below. D3, D4 Sampling frequency Off, off 44.1kHz Off, lighted 48kHz Lighted, lighted 32kHz Flashing, flashing Unlock 16. Light emitting diodes D5 to D8 are not used. 17. The infrared spatial digital audio communication system format RF signal is output from SMB connector J8. 18. J2 and J3 are not used. - 18 - CXD4016R CXD4016R EVB Semiconductor Parts List Parts No. Product name Manufacturer U1, 3 NJM2100M New Japan Radio U2 AK5353VT Asahi Kasei Microsystems U4, 21 TC74LCX541F Toshiba U5 CXD4016R SONY U6 TC74VHC04F Toshiba U7 CS8415A-CZ Cirrus Logic U8 TORX141P Toshiba U9 FXO-31FL 24.576MHz Kyocera Kinseki U10 EP1K100QI208-2 ALTERA U11 EPC2LI20 ALTERA U12 FXO-31FL 22.5792MHz Kyocera Kinseki U13, 14, 15, 16, 17, 18 LM317A National Semiconductor U19, 20 TL7705CP Texas Instruments U22 AD8057ART Analog Devices Q1 2SC2223L NEC D1, 2 TLG124 Toshiba D3, 4 TLY124 Toshiba D5, 6 TLO124 Toshiba D7, 8 TLR124 Toshiba D9 to 20 1S1588 Toshiba FPGA Operation 1. Selects the optical digital audio signal or the analog audio signal selected by S2-7. 2. Converts the selected audio signal to the DTIN pin input format set by S2-4, S2-5 and S2-6. 3. Detects the sampling frequency. - 19 - - 20 DAPD SWDT DAPD SWDT SCLK XSCEN (Middle-speed Signal) (High-speed Signal) (High-speed Signal) DT2_INF DTIN LRCK APS_XRST BCK BCKOUT LRCKOUT CSOD CK12 CSST XRST IFEXMD IIFSEL1 IIFSEL0 EXCKSEL CHNM_BL DIVCODE PCMID EMPIN XSCEN SCLK DT2_INF DTIN LRCK APS_XRST BCK BCKOUT LRCKOUT CSOD CK12 CSST XRST IFEXMD IIFSEL1 IIFSEL0 EXCKSEL CHNM_BL DIVCODE PCMID EMPIN CXD4016R CXD4016R EVB circuit diagram (TOP) XRSTPW2 POWER XRSTPW1 XRSTPW2 ORIG RMCK ORIG RMCK XRSTPW1 COPY EMPH RST RERR RCBL PRO CHS NVERR OSCLK OLRCK SDOUT AUDIO U C (High-speed Signal) (High-speed Signal) SDTO_1 LRCK_AD MCLK SCLK_AD PDN PLD1 COPY EMPH RST RERR RCBL PRO CHS NVERR OSCLK OLRCK SDOUT AUDIO U C SDTO_1 LRCK_AD MCLK SCLK_AD PDN PWXRST DIF AIF DAAOUT DAAOUT RFOUT CXD4016R Circuit Diagram Lch_1 (WHITE) Rch_1 (RED) 1 A 2 3 J1 RCA JACK 2P 3 1 6 4 A 5 RV1B 50k A 2 RV1A 50k A C21 22µ/16V A R18 4.7k VA5 R13 20k C22 0.1µ A R17 330k C16 22µ/16V C15 0.1µ A C14 22µ/16V A C9 0.1µ R8 4.7k VA5 R3 20k A A C8 22µ/16V A R7 330k C3 22µ/16V A A 1 R1 20k VA5 1 R11 20k A R20 4.7k U3A NJM2100M 3 2 A R10 4.7k U1A NJM2100M 3 2 8 8 R14 10k R4 10k 7 R2 10k 7 R6 470 R16 470 C17 4.7µ/16V T R15 330 C4 4.7µ/16V T R5 330 A AINL1 TP1 LC-2S-W A C7 0.1µ A VD5 C13 0.1µ AINR1 TP2 LC-2S-R C18 10µ/16V T VA5 A C12 10µ/16V T AGND TP5 LC-2S-BK A C11 0.1µ C6 4.7µ/16V T C10 4.7µ/16V T C20 2200p A C5 2200p CXD4016R EVB Circuit Diagram (AUDIO) U3B NJM2100M 5 6 A R12 10k U1B NJM2100M 5 6 A 4 4 1 C2 0.1µ 1 C1 22µ/16V 1 D 16 15 14 13 12 11 10 9 SCLK TP6 LC-2S-G D R9 10k VD5 MCLK TP4 LC-2S-Y TST TTL DIF PDN SCLK MCLK LRCK SDTO AK5353VT AINR AINL VREF VCOM AGND VA VD DGND C19 0.1µ 1 2 3 4 5 6 7 8 U2 1 - 21 - 1 R21 R22 R23 R24 Y8 GND Y7 A8 Y6 A7 Y5 A6 Y4 A5 Y3 A4 Y2 A3 A2 Y1 G2 A1 VCC G1 U4 10 9 8 7 6 5 4 3 2 1 VD33 C23 0.1µ TC74LCX541F 11 12 100 13 100 14 22 15 100 16 17 18 19 20 R19 100 D DGND TP3 LC-2S-BK 1 VA5 D PDN SCLK_AD MCLK LRCK_AD SDTO_1 CXD4016R EMPIN PCMID DIVCODE CHNM_BL EXCKSEL IIFSEL0 IIFSEL1 IFEXMD XRST CSST CK12 LRCKOUT 1 TP19 LC-2S-BL 22 R33 C30 18p R34 100 R32 Y1 CSST TP20 LC-2S-Y 100 IIFSEL1 IIFSEL0 EXCKSEL TP26 TP27 TP28 LC-2S-G LC-2S-G LC-2S-BL R37 is missing number. C33 27pF CX-49G_24.576MHz IFEXMD TP25 LC-2S-Y 1 1 CK12 C29 0.1µ TP34 TP35 TP36 TP37 EMPIN PCMID DIVCODE CHNM_BL LC-2S-BL LC-2S-BL LC-2S-Y LC-2S-Y 1 BCKOUT 1 BCK 1 LRCK 1 1 LRCK BCK TP16 TP15 LC-2S-Y LC-2S-Y 1 LRCKOUT BCKOUT TP13 TP14 LC-2S-G LC-2S-BL 1 1 1 DT2_INF DTIN 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 A XRST XTST MST XSM XTCK4 OSCO VSS OSCI VDD VSS CSST CK12 LRCKOUT BCKOUT BCK LRCK D R27 22 47 C25 0.1µ VA25P R28 0 A C26 0.1µ C27 0.1µ APS TP9 LC-2S-Y CXD4016R U5 R29 0 1 R30 100 C37 0.1µ R31 100 PLREF TP8 LC-2S-Y 1 PLVAR TP7 LC-2S-BL APX TP10 LC-2S-Y 1 38 R25 2.2k 46 DT2_INF TP11 LC-2S-BL 1 44 1 41 DTIN TP12 LC-2S-Y 1 33 APS_XRST 1 48 DTIN TESTMD 1 DT2_INF SMCK 2 VCOT IFEXMD 3 45 APAVS 1 1 1 1 R43 100 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D SCLK TP31 LC-2S-Y XSCEN TP32 LC-2S-Y SWDT TP33 LC-2S-Y R41 0 R39 150 R36 2.7k VD25D R40 0 TP24 DACK LC-2S-Y C34 0.1µ C31 0.1µ C28 0.1µ TP23 DAPD LC-2S-Y CSOD TP30 LC-2S-G DAPD DACK VDD VSS DAAOUT DAAVD DAAVS DAVREF DAVRO VDD VSS TEST0 TEST1 TEST2 TEST3 TEST4 CXD4016R EVB Circuit Diagram (MAIN) IIFSEL1 4 APAVD 43 6 IIFSEL0 5 APCPO EXCKSEL 42 APVGS CHNM_BL 7 APS DIVCODE 8 37 PLVAR 35 TEST7 40 VSS PCMID 9 A A A 39 VDD EMPIN 10 APX VDD 11 DAPD A 2 C36 0.01µ C32 DAAOUT 0.1µ TP22 LC-2S-Y VA25D DAVREF TP21 LC-2S-G 1 C24 4700p 1 A R44 10k R42 4.7k VA5 A R38 910 VR1 200 R35 1.2k VA25A 3 1 36 13 VSS 12 PLREF SCLK SCLK C35 0.1µ A A R45 1k D DAAOUT TP18 LC-2S-BK DGND DAAOUT_Buf TP29 LC-2S-Y C38 0.01µ Q1 2SC2223L VA5 A TP17 LC-2S-BK AGND 1 34 TEST6 SWDT 15 XSCEN 14 XSCEN 1 TEST5 CSOD 16 CSOD 1 D 1 - 22 - D SWDT 1 A R26 4.7M CXD4016R - 23 - D VCC 6A 6Y 5A 5Y 4A 4Y OUT GND VCC NC NC 1 2 3 4 5 74VHC04F 1A 1Y 2A 2Y 3A 3Y GND TORX141P U8 1 2 3 4 5 6 7 14 13 12 11 10 9 8 D C46 0.1µ L1 47µH VD33 D C39 0.1µ RST RMCK RERR RCBL PRO CHS EMPH COPY A AGND TP39 LC-2S-BK SPDIF TP38 LC-2S-Y 1 U6 1 R58 R54 D 0 100 C43 0.1µ R56 R52 C41 0.01µ C44 1000p 100 22 VA5 A C45 4700p C42 0.01µ A A C47 0.1µ R61 1.2k VD33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ORIG VL3+ C U H/S VL+ DGND DGND2 DGND3 AUDIOx SDOUT OLRCK OSCLK NVERR D DGND TP40 LC-2S-BK CS8415A-CZ COPY VL2+ EMPH RXP0 RXN0 VA+ AGND FILT RSTx RMCK RERR RCBL PRO CHS U7 C40 0.01µ D 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CXD4016R EVB Circuit Diagram (DIGITAL INTERFACE) R48 47k R47 100 D 1 VD33 VD33 D R59 R55 R51 47k D 100 100 R49 100 R46 47k R60 R57 R53 100 100 100 R50 100 D AUDIO SDOUT OLRCK OSCLK NVERR C U ORIG CXD4016R ORIG U C AUDIO SDOUT OSCLK OLRCK CHS NVERR EMPH RST RERR RCBL PRO COPY SCLK_AD PDN SDOUT LC-2S-BL TP47 9 8 7 6 5 4 3 2 1 D VD25B A6E-8104 S1 M9-1-103J R8 R7 R6 R5 R4 R3 R2 R1 COM RA4 R77 R75 100 OLRCK LC-2S-G TP48 R73 R70 TH11 TH TH8 TH TH10 TH OSCLK LC-2S-Y TP49 100 100 100 C66 0.1µ C64 0.1µ C62 0.1µ C60 0.1µ C58 0.1µ C56 0.1µ VD25B ON TH14 TH TH12 TH R83 100 D1 FULL/HALF TLG124A TH7 TH TCK CONF_DONE nCEO TDO VCCIO GND SDTO_1 I_O LRCK_AD CLKUSR_I_O MCLK I_O SCLK_AD I_O PDN RDYnBUSY I_O COPY INIT_DONE GND VCCINT VCCIO GND EMPHx RSTx RERR RCBL PRO I_O CHS NVERR GND VCCINT VCCIO GND OSCLK OLRCK I_O SDOUT I_O AUDIOx VCCIO GND U C I_O ORIG VCCINT GND TMS TRST nSTATUS R84 22 IFdata9 IFdata10 9 8 7 6 5 4 3 2 1 D A6E-8104 S2 VD25B M9-1-103J RA5 R8 R7 R6 R5 R4 R3 R2 R1 COM LED1 LED2 LED3 LED4 R67 IFdata7 C68 0.1µ 1 2 3 4 5 6 7 8 R69 C50 0.1µ TH3 TH C51 0.1µ TH4 TH C52 0.1µ D U10 EP1K100QI208-2_1 ON RMCK RMCK IFdata5 D GND OUT U12 VDD 1 4 C70 0.1µ VD33 IFdata3 TH5 TH TH6 TH D C76 0.1µ C71 0.1µ C72 0.1µ VD25B TH15 TH TH13 TH 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 D R82 10k VD33 XRSTPW1 DATA0 DCLK nCE TDI VCCINT GND DT2_INF DTIN LRCK USER_IO VCCIO GND APS_XRST BCK BCKOUT I_O LRCKOUT CSOD VCCIO GND CK12 I_O CSST I_O XRST IFEXMD VCCINT GND IIFSEL1 IIFSEL0 EXCKSEL CHNM_BL VCCINT GND DIVCODE I_O PCMID I_O VCCIO GND EMPIN SCLK I_O XSCEN DAPD SWDT VCCIO GND MSEL0 MSEL1 VCCINT nCONFIG CXD4016R EVB Circuit Diagram (PLD) FXO-31FL_22.5792MHz 2 3 INHX C69 0.1µ XRSTPW2 LC-2S-Y TP50 1 R81 C73 22 0.1µ LED5 LRCK_AD MCLK IFdata6 C49 0.1µ TH2 TH FXO-31FL_24.576MHz 22 LED6 C53 0.1µ IFdata8 TH1 TH D IFdata4 LED7 LED8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 D2 CHNM_BL TLG124A DSW2_1 1 2 DSW2_2 1 GND DSW2_3 1 INHX DSW2_4 1 1 DSW2_5 SDTO_1 1 3 DSW2_6 1 OUT DSW2_7 1 DSW2_1 DSW2_2 DSW2_3 DSW2_4 DSW2_5 DSW2_6 DSW2_7 DSW2_8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD DSW2_8 TP41 TP43 TP44L TP42 LC-2S-G LC-2S-Y LC-2S-BL C-2S-Y SCLK_AD MCLK LRCK_AD SDTO1 R85 100 LED1 R86 D3 Fs_1 TLY124 100 LED2 D4 Fs_0 TLY124 100 LED3 IFdata2 I_O I_O LED1 LED2 LED3 LED4 GND DSW1_1 DSW1_2 LOCK DSW1_3 I_O DSW1_4 VCCIO DSW1_5 DSW1_6 DSW1_7 DSW1_8 RMCK VCCINT CRYST22M I_O GL_CLK1 GND VCC_CKLK Ded_Input GlobalCLK1 Ded_Input GND_CLK GND LED5 VCCIO LED6 I_O LED7 LED8 I_O DSW2_1 VCCINT DSW2_2 I_O DSW2_3 I_O DSW2_4 DSW2_5 VCCIO I_O DSW2_6 I_O DSW2_7 I_O DSW2_8 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 16 15 14 13 12 11 10 9 100 LED4 IFdata1 nCS CS nWS IFdata10 nRS IFdata9 I_O VCCINT IFdata8 I_O IFdata7 I_O IFdata6 I_O VCCIO I_O I_O I_O I_O I_O GND I_O DEV_OE VCCINT Ded_Input CRYST24M Ded_Input GND DEV_CLRn I_O VCCIO I_O I_O I_O IFdata5 I_O IFdata4 GND IFdata3 I_O IFdata2 IFdata1 DATA7 VCCIO DATA6 I_O DATA5 DATA4 I_O DATA3 DATA2 DATA1 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 R62 U9 R87 4 D5 STA_5 TLO124 VD33 R88 100 LED5 D6 STA_6 TLO124 100 LED6 R89 100 LED7 R90 D7 STA_7 TLR124 100 LED8 D8 STA_8 TLR124 4 5 6 7 8 U11 R64 1k VD33 DCLK VCCSEL NC NC OE R63 10k VD33 EPC2LI20 C67 0.1µ C65 0.1µ C63 0.1µ C61 0.1µ C59 0.1µ C57 0.1µ C55 0.1µ C54 0.1µ VD25B 3 2 1 20 19 TCK DATA TDO VCC TMS nCS GND TDI nCASC nInt_Conf D 100 R80 D C75 0.1µ VD33 100 18 VPP 17 NC 16 NC 15 NC 14 VppSel 100 R79 TH9 TH 100 100 0 100 100 100 100 R78 R76 R74 R71 R72 R65 R66 R68 RA1 M9-1-103J RA3 M5-1-102J XSCEN DAPD SWDT EMPIN SCLK PCMID DIVCODE IIFSEL1 IIFSEL0 EXCKSEL CHNM_BL XRST IFEXMD CSST CK12 LRCKOUT CSOD D R91 1k D GND A9 GND A7 GND A5 GND A3 GND A1 J2 GND A9 GND A7 GND A5 GND A3 GND A1 J3 IL-10P-S3EN2 10 9 8 7 6 5 4 3 2 1 IL-10P-S3EN2 10 9 8 7 6 5 4 3 2 1 D C74 0.1µ VD33 D D TP46 LC-2S-BK DGND 1 2 3 TCK GND 4 5 TDO Vcc 6 7 TMS NC 8 NC NC 10 9 TDI GND J4 XG4C-1031 D TP45 LC-2S-BK DGND RA2 M9-1-103J APS_XRST BCK BCKOUT DT2_INF DTIN LRCK IFdata1 IFdata2 IFdata3 IFdata4 IFdata5 IFdata6 IFdata7 IFdata8 IFdata9 IFdata10 1 COM R1 R2 R3 R4 1 2 3 4 5 - 24 - 9 10 11 12 13 9 8 7 6 5 4 3 2 1 R8 R7 R6 R5 R4 R3 R2 R1 COM 9 8 7 6 5 4 3 2 1 R8 R7 R6 R5 R4 R3 R2 R1 COM 1 C48 0.1µ CXD4016R C77 22µ/16V A R111 270 A 2 2 A JP1 R95 270 R104 240 2 LM317A VR5 50 1 C78 0.1µ R92 240 VIN VOUT R112 100 3 A R101 270 VR2 500 VOUT LM317A D15 1S1588 U16 2 A D9 1S1588 VIN U13 A R98 750 3 1 TP52 TP53 LC-2S-BK LC-2S-BK AGND AGND IL-2P-S3EN2 1 2 ADJ 1 3 1 A A C110 10µ/16V C104 47µ/16V D18 1S1588 C95 10µ/16V A D D C90 0.1µ VA5 A C83 0.1µ L4 SN3-200 C82 47µ/16V D C80 47µ/16V VD5 D D C105 0.1µ C98 0.1µ D3.3V TP57 L7 LC-2S-R SN3-200 D D2.5V_B TP54 LC-2S-G C81 0.1µ L3 SN3-200 D12 1S1588 C89 47µ/16V D C79 0.1µ 1 J5 1 D D D D C99 47µ/16V RM4 0 C84 47µ/16V RM1 0 VD33 VD25B A 2 2 A R113 270 VR6 500 R107 270 R105 240 2 LM317A R96 270 R93 240 VIN VOUT R109 750 3 U17 D16 1S1588 A R102 270 VR3 500 VOUT LM317A A A C111 10µ/16V C106 47µ/16V D19 1S1588 C96 10µ/16V C91 47µ/16V D13 1S1588 D A A C107 0.1µ C100 0.1µ A2.5V_D TP58 LC-2S-O L8 SN3-200 D C92 0.1µ C85 0.1µ D2.5V_D TP55 LC-2S-G L5 SN3-200 1 CXD4016R EVB Circuit Diagram (POWER) A 2 VIN R99 750 3 U14 D10 1S1588 ADJ 1 3 1 L2 SN3-200 1 D A D VA25D A C101 47µ/16V RM5 0 C86 47µ/16V RM2 0 VD25D 2 A 2 A R97 270 A R114 270 VR7 500 R108 270 R106 240 2 LM317A VIN VOUT R110 750 3 U18 D17 1S1588 A R103 270 VR4 500 R94 240 2 LM317A VIN VOUT R100 750 3 U15 D1 1S15881 ADJ 1 3 1 1 ADJ 1 3 1 ADJ 1 3 1 ADJ 1 3 - 25 - 1 A A C112 10µ/16V D20 1S1588 C108 47µ/16V C97 10µ/16V C93 47µ/16V D14 1S1588 A C87 0.1µ A A C109 0.1µ C102 0.1µ A2.5V_A TP59 LC-2S-O L9 SN3-200 A 1 C94 0.1µ A2.5V_P TP56 L6 LC-2S-O SN3-200 1 TP51 LC-2S-R +5V A A A A C103 47µ/16V RM6 0 VA25A VA25P C88 47µ/16V RM3 0 CXD4016R 2 1 SW1 AB-15AH 3 - 26 - td = 60ms C116 4.7µ/16V T R115 10k C117 0.1µ D 1 2 3 4 R118 10k D C113 0.1µ R116 10k VD5 D G1 VCC A1 G2 A2 Y1 A3 Y2 Y3 A4 A5 Y4 A6 Y5 A7 Y6 A8 Y7 GND Y8 U21 20 19 18 17 16 15 14 13 12 11 VD25B TC74LCX541F 1 2 3 4 5 6 7 8 9 10 C115 0.1µ XRSTPW1 TP60 LC-2S-Y 1 XRSTPW2 XRSTPW1 td = 60ms C118 4.7µ/16V T CXD4016R EVB Circuit Diagram (RESET) 8 VCC 7 VsSENSE 6 RESET 5 RESET TL7705CP Vref RESIN Ct GND U19 VD5 C119 0.1µ D 1 2 3 4 VCC VsSENSE RESET RESET TL7705CP U20 Vref RESIN Ct GND 8 7 6 5 D R117 10k VD5 C114 0.1µ R119 10k VD5 XRSTPW2 TP61 LC-2S-Y 1 VD5 CXD4016R DAAOUT R122 300 C128 120p A A L12 12µH C127 27p L11 6.8µH A TP64 LC-2S-BK AGND 1 - 27 A C129 120p A C130 10p R123 0 3 1 A R125 2.2k A 3 IN– VCC 4 5 C124 0.1µ AD8057ART IN+ VEE OUT U22 A C122 3p CXD4016R EVB Circuit Diagram (RFOUT) A VR9 10k 2 C126 2200p R121 2.2k VA5 2 1 C121 3p A C125 2200p R120 1k VR8 10k 2 1 3 1 C120 0.1µ A R124 75 C123 0.1µ TP63 LC-2S-Y TX_LED 1 VA5 A 1 A J8 SMB A RF OUT J7 F-CONNECTOR NF-R-2 L10 68µH (Large Size) A IL-2P-S3EN2 J6 1 2 Emitter Voltage Source 2 TP62 LC-2S-BK AGND CXD4016R CXD4016R Pattern Diagram CXD4016R EVB A Side Pattern Diagram CXD4016R EVB B Side Pattern Diagram - 28 - CXD4016R CXD4016R EVB GND Layer Pattern Diagram CXD4016R EVB Power Supply Layer Pattern Diagram - 29 - CXD4016R CXD4016R EVB A Side Silk Diagram CXD4016R EVB B Side Silk Diagram - 30 - CXD4016R Package Outline (Unit : mm) 64PIN LQFP (PLASTIC) 12.0 ± 0.2 + 0.2 1.5 – 0.1 10.0 ± 0.1 33 48 49 32 A 17 64 1 16 0.5 b 0.08 S 0.08 M S 0.25 0.1 ± 0.1 0.145 ± 0.055 0.5 ± 0.2 0.6 ± 0.15 0.20 ± 0.05 DETAIL B 0° to 8° DETAIL A PACKAGE STRUCTURE SONY CODE LQFP-64P-L023 JEITA CODE P-LQFP64-10X10-0.5 JEDEC CODE PACKAGE MATERIAL EPOXY RESIN TERMINAL TREATMENT SOLDER PLATING TERMINAL MATERIAL 42 ALLOY PACKAGE MASS 0.32g LEAD PLATING SPECIFICATIONS ITEM - 31 - SPEC. LEAD MATERIAL 42 ALLOY SOLDER COMPOSITION Sn-2%Bi PLATING THICKNESS 5-20µm Sony Corporation