EL7531 Data Sheet December 10, 2015 Monolithic 1A Step-Down Regulator with Low Quiescent Current The EL7531 is a synchronous, integrated FET 1A step-down regulator with internal compensation. It operates with an input voltage range from 2.5V to 5.5V, which accommodates supplies of 3.3V, 5V, or a Li-Ion battery source. The output can be externally set from 0.8V to VIN with a resistive divider. The EL7531 features automatic PFM/PWM mode control, or PWM mode only. The PWM frequency is typically 1.4MHz and can be synchronized up to 12MHz. The typical no load quiescent current is only 120µA. Additional features include a Power-Good output, <1µA shut-down current, short-circuit protection, and over-temperature protection. The EL7531 is available in the 10 Ld MSOP package, making the entire converter occupy less than 0.15 in2 of PCB area with components on one side only. The 10 Ld MSOP package is specified for operation over the full -40°C to +85°C temperature range. Features • Less than 0.15 in2 (0.97 cm2) footprint for the complete 1A converter • Components on one side of PCB • Max height 1.1mm MSOP10 • Power-Good (PG) output • Internally-compensated voltage mode controller • Up to 94% efficiency • <1µA shut-down current • 120µA quiescent current • Overcurrent and over-temperature protection • External synchronizable up to 12MHz • Pb-Free plus anneal available (RoHS compliant) Applications • PDA and pocket PC computers Ordering Information PART PART NUMBER MARKING FN7428.10 TAPE & REEL PACKAGE PKG. DWG. # • Bar code readers • Cellular phones EL7531IYZ (Note) BHAAA - 10 Ld MSOP (Pb-free) M10.118A • Portable test equipment EL7531IYZ-T7 (Note) BHAAA 7” 10 Ld MSOP (Pb-free) M10.118A • Li-Ion battery powered devices EL7531IYZ-T13 (Note) BHAAA 13” 10 Ld MSOP (Pb-free) M10.118A • Small form factor (SFP) modules Typical Application Diagram NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout VS (2.5V to 5.5V) R3 100 C2 10µF LX EL7531 R5 100k EN R4 100k 1 SGND FB 10 2 PGND VO 9 3 LX PG 8 4 VIN EN 7 5 VDD R1* 124k PG EL7531 (10 LD MSOP) TOP VIEW R6 100k 1.8µH C1 10µF VDD C3 0.1µF VO L1 VIN FB SYNC PGND SGND R2* 100k VO C4 470pF (1.8V @ 1A) * VO = 0.8V * (1 + R1 / R2) SYNC 6 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas LLC Copyright © Intersil Americas LLC 2004, 2005, 2006, 2015. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL7531 Absolute Maximum Ratings (TA = 25°C) VIN, VDD, PG to SGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) SYNC, EN, VO, FB to SGND . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2A Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V (as shown in Typical Application Diagram), unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 790 800 810 mV DC CHARACTERISTICS VFB Feedback Input Voltage PWM mode VOUT/VOUT VFB vs Temperature Junction temperature = -40°C to +85°C (see Figure 7) 0.3 % VOUT/VOUT Line Regulation VIN = 3.3V to 5V, IO = 1A (see Figure 7) 0.1 % VOUT/VOUT Load Regulation IO = 0A to 1A, VIN = 3.3V (see Figure 7) 0.4 % IFB Feedback Input Current 100 nA 2.5 5.5 V VIN, VDD Input Voltage VIN,OFF Minimum Voltage for Shutdown VIN falling 2 2.2 V VIN,ON Maximum Voltage for Startup VIN rising 2.2 2.4 V IS Input Supply Quiescent Current Active - PFM Mode VSYNC = 0V 120 145 µA Active - PWM Mode VSYNC = 3.3V 6.5 7.5 mA Supply Current PWM, VIN = VDD = 5V 400 500 µA EN = 0, VIN = VDD = 5V 0.1 1 µA RDS(ON)-PMOS PMOS FET Resistance VDD = 5V, wafer test only 70 100 m RDS(ON)-NMOS NMOS FET Resistance VDD = 5V, wafer test only 45 75 m IDD ILMAX Current Limit 1.5 A TOT,OFF Over-temperature Threshold T rising 145 °C TOT,ON Over-temperature Hysteresis T falling 130 °C EN, SYNC Current VEN, VRSI = 0V and 3.3V -1 VEN1, VSYNC1 EN, SYNC Rising Threshold VDD = 3.3V 2.4 1.8 VEN2, VSYNC2 EN, SYNC Falling Threshold VDD = 3.3V 9 1.4 Minimum VFB for PG, WRT Targeted VFB Value VFB rising PG Voltage Drop ISINK = 3.3mA IEN, ISYNC VPG VOLPG VFB falling 1 µA V 0.8 V 95 % 86 % 35 70 mV 1.4 1.6 MHz AC CHARACTERISTICS FPWM PWM Switching Frequency tSYNC Minimum SYNC Pulse Width tSS Soft-start Time 1.25 Guaranteed by design 25 ns 650 2 µs FN7428.10 December 10, 2015 EL7531 Pin Descriptions PIN NUMBER PIN NAME PIN FUNCTION 1 SGND Negative supply for the controller stage 2 PGND Negative supply for the power stage 3 LX Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage 4 VIN Positive supply for the power stage 5 VDD Power supply for the controller stage 6 SYNC 7 EN Enable 8 PG Power-Good open drain output 9 VO Output voltage sense 10 FB Voltage feedback input; connected to an external resistor divider between VO and SGND for variable output SYNC input pin; when connected to HI, regulator runs at forced PWM mode; when connected to Low, auto PFM/PWM mode; when connected to external sync signal, at external PWM frequency up to 12MHz Block Diagram 100 0.1µF C4 VDD INDUCTOR SHORT VO + CURRENT SENSE 10pF 124K 470pF FB 5M + PWM COMPENSATION 100K SYNC SYNC RAMP GENERATOR EN EN SOFTSTART 10µF 3.3V CLOCK + – BANDGAP REFERENCE + PWM COMPARATOR PFM ON-TIME CONTROL + PWM COMPARATOR UNDERVOLTAGE LOCKOUT TEMPERATURE SENSE SGND VIN P-DRIVER LX CONTROL LOGIC 1.8V 0 TO 1A 10µF N-DRIVER + SYNCHRONOUS RECTIFIER 1.8µH PGND 100K PG PG POWER GOOD 3 FN7428.10 December 10, 2015 EL7531 Performance Curves and Waveforms All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 1A with component values shown on page 1 at room ambient temperature, unless otherwise noted. 100 90 VO = 2.5V 90 85 80 75 VO = 1.8V VO = 1.5V 70 VO = 1.0V 65 VO = 0.8V 60 VO = 1.2V 55 VO = 3.3V 80 EFFICIENCY (%) EFFICIENCY (%) 100 VO = 3.3V 95 VO = 1.0V 30 10 0.100 VO = 1.2V 40 20 0.010 VO = 1.5V 50 45 VIN = 5V VO = 1.8V 60 50 40 0.001 VO = 2.5V 70 VO = 0.8V VIN = 5V 0 0.001 1.000 0.010 IO (A) FIGURE 1. EFFICIENCY vs IO (PFM/PWM MODE) 100 95 100 VO = 2.5V VO = 1.8V 85 80 VO = 1.5V 75 VO = 1.2V VO = 1.0V 70 65 60 VO = 2.5V 90 VO = 0.8V 55 80 VO = 1.8V 70 VO = 1.5V VO = 1.2V 60 50 VO = 1.0V 40 30 20 50 VO = 0.8V 10 45 VIN = 3.3V 40 0.001 0.010 IO (A) 0.100 VIN = 3.3V 0 0.001 1.000 0.010 0.100 1.000 IO (A) FIGURE 3. EFFICIENCY vs IO (PFM/PWM MODE) FIGURE 4. EFFICIENCY vs IO (PWM MODE) 1.44 0.1% VIN = 3.3V IO = 1A VIN = 5V IO = 1A VIN = 5V IO = 0A 1.42 0.0% 1.4 VO CHANGES FS (MHz) 1.000 FIGURE 2. EFFICIENCY vs IO (PWM MODE) EFFICIENCY (%) EFFICIENCY (%) 90 0.100 IO (A) VIN = 3.3V IO = 0A 1.38 1.36 1.34 1.32 -50 -0.1% VIN = 3.3V -0.2% VIN = 5V -0.3% -0.4% -0.5% 0 50 100 150 TA (°C) FIGURE 5. FS vs JUNCTION TEMPERATURE (PWM MODE) 4 0 0.2 0.4 0.6 0.8 1 IO (A) FIGURE 6. LOAD REGULATIONS (PWM MODE) FN7428.10 December 10, 2015 EL7531 Performance Curves and Waveforms (Continued) All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 1A with component values shown on page 1 at room ambient temperature, unless otherwise noted. 0.1% 12 0.0% VIN = 5V IO = 0A 8 -0.2% -0.3% IS (mA) VO CHANGES 10 VIN = 3.3V IO = 0A -0.1% VIN = 3.3V IO = 1A -0.4% 6 4 -0.5% -0.6% VIN = 5V IO = 1A -0.7% -50 0 2 50 100 0 150 2.5 3 3.5 TJ (°C) FIGURE 7. PWM MODE LOAD/LINE REGULATIONS vs JUNCTION TEMPERATURE 100 VO = 3.3V VO = 1.8V 120 EFFICIENCY (%) IS (µA) 90 5 1.4MHz 80 110 100 4.5 FIGURE 8. NO LOAD QUIESCENT CURRENT (PWM MODE) 140 130 4 VS (V) VO = 1.5V VO = 1.2V VO = 1.0V VO = 0.8V 80 70 5MHz 12MHz 60 40 20 60 50 2.0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 200 400 VS (V) 600 800 1K 1.2K IO (mA) FIGURE 9. NO LOAD QUIESCENT CURRENT (PFM MODE) FIGURE 10. EFFICIENCY vs IO (PWM MODE) 1 0.5 12MHz 0.3 VO CHANGES (%) VO CHANGES (%) 0.6 1.4MHz 0.2 5MHz 0 -0.2 -0.6 12MHz 0.1 1.4MHz -0.1 5MHz -0.3 0 200 400 600 800 1K 1.2K IO (mA) FIGURE 11. LOAD REGULATION (PWM MODE) 5 -0.5 2.5 3 3.5 4 4.5 5 5.5 VIN (V) FIGURE 12. LINE REGULATION @ 500mA (PWM MODE) FN7428.10 December 10, 2015 EL7531 Performance Curves and Waveforms (Continued) All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 1A with component values shown on page 1 at room ambient temperature, unless otherwise noted. VIN (2V/DIV) EN IIN (0.5A/DIV) IIN (0.5A/DIV) VO (2V/DIV) VO (2V/DIV) PG PG 500µs/DIV 200µs/DIV FIGURE 13. START-UP AT IO = 1A FIGURE 14. ENABLE AND SHUT-DOWN LX (2V/DIV) LX (2V/DIV) IL (0.5A/DIV) IL (0.5A/DIV) VO (10mV/DIV) VO (50mV/DIV) 0.5µs/DIV 2µs/DIV FIGURE 15. PFM STEADY-STATE OPERATION WAVEFORM (IO = 100mA) SYNC (2V/DIV) SYNC (2V/DIV) LX (2V/DIV) IL (0.5A/DIV) LX (2V/DIV) IL (0.5A/DIV) 0.2µs/DIV FIGURE 17. EXTERNAL SYNCHRONIZATION TO 2MHz 6 FIGURE 16. PWM STEADY-STATE OPERATION (IO = 1A) 20ns/DIV FIGURE 18. EXTERNAL SYNCHRONIZATION TO 12MHz FN7428.10 December 10, 2015 EL7531 Performance Curves and Waveforms (Continued) All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 1A with component values shown on page 1 at room ambient temperature, unless otherwise noted. IO (0.5A/DIV) IO (0.5A/DIV) VO (100mV/DIV) VO (100mV/DIV) 50µs/DIV 100µs/DIV FIGURE 19. LOAD TRANSIENT RESPONSE (22mA to 1A) FIGURE 20. PWM LOAD TRANSIENT RESPONSE (0A TO 1A) IO=150mA SYNC (2V/DIV) IO (0.5A/DIV) VO (100mV/DIV) LX (2V/DIV) 2µs/DIV 50µs/DIV FIGURE 21. PWM LOAD TRANSIENT RESPONSE (0.25A TO 0.75A) FIGURE 22. PFM-PWM TRANSITION TIME 3 IO=50mA SYNC (2V/DIV) LX (2V/DIV) VO CHANGES (%) 2 1 0 -1 PFM PWM -2 -3 0 200 400 600 800 1000 1200 IOUT (mA) 2µs/DIV FIGURE 23. PFM-PWM TRANSITION TIME 7 FIGURE 24. PFM-PWM LOAD REGULATION FN7428.10 December 10, 2015 EL7531 Performance Curves and Waveforms (Continued) All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 1A with component values shown on page 1 at room ambient temperature, unless otherwise noted. 1 0.4 M JA = 0.3 SO P1 20 0 6° C/ W 0.2 0.1 0 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 870mW 0.9 486mW 0.5 POWER DISSIPATION (W) POWER DISSIPATION (W) 0.6 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.8 0.7 JA = 0.6 0.5 M SO P1 11 0 5° C/ W 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 8 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7428.10 December 10, 2015 EL7531 Applications Information Product Description The EL7531 is a synchronous, integrated FET 1A step-down regulator which operates from an input of 2.5V to 5.5V. The output voltage is user-adjustable with a pair of external resistors. When the load is very light, the regulator automatically operates in the PFM mode, thus achieving high efficiency at light load (>70% for 1mA load). When the load increases to typically 250mA, the regulator automatically switches over to a voltage-mode PWM operating at nominal 1.4MHz switching frequency. The efficiency is up to 94%. It can also operate in a fixed PWM mode or be synchronized to an external clock up to 12MHz for improved EMI performance. PFM Operation The heart of the EL7531 regulator is the automatic PFM/PWM controller. If the SYNC pin is connected to ground, the regulator operates automatically in either the PFM or PWM mode, depending on load. When the SYNC pin is connected to VIN, the regulator operates in the fixed PWM mode. When the pin is connected to an external clock ranging from 1.6MHz to 12MHz, the regulator is in the fixed PWM mode and synchronized to the external clock frequency. In the automatic PFM/PWM operation, when the load is light, the regulator operates in the PFM mode to achieve high efficiency. The top P channel MOSFET is turned on first. The inductor current increases linearly to a preset value before it is turned off. Then the bottom N channel MOSFET turns on, and the inductor current linearly decreases to zero current. The N channel MOSFET is then turned off, and an antiringing MOSFET is turned on to clamp the VLX pin to VO. The inductor current looks like triangular pulses. The frequency of the pulses is mainly a function of output current. The higher the load, the higher the frequency of the pulses until the inductor current becomes continuous. At this point, the controller automatically changes to PWM operation. When the controller transitions to PWM mode, there can be a perturbation to the output voltage. This perturbation is due to the inherent behavior of switching converters when transitioning between two control loops. To reduce this effect, it is recommended to use the phase-lead capacitor (C4) shown in the Typical Application Diagram on page 1. This capacitor allows the PWM loop to respond more quickly to this type of perturbation. To properly size C4, refer to the Component Selection section. 9 PWM Operation The regulator operates the same way in the forced PWM or synchronized PWM mode. In this mode, the inductor current is always continuous and does not stay at zero. In this mode, the P channel MOSFET and N channel MOSFET always operate complementary. When the PMOSFET is on and the NMOSFET off, the inductor current increases linearly. The input energy is transferred to the output and also stored in the inductor. When the P channel MOSFET is off and the N channel MOSFET on, the inductor current decreases linearly, and energy is transferred from the inductor to the output. Hence, the average current through the inductor is the output current. Since the inductor and the output capacitor act as a low pass filter, the duty cycle ratio is approximately equal to VO divided by VIN. The output LC filter has a second order effect. To maintain the stability of the converter, the overall controller must be compensated. This is done with the fixed internally compensated error amplifier and the PWM compensator. Because the compensations are fixed, the values of input and output capacitors are 10µF to 22µF ceramic and inductor is 1.5µH to 2.2µH. Forced PWM Mode/SYNC Input Pulling the SYNC pin HI (>2.5V) forces the converter into PWM mode in the next switching cycle regardless of output current. The duration of the transition varies depending on the output current. Figures 22 and 23 (under two different loading conditions) show the device goes from PFM to PWM mode. Note: In forced PWM mode, the IC will continue to start-up in PFM mode to support pre-biased load applications. Start-Up and Shut-Down When the EN pin is tied to VIN, and VIN reaches approximately 2.4V, the regulator begins to switch. The inductor current limit is gradually increased to ensure proper soft-start operation. When the EN pin is connected to a logic low, the EL7531 is in the shut-down mode. All the control circuitry and both MOSFETs are off, and VOUT falls to zero. In this mode, the total input current is less than 1µA. When the EN reaches logic HI, the regulator repeats the start-up procedure, including the soft-start function. Current Limit and Short-Circuit Protection The current limit is set at about 2A for the PMOS. When a short-circuit occurs in the load, the preset current limit restricts the amount of current available to the output, which causes the output voltage to drop below the preset voltage. In the meantime, the excessive current heats up the regulator until it reaches the thermal shut-down point. FN7428.10 December 10, 2015 EL7531 Thermal Shut-Down Once the junction reaches about 145°C, the regulator shuts down. Both the P channel and the N channel MOSFETs turn off. The output voltage will drop to zero. With the output MOSFETs turned off, the regulator will soon cool down. Once the junction temperature drops to about 130°C, the regulator will restart again in the same manner as EN pin connects to logic HI. Thermal Performance The EL7531 is available in a fused-lead MSOP10 package. Compared with regular MSOP10 package, the fused- lead package provides lower thermal resistance. The JA is 100°C/W on a 4-layer board and 125°C/W on 2-layer board. Maximizing the copper area around the pins will further improve the thermal performance. Power Good Output The PG (pin 8) output is used to indicate when the output voltage is properly regulating at the desired set point. It is an open-drain output that should be tied to VIN or VCC through a 100k resistor. If no faults are detected, EN is high, and the output voltage is within ~5% of regulation, the PG pin will be allowed to go high. Otherwise, the open-drain NMOS will pull PG low. Output Voltage Selection Users can set the output voltage of the variable version with a resister divider, which can be chosen based on the following formula: R 2 V O = 0.8 1 + ------- R 1 The inductor must be able to handle IO for the RMS load current, and to assure that the inductor is reliable, it must handle the 2A surge current that can occur during a current limit condition. In addition to decoupling capacitors and inductor value, it is important to properly size the phase-lead capacitor C4 (Refer to the Typical Application Diagram). The phase-lead capacitor creates additional phase margin in the control loop by generating a zero and a pole in the transfer function. As a general rule of thumb, C4 should be sized to start the phaselead at a frequency of ~2.5kHz. The zero will always appear at lower frequency than the pole and follow the equation below: 1 f Z = ---------------------2R 2 C 4 Over a normal range of R2 (~10-100k), C4 will range from ~470-4700pF. The pole frequency cannot be set once the zero frequency is chosen as it is dictated by the ratio of R1 and R2, which is solely determined by the desired output set point. The equation below shows the pole frequency relationship: 1 f P = --------------------------------------2 R 1 R 2 C 4 Layout Considerations The layout is very important for the converter to function properly. The following PC layout guidelines should be followed: 1. Separate the Power Ground ( ) and Signal Ground ( ); connect them only at one point right at the pins Component Selection Because of the fixed internal compensation, the component choice is relatively narrow. For a regulator with fixed output voltage, only two capacitors and one inductor are required. We recommend 10µf to 22µF multi-layer ceramic capacitors with X5R or X7R rating for both the input and output capacitors, and 1.5 to 2.2µH for the inductor. The RMS current present at the input capacitor is decided by the following formula: V O V IN – V O I INRMS = ----------------------------------------------- I O V IN 2. Place the input capacitor as close to VIN and PGND pins as possible 3. Make the following PC traces as small as possible: 4. from LX pin to L 5. from CO to PGND 6. If used, connect the trace from the FB pin to R1 and R2 as close as possible 7. Maximize the copper area around the PGND pin 8. Place several via holes under the chip to additional ground plane to improve heat dissipation The demo board is a good example of layout based on this outline. Please refer to the EL7531 Application Brief. This is about half of the output current IO for all the VO. This input capacitor must be able to handle this current. The inductor peak-to-peak ripple current is given as: V IN – V O V O I IL = -------------------------------------------L V IN f S L is the inductance fS the switching frequency (nominally 1.4MHz) 10 FN7428.10 December 10, 2015 EL7531 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION December 10, 2015 FN7428.10 CHANGE - Updated Ordering Information Table on page 1. - Added Revision History. - Added About Intersil Verbiage. - Replaced POD from MDP0043 to M10.118A. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN7428.10 December 10, 2015 EL7531 Package Outline Drawing M10.118A (JEDEC MO-187-BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 3.0 ± 0.1 A 0.25 10 DETAIL "X" CAB 0.18 ± 0.05 SIDE VIEW 2 4.9 ± 0.15 3.0 ± 0.1 1.10 Max B PIN# 1 ID 1 2 0.95 BSC 0.5 BSC TOP VIEW Gauge Plane 0.86 ± 0.09 H 0.25 C 3°±3° SEATING PLANE 0.10 ± 0.05 0.23 +0.07/ -0.08 0.08 C A B 0.55 ± 0.15 0.10 C DETAIL "X" SIDE VIEW 1 5.80 4.40 3.00 NOTES: 0.50 0.30 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. Plastic interlead protrusions of 0.25mm max per side are not included. 4. 1.40 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. TYPICAL RECOMMENDED LAND PATTERN 6. This replaces existing drawing # MDP0043 MSOP10L. 12 FN7428.10 December 10, 2015