tb459

Using the ISL6269 and ISL6269A for
5V VOUT Applications
®
Technical Brief
Description
This document specifies the requirements for the extended
output voltage regulation range of the ISL6269 and
ISL6269A Single-Phase Synchronous-Buck PWM
controllers. The application space specified within the
ISL6269 and ISL6269A datasheets is +7.0V to +25.0V input
voltage and +0.6V to +3.3V output voltage. The application
space may be amended to accommodate an output voltage
of 5V when the requirements of this document are followed.
Requirements
• The input voltage of the converter must be between
+12.0V to +25.0V.
• The FCCM pin must be connected to the VCC pin, forcing
the converter into continuous conduction mode. If allowed
into discontinuous conduction mode at low load, the
bootstrap capacitor voltage could discharge to 0V during
the time interval between PWM pulses.
TB459.0
May 22, 2006
The static VCOMP voltage increases as VOUT, ILOAD, and
duty cycle increases. The duty cycle increases as VIN
decreases or in response to a load transient. As the slew rate
of the transient becomes faster, the ΔVCOMP becomes larger.
A minimum VIN of 12V has been established so that VCOMP
does not hit an internal 3.20V clamp in applications where
VOUT is programmed to 5V. The voltage clamp ensures that
there will be sufficient head room above VCOMP so that the
window voltage VW, which can be as large as 900mV, does
not saturate at the minimum specified VCC input bias voltage
of 4.75V. A graphical representation of the VCOMP range is
found in Figure 4. The waveforms in Figure 2 show the
transient response of the 5V converter at 7V VIN and a
transient load of 1Ω. Notice that the duty cycle goes to 100%,
VOUT starts falling, and VCOMP hits the 3.20V clamp.
Vcomp
VOUT
VLoad_1Ω
• A 499Ω resistor RMS is placed in series with the VO pin to
protect the internal ESD diode that is connected to VCC.
The ESD diode will conduct current into the VCC node in
the unlikely event where the tolerance stack up of VCC,
VFB, IFB, VOVR, RTOP, and RBOTTOM results in a voltage
sufficient to forward bias the device. Refer to Figure 5.
ILo
VCOMP and Duty Cycle
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR across ripple capacitor CR is
compared. Figure 1 shows PWM pulses being generated as
VR traverses the VW and VCOMP thresholds.
Ripple Capacitor Voltage CR
Window Voltage VW
FIGURE 2. TRANSIENT RESPONSE AT 7V VIN
The waveforms in Figure 3 show the transient response of
the 5V converter at 15V VIN and a transient load of 1Ω.
Notice that VOUT stays well regulated and VCOMP avoids
the 3.20V clamp.
Vcomp
VOUT
VLoad_1Ω
Error Amplifier Voltage VCOMP
PWM
ILo
FIGURE 1. MODULATOR LOAD TRANSIENT WAVEFORMS
FIGURE 3. TRANSIENT RESPONSE AT 15V VIN
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Intersil Americas Inc. 2006. All Rights Reserved
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Technical Brief 459
5V
VIN
12V-25V
VCC nominal
VIN
5V
RVCC
VCC
BOOT
GND
PHASE
VCOMP 3.20V
upper clamp
ISEN
CBOOT
FCCM
CVCC
CPVCC
VW range
900mV
QHIGH_SIDE
UG
PVCC
4V
CIN
ISL6269
ISL6269A
RSEN
Headroom
PGOOD
RPGOOD
VOUT
5.0V
LOUT
COUT
3V
QLOW_SIDE
EN
VCOMP range
2V
RCOMP
LG
COMP
PGND
CCOMP1
FB
CCOMP2
VO
FSET
RMS
RFSET
CFSET
RBOTTOM RTOP
1V
FIGURE 5. SCHEMATIC OF 5V VOUT APPLICATION
VR 500mV
lower clamp
0V
FIGURE 4. VCOMP RANGE
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verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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TB459.0
May 22, 2006