Data Sheet ESIGNS R NEW D NT O F D E D N EM E COMME R E PL AC D E NO T R E r at D N OMME ort Cente sc pp2009 u S l NO REC a /t ic June 25, m n o h tersil.c our Tec contact ERSIL or www.in T 1-888-IN High-Performance Notebook PWM Controller with Bias Regulator and Audio-Frequency Clamp • High performance R3 technology Intersil’s R3 technology combines the best features of fixedfrequency PWM and hysteretic PWM while eliminating many of their shortcomings. R3 technology employs an innovative modulator that synthesizes an AC ripple voltage signal VR, analogous to the output inductor ripple current. The AC signal VR enters a window comparator where the lower threshold is the error amplifier output VCOMP, and the upper threshold is a programmable voltage reference VW, resulting in generation of the PWM signal. The voltage reference VW sets the steady state PWM frequency. Both edges of the PWM can be modulated in response to input voltage transients and output load transients, much faster than conventional fixed frequency PWM controllers. Unlike a conventional hysteretic converter, the ISL6269 has an error amplifier that provides ±1% voltage regulation at the FB pin. The ISL6269 has a 1.5ms digital soft-start and can be started into a pre-biased output voltage. A resistor divider is used to program the output voltage setpoint. The ISL6269 can be configured to operate in continuous-conduction-mode (CCM) or diode-emulation-mode (DEM), which improves light-load efficiency. In CCM the controller always operates as a synchronous rectifier however, when DEM is enabled the low-side MOSFET is permitted to stay off, blocking negative current flow into the low-side MOSFET from the output inductor. PGOOD PHASE UG BOOT 15 14 13 VCC 2 11 LG FCCM 3 10 PGND EN 4 9 1 VO FB 8 FSET COMP 7 • Output voltage range: +0.6V to +3.3V • Wide output load range: 0A to 25A • Selectable diode emulation mode for increased light load efficiency • Programmable PWM frequency: 200kHz to 600kHz • Pre-biased output start-up capability • Internal 5V LDO for self-biasing • Integrated MOSFET drivers and bootstrap diode • Internal digital soft-start • Power good monitor • PWM minimum frequency above audible spectrum • Fault protection - Undervoltage protection - Soft crowbar overvoltage protection - Low-side MOSFET rDS(ON) overcurrent protection - Over-temperature protection - Fault identification by PGOOD pull-down resistance • Pb-free (RoHS compliant) Applications • PCI express graphical processing unit • Auxiliary power rail PART NUMBER (Note) 12 PVCC 6 • Wide input voltage range: +7.0V to +25.0V Ordering Information 1 5 • +0.6V Internal Reference - ±0.6% tolerance over the commercial temperature range (0°C to +70°C) - ±1.0% tolerance over the industrial temperature range (-40°C to +85°C) • Network adapter VIN GND • Fast transient response • VRM ISL6269 (16 LD 4x4 QFN) TOP VIEW 16 FN9177.3 Features The ISL6269 IC is a Single-Phase Synchronous-Buck PWM controller featuring Intersil's Robust Ripple Regulator (R3) technology that delivers truly superior dynamic response to input voltage and output load transients. Integrated MOSFET drivers, 5V LDO and bootstrap diode result in fewer components and smaller implementation area. Pinout ISL6269 ISEN PART MARKING TEMP RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL6269CRZ* 62 69CRZ -10 to +100 16 Ld 4x4 QFN L16.4x4 ISL6269IRZ* 62 69IRZ -40 to +100 16 Ld 4x4 QFN L16.4x4 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas LLC 2006, 2007, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Block Diagram VIN VO PACKAGE BOTTOM 5V LDO PWM FREQUENCY CONTROL VCC VREF VW 2 gmVIN EN FSET GND R PWM Q OVP gmVO UVP CR VCOMP S BOOT EA DRIVER POR DIGITAL SOFT-START PWM CONTROL FB COMP ISEN OCP IOC 30 90 UG 60 PHASE SHOOT THROUGH PROTECTION PVCC DRIVER LG 150°OT PGND PGOOD FCCM FN9177.3 June 25, 2009 FIGURE 1. SCHEMATIC BLOCK DIAGRAM ISL6269 VR ISL6269 Typical Application ISL6269 VIN 7V TO 25V PGOOD VIN CIN RPGOOD QHIGH_SIDE PVCC UG RPVCC VCC BOOT CVCC CPVCC CBOOT GND VOUT LOUT 0.6V TO 3.3V PHASE COUT RSEN FCCM ISEN QLOW_SIDE EN LG RCOMP COMP PGND CCOMP1 FB VO CCOMP2 FSET RFSET RBOTTOM CFSET RTOP FIGURE 2. ISL6269 TYPICAL APPLICATION SCHEMATIC 3 FN9177.3 June 25, 2009 ISL6269 Absolute Voltage Ratings Thermal Information ISEN, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V VCC, PGOOD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V EN, FCCM . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +3.3V VO, FB, COMP, FSET . . . . . . . . . . . . . . . -0.3V to GND, VCC +0.3V PHASE to GND (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V (<100ns Pulse Width, 10µJ) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0V BOOT to GND, or PGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V UG (DC) . . . . . . . . . . . . . . . . . . . . . . .-0.3V to PHASE, BOOT +0.3V (<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . -4.0V LG (DC) . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to PGND, PVCC +0.3V (<100ns Pulse Width, 4µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V Thermal Resistance (Typical, Notes 1, 2) JA (°C/W) JC (°C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 48 11.5 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISL6269CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +100C ISL6269IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range ISL6269CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C ISL6269IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . . . 7V to 25V PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C, PVCC = 5V, VIN = 15V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VIN VIN Input Voltage Range VVIN VIN Input Bias Current IVIN VIN Shutdown Current EN = 5V, VIN = 25V IVIN_SHDN EN = GND, VIN= 25V 7.0 - 25 V - 2.2 3.0 mA - 0.1 1.0 µA 4.75 5.00 5.25 V 4.45 4.55 V VCC LDO VCC Output Voltage Range VVCC VIN = 7V to 25V, IVCC = 0mA to 80mA Rising VCC POR Threshold Voltage VVCC_THR TA = -10°C to +100°C 4.35 4.33 4.45 4.55 V Falling VCC POR Threshold Voltage V 4.10 4.20 4.30 V 4.08 4.20 4.30 V - 0.1 1.0 µA - 0.6 - V VCC_THF TA = -10°C to +100°C PVCC PVCC Shutdown Current IPVCC_SHDN EN = GND, PVCC = 5V REGULATION Reference Voltage VREF Voltage Regulation Accuracy V REG FB connected to COMP, TA = -10°C to +100°C -0.6 - +0.6 % FB connected to COMP, TA = -40°C to +100°C -1.0 - +1.0 % FCCM = 5V 200 - 600 kHz FCCM = GND, TA = -10°C to +100°C 19 28 - kHz FCCM to GND 18 28 - kHz fSW = 300kHz -12 - +12 % 0.60 - 3.30 V PWM Frequency Range fSW fAUDIO Frequency-Set Accuracy VO Range VVO 4 FN9177.3 June 25, 2009 ISL6269 Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C, PVCC = 5V, VIN = 15V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL VO Input Leakage IVO MIN TYP MAX UNIT VO = 0.60V TEST CONDITIONS - 1.3 - µA VO = 3.30V - 7.0 - µA FB = 0.60V -0.5 - +0.5 µA ERROR AMPLIFIER FB Input Bias Current IFB COMP Source Current ICOMP_SRC FB = 0.40V, COMP = 3.20V - 2.5 - mA COMP Sink Current ICOMP_SNK FB = 0.80V, COMP = 0.30V - 0.3 - mA COMP High Clamp Voltage VCOMP_HC FB = 0.40V, Sink 50µA 3.10 3.40 3.65 V COMP Low Clamp Voltage VCOMP_LC FB = 0.80V, Source 50µA 0.09 0.15 0.21 V POWER GOOD PGOOD Pull-down Impedance PGOOD = 5mA Sink, TA = -10°C to +100°C 75 95 125 PGOOD = 5mA Sink 67 95 125 RPG_UV PGOOD = 5mA Sink, TA = -10°C to +100°C 75 95 125 PGOOD = 5mA Sink 67 95 125 RPG_OV PGOOD = 5mA Sink, TA = -10°C to +100°C 50 63 85 PGOOD = 5mA Sink 45 63 85 RPG_OC PGOOD = 5mA Sink, TA = -10°C to +100°C 25 32 45 PGOOD = 5mA Sink 22 32 45 IPGOOD PGOOD = 5V - 0.1 1.0 µA - 5.0 - mA RPG_SS PGOOD Leakage Current PGOOD Maximum Sink Current PGOOD Soft-Start Delay tSS EN High to PGOOD High, TA = -10°C to +100°C 2.20 2.75 3.30 ms EN High to PGOOD High 2.20 2.75 3.50 ms GATE DRIVER UG Pull-Up Resistance RUGPU 200mA Source Current - 1.0 1.5 UG Source Current IUGSRC UG - PHASE = 2.5V - 2.0 - A UG Sink Resistance RUGPD 250mA Sink Current - 1.0 1.5 UG Sink Current IUGSNK UG - PHASE = 2.5V - 2.0 - A LG Pull-Up Resistance RLGPU 250mA Source Current - 1.0 1.5 LG Source Current ILGSRC LG - PGND = 2.5V - 2.0 - A LG Sink Resistance RLGPD 250mA Sink Current - 0.5 0.9 ILGSNK LG Sink Current LG - PGND = 2.5V - 4.0 - A UG to LG Deadtime tUGFLGR UG falling to LG rising, no load - 21 - ns LG to UG Deadtime tLGFUGR LG falling to UG rising, no load - 14 - ns BOOTSTRAP DIODE Forward Voltage VF PVCC = 5V, IF = 2mA - 0.58 - V Reverse Leakage IR VR = 25V - 0.2 - µA CONTROL INPUTS EN High Threshold VENTHR 2.0 - - V EN Low Threshold VENTHF - - 0.5 V FCCM High Threshold VFCCMTHR 2.0 - - V FCCM Low Threshold VFCCMTHF EN Leakage 5 - - 1.0 V IENL EN = 0V - 0.1 1.0 µA IENH EN = 5.0V - 20 - µA FN9177.3 June 25, 2009 ISL6269 Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C, PVCC = 5V, VIN = 15V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL FCCM Leakage MIN TYP MAX UNIT IFCCML FCCM = 0V TEST CONDITIONS - 0.1 1.0 µA IFCCMH FCCM = 5.0V - 2.0 - µA ISEN sourcing, TA = -10°C to +100°C 19 26 33 µA ISEN sourcing 17 26 33 µA PROTECTION ISEN OCP Threshold IOC ISEN Short-Circuit Threshold ISC - 50 - µA UVP Threshold VUV 81 84 87 % OVP Rising Threshold VOVR 113 116 119 % OVP Falling Threshold VOVF 100 103 106 % OTP Rising Threshold TOTR - 150 - °C TOTHYS - 25 - °C OTP Hysteresis ISEN sourcing Functional Pin Descriptions FB (Pin 6) The VIN pin measures the converter input voltage which is a required input to the R3 PWM modulator. The VIN pin is also the input source for the integrated +5V LDO regulator. Connect across the drain of the high-side MOSFET to the GND pin. The FB pin is the inverting input of the control-loop error amplifier. The converter output voltage regulates to 600mV from the FB pin to the GND pin. Program the desired output voltage with a resistor network connected across the VO, FB, and GND pins. Select the resistor values such that FB to GND is 600mV when the converter output voltage is at the programmed regulation value. VCC (Pin 2) FSET (Pin 7) The VCC pin is the output of the integrated +5V LDO regulator, which provides the bias voltage for the IC. The VCC pin delivers regulated +5V whenever the EN pin is pulled above VENTHR. For best performance the LDO requires at least a 1µF MLCC decouple capacitor to the GND pin. The FSET pin programs the PWM switching frequency. Program the desired PWM frequency with a resistor and a capacitor connected across the FSET and GND pins. VIN (Pin 1) FCCM (Pin 3) The FCCM pin configures the controller to operate in forcedcontinuous-conduction-mode (FCCM) or diode-emulationmode (DEM). DEM is disabled when the FCCM pin is pulled above the rising threshold voltage VFCCMTHR, conversely DEM is enabled when the FCCM pin is pulled below the falling threshold voltage VFCCMTHF. EN (Pin 4) The EN pin is the on/off switch of the IC. When the EN pin is pulled above the rising threshold voltage VENTHR, the VCC 5V LDO ramps and begins regulating. The soft-start sequence begins after VVCC is above the power-on reset (POR) rising threshold voltage VVCC_THR . When the EN pin is pulled below the falling threshold voltage VENTHF, PWM immediately stops and VVCC decays below the POR falling threshold voltage VVCC_THF, at which time the IC turns off. COMP (Pin 5) The COMP pin is the output of the control-loop error amplifier. Compensation components for the control-loop connect across the COMP and FB pins. 6 VO (Pin 8) The VO pin measures the converter output voltage and is used exclusively as an input to the R3 PWM modulator. Connect at the physical location where the best output voltage regulation is desired. ISEN (Pin 9) The ISEN pin programs the threshold of the OCP overcurrent fault protection. Program the desired OCP threshold with a resistor connected across the ISEN and PHASE pins. The OCP threshold is programmed to detect the peak current of the output inductor. The peak current is the sum of the DC and AC components of the inductor current. PGND (Pin 10) The PGND pin conducts the turn-off transient current through the LG gate driver. The PGND pin must be connected to complete the pull-down circuit of the LG gate driver. The PGND pin should be connected to the source of the low-side MOSFET through a low impedance path, preferably in parallel with the trace connecting the LG pin to the gate of the low-side MOSFET. The adaptive shootthrough protection circuit, measures the low-side MOSFET gate-source voltage from the LG pin to the PGND pin. FN9177.3 June 25, 2009 ISL6269 LG (Pin 11) The LG pin is the output of the low-side MOSFET gate driver. Connect to the gate of the low-side MOSFET. PVCC (Pin 12) The PVCC pin is the input voltage bias for the LG low-side MOSFET gate driver. Connect +5V from the PVCC pin to the PGND pin. Decouple with at least 1µF of an MLCC capacitor across the PVCC and PGND pins. The VCC output may be used for the PVCC input voltage source. BOOT (Pin 13) The BOOT pin stores the input voltage for the UG high-side MOSFET gate driver. Connect an MLCC capacitor across the BOOT and PHASE pins. The boot capacitor is charged through an internal boot diode connected from the PVCC pin to the BOOT pin, each time the PHASE pin drops below PVCC minus the voltage dropped across the internal boot diode. UG (Pin 14) measures the VIN and VO pin voltages. The positive slope of VR can be written as: V RPOS = g m V IN – V OUT (EQ. 1) The negative slope of VR can be written as: V RNEG = g m V OUT (EQ. 2) Where gm is the gain of the transconductance amplifier. A window voltage VW is referenced with respect to the error amplifier output voltage VCOMP, creating an envelope into which the ripple voltage VR is compared. The amplitude of VW is set by a resistor connected across the FSET and GND pins. The VR, VCOMP, and VW signals feed into a window comparator in which VCOMP is the lower threshold voltage and VW is the higher threshold voltage. Figure 3 shows PWM pulses being generated as VR traverses the VW and VCOMP thresholds . The PWM switching frequency is proportional to the slew rates of the positive and negative slopes of VR; the PWM switching frequency is inversely proportional to the voltage between VW and VCOMP. The UG pin is the output of the high-side MOSFET gate driver. Connect to the gate of the high-side MOSFET. PHASE (Pin 15) Ripple Capacitor Voltage CR The PHASE pin detects the voltage polarity of the PHASE node and is also the current return path for the UG high-side MOSFET gate driver. Connect the PHASE pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor. Window Voltage VW Error Amplifier Voltage VCOMP PGOOD (Pin 16) The PGOOD pin is an open-drain output that indicates when the converter is able to supply regulated voltage. Connect the PGOOD pin to +5V through a pull-up resistor. PWM GND (Bottom Pad) Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin, not the PGND pin. FIGURE 3. MODULATOR WAVEFORMS DURING LOAD TRANSIENT EN, LDO, and POR Theory of Operation Modulator The ISL6269 is a hybrid of fixed frequency PWM control, and variable frequency hysteretic control. Intersil’s R3 technology can simultaneously affect the PWM switching frequency and PWM duty cycle in response to input voltage and output load transients. The term “Ripple” in the name “Robust-RippleRegulator” refers to the converter output inductor ripple current, not the converter output ripple voltage. The R3 modulator synthesizes an AC signal VR, which is an ideal representation of the output inductor ripple current. The duty-cycle of VR is the result of charge and discharge current through a ripple capacitor CR. The current through CR is provided by a transconductance amplifier gm that 7 The VCC LDO regulates by pulling up towards the voltage at the VIN pin; the LDO has no pull-down capability. The LDO is enabled when the EN pin surpasses the rising EN threshold voltage VENTHR. The ISL6269 is enabled once VVCC has increased above the rising power-on reset (POR) VVCC_THR threshold voltage. The controller immediately stops generating PWM and disables the LDO when the EN pin is pulled below the falling EN threshold voltage VENTHF . The IC completely shuts off when VVCC decreases below the falling POR VVCC_THF threshold voltage. Soft-Start, and PGOOD The ISL6269 uses a digital soft-start circuit to ramp the output voltage of the converter to the programmed regulation setpoint at a predictable slew rate. The slew rate of the soft-start sequence has been selected to limit the inrush current through the output capacitors as they charge to the FN9177.3 June 25, 2009 ISL6269 desired regulation voltage. When the EN pin is pulled above the rising EN threshold voltage VENTHR and VVCC has ramped above the rising POR VVCC_THR threshold voltage, the PGOOD Soft-Start Delay tSS starts and the output voltage begins to rise. The output voltage enters regulation in approximately 1.5ms and the PGOOD pin goes to high impedance once tSS has elapsed. 1.5ms VOUT VCC EN the opposite gate-driver output has fallen below approximately 1V. The dead-time shown in Figure 5 is extended by the additional period that the falling gate voltage stays above the 1V threshold. The high-side gate-driver output voltage is measured across the UG and PHASE pins while the low-side gate-driver output voltage is measured across the LG and PGND pins. The power for the LG gate-driver is sourced directly from the PVCC pin. The power for the UG gate-driver is sourced from a “boot” capacitor connected across the BOOT and PHASE pins. The boot capacitor is charged from a 5V bias supply through a “boot diode” each time the low-side MOSFET turns on, pulling the PHASE pin low. The ISL6269 has an integrated boot diode connected from the PVCC pin to the BOOT pin. tLGFUGR tUGFLGR 50% PGOOD UG 2.75ms FIGURE 4. SOFT-START SEQUENCE The PGOOD pin indicates when the converter is capable of supplying regulated voltage. The PGOOD pin is an undefined impedance if VVCC has not reached the rising POR threshold VVCC_THR, or if VVCC is below the falling POR threshold VVCC_THF. The ISL6269 features a unique faultidentification capability that can drastically reduce troubleshooting time and effort. The pull-down resistance of the PGOOD pin corresponds to the fault status of the controller. During soft-start or if an undervoltage fault occurs, the PGOOD pulldown resistance is 95, or 30 for an overcurrent fault, or 60 for an overvoltage fault. TABLE 1. PGOOD PULL-DOWN RESISTANCE CONDITION PGOOD RESISTANCE VCC Below POR Undefined Soft Start or Undervoltage 95 Overvoltage 60 Overcurrent 30 MOSFET Gate-Drive Outputs LG and UG The ISL6269 has internal gate-drivers for the high-side and low-side N-Channel MOSFETs. The LG gate-driver is optimized for low duty-cycle applications where the low-side MOSFET conduction losses are dominant, requiring a low rDS(ON) MOSFET. The LG pulldown resistance is small in order to clamp the gate of the MOSFET below the VGS(th) at turnoff. The current transient through the gate at turnoff can be considerable because the switching charge of a low rDS(ON) MOSFET can be large. Adaptive shoot-through protection prevents a gate-driver output from turning on until 8 LG 50% FIGURE 5. LG AND UG DEAD-TIME Diode Emulation The ISL6269 normally operates in continuous-conductionmode (CCM), minimizing conduction losses by forcing the low-side MOSFET to operate as a synchronous rectifier. An improvement in light-load efficiency is achieved by allowing the converter to operate in diode-emulation-mode (DEM), where the low-side MOSFET behaves as a smart-diode, forcing the device to block negative inductor current flow. The ISL6269 can be configured to operate in DEM by setting the FCCM pin low. Setting the FCCM pin high will disable DEM. Positive-going inductor current flows from either the source of the high-side MOSFET, or the drain of the low-side MOSFET. Negative-going inductor current usually flows into the drain of the low-side MOSFET. When the low-side MOSFET conducts positive inductor current, the phase voltage will be negative with respect to the GND and PGND pins. Conversely, when the low-side MOSFET conducts negative inductor current, the phase voltage will be positive with respect to the GND and PGND pins. Negative inductor current occurs when the output load current is less than ½ the inductor ripple current. Sinking negative inductor current through the low-side MOSFET lowers efficiency through unnecessary conduction losses. Efficiency can be further FN9177.3 June 25, 2009 ISL6269 improved with a reduction of unnecessary switching losses by reducing the PWM frequency. It is characteristic of the R3 architecture for the PWM frequency to decrease while in diode emulation. The extent of the frequency reduction is proportional to the reduction of load current. The ISL6269 features an audio filter that clamps the minimum PWM frequency to a level beyond human hearing when the output load current becomes low enough. With FCCM pulled low, the converter will automatically enter DEM after the PHASE pin has detected positive voltage, while the LG gate-driver pin is high, for eight consecutive PWM pulses. The converter will return to CCM on the following cycle after the PHASE pin detects negative voltage, indicating that the body diode of the low-side MOSFET is conducting positive inductor current. Overcurrent and Short-Circuit Protection The overcurrent protection (OCP) and short circuit protection (SCP) setpoint is programmed with resistor RSEN that is connected across the ISEN and PHASE pins. The PHASE pin is connected to the drain terminal of the low-side MOSFET. The SCP setpoint is internally set to twice the OCP setpoint. When an OCP or SCP fault is detected, the PGOOD pin will pulldown to 30and latch off the converter. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if VVCC has decayed below the falling POR threshold voltage VVCC_THF. The OCP circuit does not directly detect the DC load current leaving the converter. The OCP circuit detects the peak of positive-flowing output inductor current. The low-side MOSFET drain current ID is assumed to be equal to the positive output inductor current when the high-side MOSFET is off. The inductor current develops a negative voltage across the rDS(ON) of the low-side MOSFET that is measured shortly after the LG gate-driver output goes high. The ISEN pin sources the OCP sense current ISEN, through the OCP programming resistor RSEN, forcing the ISEN pin to zero volts with respect to the GND pin. The negative voltage across the PHASE and GND pins is nulled by the voltage dropped across RSEN as ISEN conducts through it. An OCP fault occurs if ISEN rises above the OCP threshold current IOC while attempting to null the negative voltage across the PHASE and GND pins. ISEN must exceed IOC on all the PWM pulses that occur within 20µs. If ISEN falls below IOC on a PWM pulse before 20µs has elapsed, the timer will be reset. An SCP fault will occur within 10µs when ISEN exceeds twice IOC. The relationship between ID and ISEN is written as: (EQ. 3) I SEN R SEN = I D r DS ON The value of RSEN is then written as: I PP I + -------- OC SP r DS ON FL 2 R SEN = ---------------------------------------------------------------------------I OC 9 Where: - RSEN () is the resistor used to program the overcurrent setpoint - ISEN is the current sense current that is sourced from the ISEN pin - IOC is the ISEN threshold current sourced from the ISEN pin that will activate the OCP circuit - IFL is the maximum continuous DC load current - IPP is the inductor peak-to-peak ripple current - OCSP is the desired overcurrent setpoint expressed as a multiplier relative to IFL Overvoltage Protection When an OVP fault is detected, the PGOOD pin will pull-down to 60and latch-off the converter. The OVP fault will remain latched until the VVCC has decayed below the falling POR threshold voltage VVCC_THF. The OVP fault detection circuit triggers after the voltage across the FB and GND pins has increased above the rising overvoltage threshold VOVR. Although the converter has latched-off in response to an OVP fault, the LG gate-driver output will retain the ability to toggle the low-side MOSFET on and off, in response to the output voltage transversing the VOVR and VOVF thresholds. Undervoltage Protection When a UVP fault is detected, the PGOOD pin will pull down to 95and latch-off the converter. The fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if VVCC has decayed below the falling POR threshold voltage VVCC_THF. The UVP fault detection circuit triggers after the voltage across the FB and GND pins has fallen below the undervoltage threshold VUV. Over-Temperature When the temperature of the ISL6269 increases above the rising threshold temperature TOTR, the IC will enter an OTP state that suspends the PWM , forcing the LG and UG gate-driver outputs low. The status of the PGOOD pin does not change nor does the converter latch-off. The PWM remains suspended until the IC temperature falls below the hysteresis temperature TOTHYS at which time normal PWM operation resumes. The OTP state can be reset if the EN pin is pulled below the falling EN threshold voltage VENTHF or if VVCC decays below the falling POR threshold voltage V VCC_THF. All other protection circuits function normally during OTP. It is likely that the IC will detect an UVP fault because in the absence of PWM, the output voltage immediately decays below the undervoltage threshold VUV; the PGOOD pin will pull-down to 95and latch-off the converter. The UVP fault will remain latched until the EN pin has been pulled below the falling EN threshold voltage VENTHF or if VVCC has decayed below the falling POR threshold voltage VVCC_THF. (EQ. 4) FN9177.3 June 25, 2009 ISL6269 Programming the Output Voltage When the converter is in regulation there will be 600mV from the FB pin to the GND pin. Connect a two-resistor voltage divider across the VO pin and the GND pin with the output node connected to the FB pin. Scale the voltage-divider network such that the FB pin is 600mV with respect to the GND pin when the converter is regulating at the desired output voltage. The output voltage can be programmed from 600mV to 3.3V. R2 C2 COMP + (EQ. 5) REF Where: FSET - VOUT is the desired output voltage of the converter - VREF is the voltage that the converter regulates to between the FB pin and the GND pin - RTOP is the voltage-programming resistor that connects from the FB pin to the VO pin. In addition to setting the output voltage, this resistor is part of the loop compensation network - RBOTTOM is the voltage-programming resistor that connects from the FB pin to the GND pin Beginning with RTOP between 1k to 5kcalculating RBOTTOM is written as: V REF R TOP R BOTTOM = ------------------------------------V OUT – V REF RFSET CFSET R3 MODULATOR VO VOUT VIN (EQ. 6) VIN QHIGH_SIDE UG Programming the PWM Switching Frequency The ISL6269 does not use a clock signal to produce PWM. The PWM switching frequency fSW is programmed by the resistor RFSET that is connected from the FSET pin to the GND pin. The approximate PWM switching frequency is written as: 1 f SW = --------------------------K R FSET PHASE LOUT 1 R FSET = -----------------K f SW DCR GATE DRIVERS QLOW_SIDE COUT LG (EQ. 7) Estimating the value of RFSET is written as: GND CESR ISL6269 (EQ. 8) Where: - R1 FB EA Programming the output voltage is written as: R BOTTOM V REF = V OUT -------------------------------------------------R TOP + R BOTTOM C1 fSW is the PWM switching frequency RFSET is the fSW programming resistor K = 75 x 10-12 It is recommended that whenever the control loop compensation network is modified, fSW should be checked for the correct frequency and if necessary, adjust RFSET. Compensation Design The LC output filter has a double pole at its resonant frequency that causes the phase to abruptly roll downward. The R3 modulator used in the ISL6269 makes the LC output filter resemble a first order system in which the closed loop stability can be achieved with a Type II compensation network. 10 FIGURE 6. COMPENSATION REFERENCE CIRCUIT Your local Intersil representative can provide a PC-based tool that can be used to calculate compensation network component values and help simulate the loop frequency response. The compensation network consists of the internal error amplifier of the ISL6269 and the external components R1, R2, C1, and C2 as well as the frequency setting components RFSET, and CFSET, are identified in the schematic Figure 6. General Application Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a single-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In FN9177.3 June 25, 2009 ISL6269 Selecting the LC Output Filter The duty cycle of an ideal buck converter is a function of the input and the output voltage. This relationship is written as: V OUT D = ---------------V IN (EQ. 9) The output inductor peak-to-peak ripple current is written as: V OUT 1 – D I PP = -------------------------------------f SW L OUT (EQ. 10) A typical step-down DC/DC converter will have an IPP of 20% to 40% of the maximum DC output load current. The value of IPP is selected based upon several criteria such as MOSFET switching loss, inductor core loss, and the resistive loss of the inductor winding. The DC copper loss of the inductor can be estimated by: P COPPER = I LOAD 2 (EQ. 11) DCR Where ILOAD is the converter output DC current. The copper loss can be significant so attention has to be given to the DCR selection. Another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. A saturated inductor could cause destruction of circuit components, as well as nuisance OCP faults. A DC/DC buck regulator must have output capacitance COUT into which ripple current IPP can flow. Current IPP develops a corresponding ripple voltage VPP across COUT, which is the sum of the voltage drop across the capacitor ESR and of the voltage change stemming from charge moved in and out of the capacitor. These two voltages are written as: V ESR = I PP E SR (EQ. 12) and I PP V C = ------------------------------------8 C OUT f (EQ. 13) SW If the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total ESR until the required VPP is achieved. The inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. Low inductance capacitors constructed with reverse package geometry are available. A capacitor dissipates heat as a function of RMS current and frequency. Be sure that IPP is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS current at fSW. Take into account that the rated value of a capacitor can fade as much as 50% as the DC voltage across it increases. 11 Selection of the Input Capacitor The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the RMS current required by the switching circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a preferred rating. Figure 7 is a graph of the input RMS ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter efficiency. The ripple current calculation is written as: 2 2 D 2 I MAX D – D + x I MAX ------ 12 I IN_RMS = ----------------------------------------------------------------------------------------------------I MAX (EQ. 14) Where: - IMAX is the maximum continuous ILOAD of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of IMAX (0% to 100%) - D is the duty cycle that is adjusted to take into account the efficiency of the converter which is written as: V OUT D = -------------------------V IN EFF (EQ. 15) In addition to the bulk capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain of the high-side MOSFET and the source of the low-side MOSFET. NORMALIZED INPUT RMS RIPPLE CURRENT addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts. 0.60 0.55 0.50 0.45 0.40 0.35 0.30 x=1 x = 0.75 x = 0.50 x = 0.25 x=0 0.25 0.20 0.15 0.10 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 DUTY CYCLE FIGURE 7. NORMALIZED RMS INPUT CURRENT FOR x = 0.8 FN9177.3 June 25, 2009 ISL6269 MOSFET Selection and Considerations Typically, a MOSFET cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. The MOSFETs used in the power stage of the converter should have a maximum VDS rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the MOSFET switches off. There are several power MOSFETs readily available that are optimized for DC/DC converter applications. The preferred high-side MOSFET emphasizes low switch charge so that the device spends the least amount of time dissipating power in the linear region. Unlike the low-side MOSFET which has the drain-source voltage clamped by its body diode during turn off, the high-side MOSFET turns off with VIN - VOUT - VLacross it. The preferred low-side MOSFET emphasizes low rDS(ON) when fully saturated to minimize conduction loss. As an example, suppose the high-side MOSFET has a total gate charge Qg, of 25nC at VGS = 5V, and a VBOOT of 200mV. The calculated bootstrap capacitance is 0.125µF; for a comfortable margin select a capacitor that is double the calculated capacitance, in this example 0.22µF will suffice. Use an X7R or X5R ceramic capacitor. Layout Considerations As a general rule, power should be on the bottom layer of the PCB and weak analog or logic signals are on the top layer of the PCB. The ground-plane layer should be adjacent to the top layer to provide shielding. The ground plane layer should have an island located under the IC, the compensation components, and the FSET components. The island should be connected to the rest of the ground plane layer at one point. VIAS TO GROUND PLANE For the low-side MOSFET, (LS), the power loss can be assumed to be conductive only and is written as: 2 P CON_LS I LOAD r DS ON _LS 1 – D (EQ. 16) For the high-side MOSFET, (HS), its conduction loss is written as: P CON_HS = I LOAD 2 r DS ON _HS D VOUT INDUCTOR HIGH-SIDE MOSFETS PHASE NODE VIN OUTPUT CAPACITORS SCHOTTKY DIODE LOW-SIDE MOSFETS INPUT CAPACITORS (EQ. 17) FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT For the high-side MOSFET, its switching loss is written as: V IN I VALLEY t ON f V IN I PEAK t OFF f SW SW P SW_HS = ----------------------------------------------------------------- + ------------------------------------------------------------2 2 (EQ. 18) Where: - IVALLEY is the difference of the DC component of the inductor current minus 1/2 of the inductor ripple current - IPEAK is the sum of the DC component of the inductor current plus 1/2 of the inductor ripple current - tON is the time required to drive the device into saturation - tOFF is the time required to drive the device into cut-off Selecting The Bootstrap Capacitor The selection of the bootstrap capacitor is written as: Qg C BOOT = -----------------------V BOOT GND (EQ. 19) Where: Signal Ground and Power Ground The bottom of the ISL6269 QFN package is the signal ground (GND) terminal for analog and logic signals of the IC. Connect the GND pad of the ISL6269 to the island of ground plane under the top layer using several vias, for a robust thermal and electrical conduction path. Connect the input capacitors, the output capacitors, and the source of the lower MOSFETs to the power ground plane. PGND (PIN 10) This is the return path for the pull-down of the LG low-side MOSFET gate driver. Ideally, PGND should be connected to the source of the low-side MOSFET with a low-resistance, low-inductance path. VIN (PIN 1) The VIN pin should be connected close to the drain of the high-side MOSFET, using a low resistance and low inductance path. VCC (PIN 2) - Qg is the total gate charge required to turn on the high-side MOSFET - VBOOT, is the maximum allowed voltage decay across the boot capacitor each time the high-side MOSFET is switched on 12 For best performance, place the decoupling capacitor very close to the VCC and GND pins. PVCC (PIN 12) For best performance, place the decoupling capacitor very close to the PVCC and PGND pins, preferably on the same side of the PCB as the ISL6269 IC. FN9177.3 June 25, 2009 ISL6269 FCCM (PIN 3), EN (PIN 4), AND PGOOD (PIN 16) LG (PIN 11) These are logic inputs that are referenced to the GND pin. Treat as a typical logic signal. The signal going through this trace is both high dv/dt and high di/dt, with high peak charging and discharging current. Route this trace in parallel with the trace from the PGND pin. These two traces should be short, wide, and away from other traces. There should be no other weak signal traces in proximity with these traces on any layer. COMP (PIN 5), FB (PIN 6), AND VO (PIN 8) For best results, use an isolated sense line from the output load to the VO pin. The input impedance of the FB pin is high, so place the voltage programming and loop compensation components close to the VO, FB, and GND pins keeping the high impedance trace short. FSET (PIN 7) This pin requires a quiet environment. The resistor RFSET and capacitor CFSET should be placed directly adjacent to this pin. Keep fast moving nodes away from this pin. BOOT (PIN 13), UG (PIN 14), AND PHASE (PIN 15) The signals going through these traces are both high dv/dt and high di/dt, with high peak charging and discharging current. Route the UG and PHASE pins in parallel with short and wide traces. There should be no other weak signal traces in proximity with these traces on any layer. Copper Size for the Phase Node ISEN (PIN 9) Route the connection to the ISEN pin away from the traces and components connected to the FB pin, COMP pin, and FSET pin. The parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. It is best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application. An MLCC should be connected directly across the drain of the upper MOSFET and the source of the lower MOSFET to suppress the turn-off voltage spike. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN9177.3 June 25, 2009 ISL6269 Package Outline Drawing L16.4x4 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 6, 02/08 4X 1.95 4.00 12X 0.65 A B 13 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 16 1 4.00 12 2 . 10 ± 0 . 15 9 4 0.15 (4X) 5 8 TOP VIEW 0.10 M C A B +0.15 16X 0 . 60 -0.10 4 0.28 +0.07 / -0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 1.00 MAX ( 3 . 6 TYP ) ( SEATING PLANE 0.08 C SIDE VIEW 2 . 10 ) C BASE PLANE ( 12X 0 . 65 ) ( 16X 0 . 28 ) C 0 . 2 REF 5 ( 16 X 0 . 8 ) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 14 FN9177.3 June 25, 2009