Technical Brief 497 Author: Doug Mattingly Disabling the North Bridge Regulator on the ISL62771 The ISL62771 is a feature rich power supply controller targeted for AMD SVI2 compliant processors that is capable of controlling two independent rails. One of the rails, referred to as the Core regulator, can be configured as either a two-phase regulator or a single-phase regulator. The second rail is a single phase regulator and is referred to as the North Bridge regulator. running. This technical brief describes the method that can be used to effectively disable the North Bridge regulator so that the ISL62771 is controlling a single output. Figure 1 shows how to configure the ISL62771 with the North Bridge regulator disabled and the Core regulator configured as a two-phase system. Figure 2 shows how to configure the ISL62771 with the North Bridge regulator disabled and the Core regulator configured as a single-phase system. Many applications require a single AMD SVI2 compliant power supply that utilizes only one or two phases. The ISL62771 can support these requirements but it lacks an option for disabling the North Bridge regulator so that only the Core regulator is BOOT_NB UGATE_NB VDD +5V IMON_NB NTC_NB PHASE_NB LGATE_NB 10kΩ VSEN_NB ISUMN_NB 10kΩ 100kΩ 100kΩ FB_NB ISUMP_NB 10kΩ (OPTIONAL TO SET FSW = 400kHz) COMP_NB PWROK VDDP VDDP SVT SVD µP ISL62771 SVC IMON VDDIO NTC VR_HOT_L ENABLE PGOOD_NB PGOOD VCORE_GND RTN VCORE VIN BOOT2 VSEN UGATE2 FB PHASE2 LGATE2 PH2 VO2 VCORE COMP VIN BOOT1 UGATE1 PHASE1 PH1 ISEN1 PH2 ISEN2 LGATE1 PH1 VO1 Ri VO1 VO2 ISUMN Cn NTC PH1 GNDPAD ISUMP PH2 FIGURE 1. TWO-PHASE CORE REGULATOR WITH NORTH BRIDGE DISABLED February 19, 2014 TB497.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Technical Brief 497 VDD +5V BOOT_NB UGATE_NB IMON_NB NTC_NB PHASE_NB LGATE_NB 10kΩ VSEN_NB ISUMN_NB 10kΩ 100kΩ 100kΩ FB_NB ISUMP_NB 10kΩ (OPTIONAL TO SET FSW = 400kHz) COMP_NB PWROK VDDP VDDP SVT SVD µP ISL62771 SVC VDDIO VR_HOT_L ENABLE PGOOD_NB PGOOD VCORE_GND RTN IMON NTC BOOT2 UGATE2 PHASE2 LGATE2 VSEN VCORE VIN BOOT1 FB UGATE1 VCORE PHASE1 COMP LGATE1 ISEN2 VO1 ISUMN NTC PH1 VO1 +5V ISEN1 Ri Cn PH1 GNDPAD 10kΩ ISUMP FIGURE 2. SINGLE-PHASE CORE REGULATOR WITH NORTH BRIDGE DISABLED The Core regulator is configured as either a one- or two-phase system per the instructions given in the ISL62771 datasheet. Whether the Core regulator is configured as a one- or two-phase system, the North Bridge regulator is disabled in the same manner: 1. Short the following pins together: COMP_NB (pin 36), FB_NB (pin 37), and VSEN_NB (pin 38). 2. Short the following pins together: ISUMN_NB (pin 39) and ISUMP_NB (pin 40). 3. Tie pin IMON_NB (pin 2) to ground through a 100kΩ resistor. 4. Tie pin NTC_NB (pin 1) to ground through a 100kΩ resistor. 5. Tie pin BOOT_NB (pin 31) to pin VDD (pin 25). 6. Tie pin PHASE_NB (pin 33) to pin UGATE_NB (pin 32). 7. Tie pin LGATE_NB (pin 34) to ground through a 10kΩ resistor. Programming an offset on the Core regulator is accomplished through the prescribed method in the ISL62771 datasheet. Behavior of the ISL62771 With the ISL62771 configured as described in this technical brief, the internal circuitry for the North Bridge regulator is not powered down nor is it disabled. All feedback, control, protection, and gate driver circuits are active. Due to this, there is a minor bias current draw for this active circuitry. The shorting of the COMP_NB and FB_NB pins places a unity gain on the North Bridge amplifier. This will force the North Bridge DAC voltage on both of these pins after soft-start. Shorting the VSEN_NB pin to COMP_NB and FB_NB insures that there will be no over or undervoltage events that could shut the regulators down. 8. Tie pin UGATE_NB (pin 32) to ground through a 10kΩ resistor. 9. Pin PGOOD_NB (pin 35) can be left floating. These instructions will yield a system with a switching frequency of 300kHz. In order to obtain a 400kHz switching frequency, the COMP_NB pin should be tied to ground through a 10kΩ resistor. 2 TB497.0 February 19, 2014 Technical Brief 497 COMP_NB / FB_NB / VSEN_NB COMP_NB / FB_NB / VSEN_NB UGATE_NB LGATE_NB VCORE FIGURE 3. STARTUP WITH NORTH BRIDGE DISABLED FIGURE 4. NORTH BRIDGE GATE SIGNALS Figure 3 shows how the VSEN_NB, COMP_NB, and FB_NB pins will act during startup. Following startup, these pins will remain at whatever the MetalVID voltage is, unless an SVID command is sent to change the North Bridge DAC value. If an SVI command is sent to the ISL62771 that commands the North Bridge DAC to a particular VID level, the COMP_NB, FB_NB, and VSEN_NB pins will ramp to that new VID level, tracking the DAC as it ramps. If an SVI command is never sent to the North Bridge regulator, then the COMP_NB, FB_NB, and VSEN_NB voltages will remain at the MetalVID voltage that was prescribed by the initial SVC and SVD voltages at startup. Shorting the ISUMP_NB and ISUMN_NB pins together will force the current sensing amplifiers to measure a zero load current. As such, there can be no shutdowns due to a sensed overcurrent by the North Bridge circuitry. COMP_NB / FB_NB / VSEN_NB LGATE_NB UGATE_NB Both the IMON_NB and NTC_NB pins are tied to ground through a 100kΩ resistor. These resistors will insure that there will be no overcurrent or thermal shutdown initiated by the North Bridge control circuitry. The gate drivers for the North Bridge regulator remain active in this configuration. For this reason, the BOOT_NB pin is tied to VDD so that the upper gate driver retains a bias. The 10kΩ resistors on the UGATE_NB and LGATE_NB pins allow for a minimal amount of current to flow through the drivers when turned on. The PHASE_NB pin is tied to the UGATE_NB pin to simulate the switching of the PHASE node. FIGURE 5. NORTH BRIDGE GATE SIGNALS SHOWING DUTY CYCLE References For Intersil documents available on the web, see www.intersil.com [1] ISL62771 Datasheet Figure 4 shows what the upper and lower gate signals will look like for the North Bridge regulator in this configuration. Figure 5 shows a number of switching cycles. If an SVI command is sent to the North Bridge regulator and the DAC is changed, the duty cycle of the gate signals will likely change. If the North Bridge DAC is commanded to a low enough voltage, the COMP_NB signal can fall below the oscillator and switching could halt entirely. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 TB497.0 February 19, 2014