tb486

Technical Brief 486
ISL6334EVAL1Z User Guide
Board Specifications
1. Intel VR11.1 compliant.
2. 4-Phase, 130W, 400kHz, Load Line = 0.8mΩ.
3. Socket: LGA1366, die sensing, can be configured for
motherboard sensing.
4. 6 Layer Board: Top/Bottom - 0.5oz plated, 1.5oz
finished; Internal Layer – 1oz.
5. Dual footprint for Intersil 12V (ISL6612A, ISL6622)
and 5V drivers (ISL6596/ISL6620) for cost or
efficiency optimization. With minor re-work, the
board can also operate 12V drive for high-side
MOSFET and 5V drive for low-side MOSFET.
6. Dual footprint for PowerPak and DPAK MOSFET for
cost or efficiency optimization.
ISL6334EVAL1Z Board Brief
Description
FIGURE 3.
VR Enable Switch
One switch (SW2) is provided for EN_VTT signal control.
In “OFF” position, EN_VTT signal is shorted to ground
and ISL6334 is disabled. Place SW2 in the “ON” position
to enable operation.
Control Power Supply
There are two ways to provide 5VDC to this evaluation
board: through ATX power connectors (J21) or Banana
connectors (J5 and J0). SW1 is used to control the ATX
silver box power supply.
FIGURE 4.
PGOOD Indicator and Test Points
CR2 is used to indicate the status of VR_RDY (PGOOD)
signal. When VR_RDY is high, the LED in CR2 will be OFF
(no light); otherwise the red LED in CR2 will be on once
5V is applied.
FIGURE 1.
Input Power Supply and External Load
Connector
Test points are provided for VR_RDY, IMON, VR_HOT and
VR_FAN signals.
12VDC input power supply can be connected to the
board through the 4-pin ATX connector J4. Two test
points, TPVIN and TPGND, are provided for input voltage
measurement. Two connectors (J1 and J2) are provided
for external load.
FIGURE 5.
FIGURE 2.
July 7, 2010
TB486.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Technical Brief 486
VID (Figure 7)
Phase Count Control
VID code can be generated from Demo board
(JP9 = DEMO) or VTT tool (JP9 = VTT).
R1P, R2P, R3P, RW2, RW3, and RW4 are used to set the
phase count, as shown in Table 1. If phase count is
different than 4, R1 and R5 must be adjusted accordingly
for stability and correct load line.
PSI
Dynamic PSI signal can be generated from LGA1366 VTT
or external function generator. Static, fixed PSI operation
can be set through SW5. Placing the 0 switch in the “N”
position, leads to the circuit operating in PSI mode.
TABLE 1.
R3P
R2P
R1P
RW4
RW3
RW2
4-Phase
DNP
DNP
DNP
0Ω
0Ω
0Ω
3-Phase
0Ω
DNP
DNP
DNP
0Ω
0Ω
2-Phase
X
0Ω
DNP
DNP
DNP
0Ω
1-Phase
X
X
0Ω
DNP
DNP
DNP
NOTE: X = Don’t care.
Available Design Assist Tools
FIGURE 6.
1
Layout Check list.
2
VR Design Worksheet.
3
VCORE and IMON TOB Calculator.
4
Schematic is available in OrCAD format.
5
Layout is available in Allegro format.
Contact Intersil’s local office or field support for the latest
available information.
FIGURE 7.
2
July 7, 2010
TB486.0
ISL6334EVAL1Z Schematics
5
4
3
2
1
VCC5
Controller circuit
VCC5
R9
DNP
VCC5
U1
19
R10
2k
CVC
0.1u
D
3
SET R5+R1=R334;
Average OC=100uA
CR2
VR_RDY GREEN
RGND
VSEN
VR_RDY
Csen
C3
390pF
237
PSI#
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI#
Q24
2N7002
R88
0
TP29
TP7
VR_RDY
RED
IMON OC Trip = 1.12V
R5
VCC12
Vc5
R8
2.2
0
ISL6334
VCC
40
1
2
3
4
5
6
7
8
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI#
36
VR_RDY
16
17
EN_PWR
32
EN_VTT
33
249
1k
RGND
VSEN
VDIFF
14
FB
13
COMP/FB
R2
C1
C2
Vc5
CF1
470n
CT2
120p
RMOFS
IMON
ROFS
RFS1
100k
49.9k
TP6
38
TM
39
TCOMP
18
ISEN3-
DNP
R2P
Expose these traces
on external layers
DNP
C
PWM4
R3P
RW4
DNP
DNP
CW4
RP4
1.82k
ISEN4DNP
CC40
0.15u
Vc5
RN2
6.8k
RSI3
0
49.9k
R24
1k
R27
DNS
VCORE
0
CF3
470n
RT3
CW3
RCI3
DNP
R17
RCI4
VCORE4
R28
20k
C66
0.1u
CT4
120p
221
~27ns RC Time
Constant
VCORE
0
CF4
470n
RT4
RSS1
10.2k
R345
RP3
DNP
DNP
VCORE3
CT3
120p
ISENSE
B
RSI2
1.82k
CC30
0.15u
221
VR_HOT
GND
62k
VCORE
0
0
37
VR_HOT
41
26.1k
DNP RCI2
VCORE2
CF2
470n
RT2
CW2
PWM3
SS
DNP
RSI1
DNP
ISEN2-
CC20
0.15u
R11
901k
RP2
1.82k
DNP
221
TP5
VR_FAN
FS
VCORE
0
RW2
R1P
25
24
23
PWM4
ISEN4ISEN4+
RFS2
TP15
D
VCORE1
RW3
OFS
35
RT1
RCI1
0
31
30
29
VR_FAN
34
RSS2
CC10
0.15u
DNP
PWM2
IMON
9
DNP
20
21
22
PWM3
ISEN3ISEN3+
DAC
10
150pF
PWM2
ISEN2ISEN2+
CT1
120p
R344
12.1k
12pF
26
27
28
REF
11
1.30k
C5
1n
ISEN1-
RSI4
Placement needs correction
R2P and R3P and their traces should not be
close to any current sensing network.
B
33nF
RMON
C14
C15
Number of Operating Phases Configuration
Phase Dropping Decoding
0
RSS1
RSS2
RFS1
R3P
R2P
4-PHASE
DNP
DNP
3-PHASE
0 Ohm
RFS2
R1P
RW4
RW3
RW2
ISENSE_DN
R91
VSS_SENSE_DIE
DNP
R90
Place this close to the socket
SI - 1P
TO GND
DNP
TO GND
DNP
SI - 2P
DNP
TO Vc5
TO GND
DNP
CI - 1P
CI - 2P
TO GND
DNP
DNP
DNP
TO Vc5
DNP
2-PHASE
X
1-PHASE
X
DNP
0 Ohm 0 Ohm
0 Ohm
DNP
DNP
DNP
0 Ohm
0 Ohm
0 Ohm
DNP
DNP
DNP
0 Ohm
0 Ohm
DNP
DNP
DNP
TO Vc5
X
TO Vc5
X = DON'T CARE
RN2 = Vishay, NTHS0805N02N6801
A
Droop (R1+R5) and compensation network must be adjusted accordingly.
SI = Un-couppled Inductor
CI = Couppled Inductor
A
Intersil Corporation
65 Readington Road
Somerville, NJ 08876
Intersil Confidential
Size
B
Date:
July 7, 2010
TB486.0
5
4
3
2
FIGURE 8. ISL6334 BURNSIDE - 130W REV C BOARD, CONTROLLER CIRCUIT
Title
ISL6334 Burnside - 130W Rev C Board
Thursday, December 20, 2007
Sheet
1
1
of
3
Rev
C
Technical Brief 486
R1
PWM1
ISEN1ISEN1+
CI or SI
connection
RP1
1.82k
Vc5
R3
C
CW1
221
15
12
PWM1
DNP
R7
9.31k
DNP
R346
R6
100k
EN_VTT
ISL6334EVAL1Z Schematics
5
(Continued)
4
3
2
1
Follow Intel Burside ATX Layout Guideline for Power Stage and LGA1366 Socket as
well as Input Bus Line (1080 pre-preg stackup, 6 layers)
Power Stage
Dual footprint for SI and CI - Expose Output Inductor Copper
VCC12
Dual footprint - LFPAK/DPAK for High-side (T/B) and Low-Side (B/T)
VCC5
CI: Phase1 (Thermistor) + Phase3 ; Phase2 + Phase4
Default - 12VUG, LDO=LG. Hardware Options: 12VUG5VLG; LDO=UGLG; 5V DRIVER
D
RV5
D
DNP
4
1u
7
LVCC/VCC
4
PWM
RGV1 3
DNP
GDV/NC
2
1
PHASE
10
LGATE
6
EP
2
UG1
UG1
CC3
LG1
QLT11
1
11
1
QLT12
LVCC/VCC
PHASE
10
4
PWM
LGATE
6
3
GDV/NC
EP
RPS1
2SEPC330MW
160nH
0
ISEN1-
R46
2.2
CO35
330u
Need new footprint and use
bigger hole for T-core; Expose
output copper for Coupled
Inductors
UG3
UG3
QUB3
C24
4.7u
C70
4.7u
C46
4.7u
CO1
22u
PHASE3
LG3
LG3
QLT31
11
1
C32
DNP
L3
QLT32
1
RPS3
VCC/PVCC
8
7
0.1u
BOOT
2
UVCC/NC
UGATE
1
LVCC/VCC
PHASE
10
CB2
RPH2 0
UG2
UG2
QUB2
C23
4.7u
C68
4.7u
C64
4.7u
GDV/NC
LGATE
EP
LG2
6
CO7
22u
CO8
22u
CO9
22u
CO18
22u
CO11
22u
CO12
22u
CO13
22u
CO14
22u
CO15
22u
CO16
22u
CO17
22u
CO20
DNP
CO21
22u
CO22
22u
CO23
22u
CO24
22u
CO25
22u
CO26
22u
B
L2
QLT21
1
3
1
Rail4
CO19
DNP
PHASE2
LG2
11
C31
DNP
2
PWM
3
CO6
22u
Rail2
160nH
RPS2
QLT22
3
4
CO5
22u
C27
680uF
PHASE2
2
RGV2
DNP
GND/4
PWM2
CO4
22u
ISEN3-
CO10
DNP
1
5
CL2
1u
CO3
22u
0
R47
2.2
3
B
9
CO2
22u
2
RDU2
0
RDL2
0
ISEN2-
CO28
DNP
Rail5
1u
UVCC/NC
UGATE
LVCC/VCC
PHASE
10
4
PWM
LGATE
6
3
GDV/NC
7
0.1u
0
CB4
UG4
UG4
1
PHASE4
RGV4
DNP
EP
11
C76
4.7u
C79
4.7u
C78
4.7u
TP10
GND
C33
DNP
CO42
DNP
CO43
DNP
CO44
22u
CO45
DNP
CO46
DNP
2
LG4
QLT41
1
1
C75
DNP
QLT42
L4
RPS4
R73
2.2
5
4
J2
GND
TP100
GND
TP50
GND
Place these hoods on different
positions for scope probe ground
A
Intersil Corporation
160nH
0
65 Readington Road
Somerville, NJ 08876
ISEN4Size
B
Intersil Confidential
5
CO41
DNP
PHASE4
LG4
3
CL4
1u
PWM4
GND
A
QUB4
3
2
1
VCC/PVCC
2
RPH4
BOOT
8
2
9
CO40
22u
J1
V_CORE
1
Rail4
1
3
RDU4
0
RDL4
0
CO39
22u
Rail4
VCC12
UD4 ISL6622CR/12CR
R4V12 10
CO27
DNP
0
R71
2.2
Rail3
CC4
CO47
330u
160nH
1u
UD2 ISL6622CR/12CR
10
CO38
330u
C28
680uF
VCC12
R2V12
CO37
330u
C
Rail1
CC2
CO36
330u
3
1
PHASE3
2
7
RPH3 0
2
2
1
CO34
DNP
2
0.1u CB3
BOOT
UGATE
CO33
330u
C26
DNP
L1
3
RGV3
DNP
UVCC/NC
3
PWM3
VCC/PVCC
8
5
CL3
1u
9
GND/4
RDU3
0
RDL3
0
C44
4.7u
CO32
330u
C30
DNP
1u
UD3 ISL6622CR/12CR
10
C67
4.7u
CO31
330u
PHASE1
LG1
VCC12
R3V12
C22
4.7u
CO30
330u
3
2
July 7, 2010
TB486.0
FIGURE 9. ISL6334 BURNSIDE - 130W REV C BOARD, POWER STAGE
Date:
Title
ISL6334 Burnside - 130W Rev C Board
Sheet
Wednesday, December 05, 2007
1
2
of
3
Rev
C
Technical Brief 486
C
QUB1
1
PHASE1
3
BOOT
UGATE
2
UVCC/NC
CO29
DNP
3
PWM1
VCC/PVCC
8
5
CL1
1u
9
RPH1 0
3
RDU1
0
RDL1
DNP
GND/4
R1V12 10
VCORE
VCC12
0.1u CB1
2
CC1
UD1 ISL6622CR/12CR
ISL6334EVAL1Z Schematics
5
(Continued)
4
2
VCC5
Increase Resistor Value to
improve LL efficiency.
VCC5
R74
10k
Per Intel Request,
but not needed
QUT3
5
1
2
3
4
1
2
3
4
PHASE1
UG1
PHASE1
5
R59
DNP
QUT4
C34
DNP
1
2
3
4
1
2
3
4
QUT2
PHASE2
UG2
UG2
UG4
PHASE4
C38
DNP
R64
DNP
R65
DNP
C39
DNP
R66
DNP
C40
DNP
VID Code
C41
DNP
VCC5
LG3
LG1
RD2
10k
RD3
10k
RD4
10k
RD5
10k
RD6
10k
RD7
10k
D
VID0
8
VID1
13
2
9
12
19
NC1 COM1
NC2
NC3 COM2
NC4
COM3
NO1
NO2 COM4
NO3
NO4 VCC
VID2
1
10
11
20
EN1
EN2
EN3
EN4
15
18
VID3
16
nc
VCC5
TP20
VID0 TP21
VID1 TP22
VID2 TP23
VID3
C107
0.1u
5
6
VEE
GND
U7
ISL43240
1
2
3
4
QLB32
LG3
LG1
SW3
SW DIP-8
C37
DNP
RD1
10k
3
LG4
R63
DNP
QLB31
1
2
3
4
1
2
3
4
QLB12
C36
DNP
C35
DNP
VTT_VID4
VTT_VID5
VTT_VID6
VTT_VID7
5
PHASE3
5
5
5
1
2
3
4
QLB11
R62
DNP
4
7
14
17
4
7
14
17
3
VID4
8
VID5
13
2
9
12
19
NC1 COM1
NC2
NC3 COM2
NC4
COM3
NO1
NO2 COM4
NO3
NO4 VCC
VID6
18
VID7
1
10
11
20
EN1
EN2
EN3
EN4
15
16
nc
VCC5
TP24
VID4 TP25
VID5 TP26
VID6 TP27
VID7
C108
0.1u
5
6
VEE
GND
4
LG4
J5
C106
10n
NEED BNC FOOTPRINT
PSI
R101
VCC5
PSI#
0
U100
AB35
EN_VTT
DNS
DEMO
ONLY 1 "ON"
code allowed
AL10
VTT_VID1
AL9
AR9
TPGND
J0
AN9
VTT_VID3
AM10
AR8
VTT_VID4
AN10
VCC
VTT_VID5
AP9
VTT_VID6
AP8
VTT_VID7
AN8
AR18
ISENSE
AK8
AR17
ISENSE_DN
AK7
9
+5VSB
10
11
+12V1A
+12V1B
VCC12
J4
2x2 Power Connector
GND
+12V 3
Vin_GND
TPVIN
Vin
2
GND0
12V
4
B
8
NC
20
PS_ON#
-12V
16
14
SW1
3
1
RDIEP
VSEN
LGA1366_SOCKET
0 RDIEN
VSS_SENSE_DIE
RGND
VCORE
TP8
VSEN
VSS
RLCP 100
C12
DNS
RLCN 100
A
Use Intersil/VTT Interposer
for DCLL Measurement
TP9
Intersil Corporation
RGND
65 Readington Road
Somerville, NJ 08876
Add via on AR18 and
AR17 for test points
Size
B
Intersil Confidential
5
1
VSS_SENSE_DIE
VTT_VID2
A
VR_RDY
0
VCC_SENSE_DIE
PWR_OK
R99
AR7
AP7
VTT_VID0
C99
10u
R100
DNS
+5V
+5VA
+5VB
+5VC
+5VD
3
5
7
15
17
18
19
24
2
VTTPWRGOOD
4
6
21
22
23
GND
GND0
GND1
GND2
GND3
GND4
GND5
GND6
25
R79
100k
SW5
SW DIP-4
0
1
BNC
VTT
TP68
+3.3V
+3.3VA
+3.3VB
+3.3VC
5
EN_VTT
6
2
1
2
12
13
4
6
VCC5
B
J21
ATX 24-Pin Connector
SW2 TP28
ENABLE
25
1
5
LG4
LG2
QLB42
3
LG2
QLB41
1
2
3
4
QLB22
1
2
3
4
1
2
3
4
QLB21
PHASE4
1
2
3
4
PHASE4
5
5
PHASE2
5
R78
10k
PHASE2
C
4
3
July 7, 2010
TB486.0
FIGURE 10. ISL6334 BURNSIDE - 130W REV C BOARD
2
Date:
Title
ISL6334 Burnside - 130W Rev C Board
Tuesday, January 08, 2008
Sheet
1
3
of
3
Rev
C
Technical Brief 486
PHASE3
R61
DNP
R60
DNP
LG3
C
PHASE1
VTT_VID0
VTT_VID1
VTT_VID2
VTT_VID3
JP9
UG4
Place These FETs on Bottom Side for
Intel Burnside CRB Design (Depending
Upon the Layout, we might drop this)
PHASE1
VTT
UG3
VCC12
5
VCC12
PHASE2
LG1
UG3
UG1 PHASE3
RD0
10k
U6
ISL43240
DEMO
LG2
5
5
QUT1
D
1
VCC12
5
VCC12
3
VID generator, LGA1366 socket and input connectors
Place These FETs on Top Side
for Intel Burnside CRB Design
ISL6334EVAL1Z Schematics
4
3
2
1
AB35
AL9
AL10
AM10
5
(Continued)
VSS
BA35 VSS
BA36
BA37
BA38
BA39 VSS
BA40
VSS
VSS
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VR_READY
VSS_SENSE
VCC_SENSE
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS_NORTH
VCC_NORTH
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
AC33
AC34
AC35
AC36
AC37
AC38
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
A35
A36
A37
A38
A39
A40
A41
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF43
AF42
AF41
AF40
AF39
AF38
AF37
AF36
AF35
AF34
AF33
VSS
VSS
VSS
VSS
VSS
PROCHOT#
VSS
VSS
MN8
VCC
VCC
VSS
VSS
VSS
VSS
MN7
VSS
VSS
AE33
AE34
AE35
AE36
AE37
AE38
AE39
AE40
AE41
AE42
AE43
MN5
VSS
MN4
VSS
VSS
A24
A25
A26
A27
A28
A29
A30
A31
MN3
VSS
A4
A5
A6
A7
A8
A9
A10
A14
A15
A16
A17
A18
A19
A20
MN2
VSS
AD33
AD34
AD35
AD36
AD37
AD38
AD39
AD40
AD41
AD42
AD43
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
MN1
VSS
MN6
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
VSS
VSS
VSS
AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AB41
AB42
AB43
VSS
VTTPWRGOOD
VSS
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
VSS
VSS
AA33
AA34
AA35
AA36
AA37
AA38
AA39
AA40
AA41
VSS
VSS
VSS
VSS
D
VSS
VSS
C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AY42
AY41
AY40
AY39
AY38
AY37
AY36
AY35
AY34
AY33
AY32
AY31
AY30
AY29
AY28
AY27
AY26
AY25
AY24
AY23
AY22
AR7
AR8
AR9
AR17
AR18
AY19
AY20
AY21
AY2
AY3
AY4
AY5
AY6
AY7
AY8
AY9
AY10
AY11
AY12
AY13
AY14
AY15
AY16
AY17
AY18
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VSS
AP7
AP8
AP9
VSS
B2 VSS
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37 VSS
B38
B39
B40
B41
B42 VSS
AR1
AR2
AR3
AR4
AR5
AR6
AR7
AR8
AR9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR39
AR40
AR41
AR42
AR43
VCC
VCC
VSS
VCC
VCC
VSS
VCC
AW36
AW35
AW34
AW33
AW32
AW31
AW30
AW29
AW28
AW27
AW26
AW25
AW24
AW23
AW22
AW21
AW20
AW19
AW18
AW17
AW16
AW15
AW14
AW13
AW12
AW11
AW10
AW9
AW8
AW7
AW6
AW5
AW4
AW3
AW2
AW1
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
BA24
BA25
BA26
BA27
BA28
BA29
BA30
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VSS
VCC
VCC
VSS
VCC
1366LGA_6 VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AJ7
AJ8
AJ9
AJ10
AJ11
AJ33
AJ34
AJ35
AJ36
AJ37
AJ38
AJ39
AJ40
AJ41
AJ42
AJ43
U100-7
AC39
AC40
AC41
AC42
AC43
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
VSS
VSS
VSS
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
VSS
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
VSS
VSS
VSS
VSS
U100-6
1366LGA_6
VSS
VSS
VSS
VSS
VSS
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
VSS
VSS
VSS
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
E41
E42
E43
VSS
VSS
B
VSS
VSS
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
G41
G42
G43
D43
D42
D41
D40
D39
D38
D37
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
VSS
VSS
VSS
VSS
VSS
VSS
A
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
J41
J42
J43
VSS
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
VSS
J1
J2
J3 VSS
J4
J5
J6
J7
J8 VSS
J9
J10
J11
J12
J13 VSS
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
VSS
VSS
VSS
VSS
F38
F39
F40
F41
F42
F43
H43
H42
H41
H40
H39
H38
H37
H36
H35
H34
H33
H32
H31
H30
H29
H28
H27
H26
H25
H24
H23
H22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
VSS
VSS
VCC
VCC
VSS
VSS
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
VCC
VCC
VSS
VSS
VSS
VSS
VSS
U33
U34
U35
U36
U37
U38
U39
U40
U41
U42
U43
VCC
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
VCC N33
N34
VSS N35
N36
N37
N38
N39
VSS N40
N41
N42
N43
N1
N2
N3
N4
VSS N5
N6
N7
N8
N9
VSS N10
VCC N11
VSS P33
P34
P35
P36
P37
VSS P38
P39
P40
P41
P42
VSS P43
VCC
VSS
A
VSS
VSS
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T33
T34
T35
T36
T37
T38
T39
T40
T41
T42
T43
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V33
V34
V35
V36
V37
V38
V39
V40
V41
V42
V43
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32
L33
L34
L35
L36
L37
L38
L39
L40
L41
L42
L43
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W33
W34
W35
W36
W37
W38
W39
W40
W41
W42
W43
1366LGA_6
K43
K42
K41
K40
K39
K38
K37
K36
K35
K34
K33
K32
K31
K30
K29
K28
K27
K26
K25
K24
K23
K22
K21
K20
K19
K18
K17
K16
K15
K14
K13
K12
K11
K10
K9
K8
K7
K6
K5
K4
K3
K2
K1
VSS M24
VCC M25
VSS M26
M27
VSS M28
VCC M29
VSS M30
VCC M31
VSS M32
VCC M33
M34
M35
M36
VSS M37
M38
M39
M40
M41
VSS M42
M43
VSS
B
VSS
U100-4
1366LGA_6
Y1 VSS
Y2
Y3
Y4
Y5
Y6
VSS
Y7
Y8
Y9
Y10
Y11 VSS
Y33 VSS
Y34
Y35
Y36 VSS
Y37
Y38
Y39
Y40
Y41 VSS
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
U100-5
VSS
VSS
Intersil Corporation
July 7, 2010
TB486.0
Size
Custom
Date:
5
4
3
FIGURE 11. LGA1366 SOCKET PINOUT
2
1
Title
Rev
A
LGA1366 SOCKET PIN OUT
Tuesday, January 08, 2008
Sheet
5
of
5
Technical Brief 486
C
VSS
AT1
AT2
AT3
AT4
AT5
AT6
AT7
AT8
AT9
AT10
AT11
AT12
AT13
AT14
AT15
AT16
AT17
AT18
AT19
AT20
AT21
AT22
AT23
AT24
AT25
AT26
AT27
AT28
AT29
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AT40
AT41
AT42
AT43
VCC
VSS
AW42
AW41
AW40
AW39
AW38
AW37
U100-1
BA3
BA4
BA5
BA6
BA7
BA8
BA9
BA10
BA11
BA12
BA13
BA14
BA15
BA16
BA17
BA18
BA19
BA20
VSS
VSS
PSI #
VID6
VID5
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
AP1
AP2
AP3
AP4
AP5
AP6
AP7
AP8
AP9
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AP39
AP40
AP41
AP42
AP43
1366LGA_6
VSS
VSS
VSS
VSS
ISENSE_DN
ISENSE
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
AG1
AG2
AG3
AG4
AG5
AG6
AG7
AG8
AG9
AG10
AG11
AG33
AG34
AG35
AG36
AG37
AG38
AG39
AG40
AG41
AG42
AG43
VSS
VSS
VSS
AU1
AU2
AU3
AU4
AU5
AU6
AU7
AU8
AU9
AU10
AU11
AU12
AU13
AU14
AU15
AU16
AU17
AU18
AU19
AU20
AU21
AU22
AU23
AU24
AU25
AU26
AU27
AU28
AU29
AU30
AU31
AU32
AU33
AU34
AU35
AU36
AU37
AU38
AU39
AU40
AU41
AU42
AU43
VCC
VSS
VSS
VSS
AN8
AN9
AN10
AK1
AK2
AK3
AK4
AK5
AK6
AK7
AK8
AK9
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AK39
AK40
AK41
AK42
AK43
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
AK7
AK8
VSS
6
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
U100-3
1366LGA_6
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AN39
AN40
AN41
AN42
AN43
VCC
VCC
VSS
VSS
VID7
VID2
VID4
VSS
VSS
VSS
AM1
AM2
AM3
AM4
AM5
AM6
AM7
AM8
AM9
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM37
AM38
AM39
AM40
AM41
AM42
AM43
VSS
VID3
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
AH1
AH2
AH3
AH4
AH5
AH6
AH7
AH8
AH9
AH10
AH11
AH33
AH34
AH35
AH36
AH37
AH38
AH39
AH40
AH41
AH42
AH43
D
VSS
VSS
VSS
AV1
AV2
AV3
AV4
AV5
AV6
AV7
AV8
AV9
AV10
AV11
AV12
AV13
AV14
AV15
AV16
AV17
AV18
AV19
AV20
AV21
AV22
AV23
AV24
AV25
AV26
AV27
AV28
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AV37
AV38
AV39
AV40
AV41
AV42
AV43
VID1
VID0
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VSS
U100-2
1366LGA_6
AL1
AL2
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AL36
AL37
AL38
AL39
AL40
AL41
AL42
AL43
VCC
Technical Brief 486
ISL6334EVAL1Z Board Layout
FIGURE 12. TOP SILKSCREEN
7
July 7, 2010
TB486.0
Technical Brief 486
ISL6334EVAL1Z Board Layout (Continued)
FIGURE 13. TOP COMPONENT SIDE
8
July 7, 2010
TB486.0
Technical Brief 486
ISL6334EVAL1Z Board Layout (Continued)
FIGURE 14. INTERNAL PLANE L2
9
July 7, 2010
TB486.0
Technical Brief 486
ISL6334EVAL1Z Board Layout (Continued)
FIGURE 15. INTERNAL ETCH L3
10
July 7, 2010
TB486.0
Technical Brief 486
ISL6334EVAL1Z Board Layout (Continued)
FIGURE 16. INTERNAL ETCH L4
11
July 7, 2010
TB486.0
Technical Brief 486
ISL6334EVAL1Z Board Layout (Continued)
FIGURE 17. INTERNAL PLANE L5
12
July 7, 2010
TB486.0
Technical Brief 486
ISL6334EVAL1Z Board Layout (Continued)
FIGURE 18. SOLDER SIDE BOTTOM
13
July 7, 2010
TB486.0
Technical Brief 486
ISL6334EVAL1Z Board Layout (Continued)
FIGURE 19. SILKSCREEN BOTTOM
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
July 7, 2010
TB486.0