The following document contains information on Cypress products. 5ch System Power Management IC for LCD Panel with VCOM Regulator ASSP for Power Management Applications MB39A302 Data Sheet (Full Production) Publication Number MB39A302-DS405-00005 CONFIDENTIAL Revision 1.1 Issue Date January 31, 2014 D a t a S h e e t 2 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 5ch System Power Management IC for LCD Panel with VCOM Regulator ASSP for Power Management Applications MB39A302 Data Sheet (Full Production) DESCRIPTION MB39A302 is a 5ch system power supply management IC. It consists of 1ch Buck converter, 1ch Boost converter, 2ch charge pump, 1ch LDO, an operational amplifier for VCOM calibration and a gate voltage shaping circuit. The Buck converter is a voltage mode asynchronous converter with integrated switching FET. The Boost converter equips integrated switching FET with voltage mode control. It is most suitable for large size LCD panel power supply. FEATURES Power supply voltage range (VIN=VINVL=VIN2) Boost Converter included SW FET (Vs) Buck Converter included SW FET (Vlogic) Negative charge pump with output voltage feedback (VGL) Positive charge pump with output voltage feedback (VGH) Low dropout regulator (Vref_o) High performance operational amplifier (VCOM) : 8V to14V : output 20V Max 1.5A Max : output 1.8V to 3.3V 1.1A Max : output current 250mA Max : output current 250mA Max : output current 60mA Max : output current ±75mA Max, 20MHz Gain bandwidth Feedback threshold voltage : 1.25V ±1% (Vs) : 1.25V ±1% (Vlogic) : 0.25V ±40mV (VGL) : 1.25V ±2% (VGH) : 1.25V ±0.5% (Vref_o) Built-in soft-start circuit independent of loading (Vs - programmable, Vlogic, VGL, VGH) Excellent line regulation by the feed-forward method (Vs, Vlogic) Built-in output over voltage protection (Vs, Vlogic) Built-in output under voltage and short circuit protection (Vs, Vlogic, VGL, VGH) Built-in current limit protection (Vs - programmable, Vlogic, Vref_o, OPO) Built-in external p-channel gate control for Vs sequencing Integrated gate voltage shaping circuitry with adjustable turn on delay Built-in under voltage lock out protection function Built-in over temperature protection Selectable 500kHz/750kHz switching frequency Package: QFN-48 Exposed PAD APPLICATIONS Power supply of LCD panel for TV and monitor Publication Number MB39A302-DS405-00005 Revision 1.1 Issue Date January 31, 2014 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. CONFIDENTIAL D a t a S h e e t PIN ASSIGNMENTS DLY1 FBP VGH VGHM DRN SUPN DRVN GND FBN REF VREF_FB VREF_O (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 VREF_I 1 36 DRVP VOP 2 35 CPGND OGND 3 34 SUPP OPP 4 33 THR OPN 5 32 COMP OPO 6 31 FB1 XAO 7 30 GD GVOFF 8 29 GD_I EN 9 28 PGND FB2 10 27 PGND OUT 11 26 LX1 GND 12 25 LX1 SS CLIM FSEL VL INVL VDET GND IN2 IN2 BST LX2 LX2 13 14 15 16 17 18 19 20 21 22 23 24 (LCC-48P-M11) 2 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t PIN DESCRIPTION Block Vs (Boost DC/DC) Vlogic (Buck DC/DC) VGL (Negative Charge Pump) VGH (Positive Charge Pump) Gate Voltage Shaping Vref_o (LDO) VCOM (OPAMP) Misc. Control Pin Pin No. Pin Name 23 24 25 26 CLIM SS LX1 LX1 29 GD_I I 30 31 32 10 11 13 14 15 42 43 45 46 36 34 GD FB1 COMP FB2 OUT LX2 LX2 BST SUPN DRVN FBN REF DRVP SUPP O I O I I External isolation PMOS source terminal connection and VGH supply pin External isolation PMOS gate terminal connection pin Boost converter Error Amp input pin Boost converter frequency compensation pin Buck converter Error Amp input pin Buck converter regulated output sense pin O Buck converter inductor connection pin I/O O O I O O O 38 FBP I 39 40 41 8 VGH VGHM DRN GVOFF I I/O I/O I 33 THR I 37 47 48 4 5 6 21 7 9 19 22 DLY1 VREF_FB VREF_O OPP OPN OPO VL XAO EN VDET FSEL I I O I I O O O I I I January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL I/O Description I I Boost converter current limit setting pin Boost converter soft start timing control pin O Boost converter inductor connection pin Buck converter gate drive boot pin VGL power supply decoupling capacitor connection pin VGL external pumping capacitor connection pin VGL Error Amp input pin Reference voltage output pin VGH external pumping capacitor connection pin VGH power supply decoupling capacitor connection pin VGH Error Amp input pin Gate shaping circuit high voltage input pin Gate voltage shaping circuit output pin Gate voltage shaping discharge slope adjustment pin Gate voltage shaping circuit control pin Gate voltage shaping circuit output lower limit control pin (10xTHR) Time delay control pin for gate voltage shaping circuit LDO feedback input pin LDO output pin VCOMP OPAMP non-inverting input pin VCOMP OPAMP inverting input pin VCOMP OPAMP output pin Internal 5.2V regulator output pin Open drain output of power supply detection circuit 5.2V rated Boost converter enable pin Power supply detection input pin Switching frequency select pin 3 D a t a S h e e t Block Pin No. Pin Name Power 1 2 16 17 20 27 28 35 44 3 12 18 VREF_I VOP IN2 IN2 INVL PGND PGND CPGND GND OGND GND GND 4 CONFIDENTIAL I/O I I I I I - - Description VREF LDO supply pin VCOMP OPAMP supply pin Buck converter and VGL power supply pin Buck converter and VGL power supply pin Common and Internal 5.2V regulator supply pin High Current Boost Ground pin VGH Ground pin Analog ground pin VCOM OPAMP ground pin Analog ground pin Analog ground pin MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t I/O PIN EQUIVALENT CIRCUIT DIAGRAM January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 5 D a t a S h e e t 6 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t BLOCK DIAGRAM January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 7 D a t a S h e e t FUNCTIONAL DESCRIPTIONS CH1 (Vs): Boost Converter The Boost converter features fixed frequency pulse width modulated (PWM) control with integrated NMOS power switch. The switching frequency can be set to either 500 kHz or 750 kHz via the FSEL pin. The converter operates as an asynchronous Boost converter with external Schottky diode. The use of voltage mode control with input feed forward improves line regulation performance. In addition, the converter is designed with external frequency compensation that allows flexibility on selecting external component values. A PMOS switch with on resistance of 18Ω connects between LX1 and GD_I pin so that it operates in parallel with the external Schottky diode. At high loading current, most of the inductor current flows through the external Schottky diode. At light load, the PMOS switch provides a conduction path that allows the inductor current flow in reverse direction. As a result, the converter stays in continuous conduction mode for most of the load current range and allows the use of simple frequency compensation scheme. Soft Start (Boost Converter) The build in soft start circuit limits the inrush current at start up. The soft start cycle starts after EN is asserted and the duration can be set by user through the capacitor connected to SS pin. (1) When SS pin capacitor value > 220pF, soft start time is set externally. Charging current is 5μA and trigger threshold is 1.25V. (2) When SS pin capacitor value < 220pF or SS pin is open, soft start time is fixed internally at 10ms. Protection (Boost Converter) The Boost converter has built in over voltage protection to prevent MB39A302 from being damaged due to excessive voltage stress under fault conditions such as FB1 pin is left floating or short to ground. The protection circuitry monitors the Boost converter output via GD_I pin and shut down the NMOS power FET that connects to LX1 pin when the voltage on GD_I pin is higher than 21.5V. As a result, the inductor current starts to fall and the output of the Boost converter follows. The Boost converter resumes normal operation when the voltage at GD_I pin falls below the protection threshold. The Boost converter has built in under voltage protection and short circuit protection to prevent MB39A302 from damage due to low voltage stress under fault conditions. The protection circuitry monitors the Boost converter output via FB1 pin and the Under Voltage Protection activates when the voltage on FB1 pin is lower than 1V and the NMOS power FET will be shut down after 50ms. The Short Circuit Protection will activate when the voltage of FB1 pin is lower than 0.5V and the NMOS power FET will be shut down immediately. In addition, Boost converter has programmable over current protection that turns off the power FET to prevent excessive output current from damaging internal IC and external components. Gate Drive Pin (GD) GD pin voltage is pulled down by 10µA (Typ) internal current source after EN pin is asserted. The external PMOS turns on and connects the cathode of the Boost converter Schottky catch diode to the Boost converter load capacitors when GD falls below the turn-on threshold of the external PMOS. When VGD reaches VGD_I-6V, the Boost converter regulator is enabled and initiates a soft-start routine. Startup SCP protection is included to protect external PMOS from permanent damage in the event that Boost output is initially shorted to GND upon power up. When not using this feature, leave GD high impedance and connect GD_I to the output of the Boost converter. CH2 (Vlogic): Buck Converter The Buck converter is a fixed frequency PWM control asynchronous converter with integrated NMOS power switch. It features voltage mode control with input feed forward to improve line regulation performance. The main switch of the converter is a 3.2A rated power NMOS with gate drive circuit reference to LX2 pin (source terminal of the NMOS power FET). The gate drive circuit is powered from an internal 5V regulator and is bootstrapped from LX2 pin via an external capacitor to achieve driving capability beyond the supply rail. 8 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Soft Start (Buck Converter) The build in soft start circuit limits the inrush current at start up. The soft start cycle start after power supply is asserted and the duration is internally set to 3ms. Protection (Buck Converter) The Buck converter has built in over voltage protection to prevent MB39A302 from being damaged due to excessive voltage stress under fault conditions such as FB2 pin is left floating or short to ground. The protection circuitry monitors the Buck converter output voltage via OUT pin and shut down the NMOS power FET that connects to LX2 pin when the voltage on OUT pin is higher than 3.7V. As a result, the inductor current starts to fall and the output of the Buck converter follows. The Buck converter resumes normal operation when the voltage at OUT pin falls below the protection threshold. The Buck converter has built in under voltage protection and short circuit protection to prevent MB39A302 from damage due to low voltage stress under fault conditions. The protection circuitry monitors the Buck converter output voltage via FB2 pin and the Under Voltage Protection activates when the voltage on FB2 pin is lower than 1V and the NMOS power FET will be shut down after 50ms. The Short Circuit Protection will activate when the voltage of FB2 pin is lower than 0.5V and the NMOS power FET will be shut down immediately. In addition, Buck converter has over current protection that turns off the power FET to prevent excessive output current from damaging internal IC and external components. CH3 (VGL): Negative Charge Pump The negative charge pump uses fixed switching frequency controlled architecture. The output voltage is set externally by a resistor divider. Regulation is done by controlling the pump current in the driver. The charge pump uses external diodes, pumping capacitor and output filter capacitor. Since the input of the charge pump and the driver is connected to the supply pin (VIN), the maximum negative output voltage is -VIN +Vloss. Vloss includes voltage drop in external diodes and gate driver. Additional charge pump stage can be added to generate larger negative voltage. Protection (Negative Charge Pump) The negative charge pump has built in under voltage protection and short circuit protection. The protection circuitry monitors the charge pump output voltage via FBN pin and the Under Voltage Protection activates when the voltage on REF-FBN pin is lower than 0.8V and the power FETs will be shut down after 50ms. The Short Circuit Protection will activate when the voltage of REF-FBN pin is lower than 0.4V and the power FETs will be shut down immediately. CH4 (VGH): Positive Charge Pump The positive charge pump uses fixed switching frequency controlled architecture. The output voltage is set externally by a resistor divider. Regulation is done by controlling the pump current in the driver. The charge pump uses external diodes, pumping capacitor and output filter capacitor. The input of the charge pump is connected to the VS (Boost converter output) and the pump capacitor is charged to VS during charging phase. As the supply to the driver (SUPP pin) can be either the VS (Boost converter output) or the VIN (Power supply) of MB39A302, the maximum output voltage is VSUPP + VS - Vloss. Vloss includes voltage drop in external diodes and gate driver. Additional charge pump stage can be added to increase the maximum output voltage. Protection (Positive Charge Pump) The positive charge pump has built in under voltage protection and short circuit protection. The protection circuitry monitors the charge pump output voltage via FBP pin and the Under Voltage Protection activates when the voltage on FBP pin is lower than 1V and the power FETs will be shut down after 50ms. The Short Circuit Protection will activate when the voltage of FBP pin is lower than 0.5V and the power FETs will be shut down immediately. January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 9 D a t a S h e e t CH5 (Vref_o): Low Dropout regulator (LDO) The integrated low noise low drop out regulator (LDO) is available with 60mA current capability. It has built in over current protection circuit to prevent the LDO from being damaged under fault conditions. This LDO can be stable with 1μF to 10μF output ceramic capacitor. CH6 (OPO): VCOM Operational Amplifier The integrated low input offset voltage operational amplifier (OP Amp) is available with ±75mA current capability. It can be stable with 3Ω to 10Ω load resistor in series with 1μF to 150μF output capacitor. There is also built in over current protection to prevent this amplifier from being damaged under fault conditions. Gate Voltage Shaping The ability to control the falling edge of the gate drive signal is essential for reduction of flicking on LCD display. The gate voltage shaping circuit provides timing and slew rate control for the gate drive signal and an isolation switch to protect circuit powered from VGH. Upon initial startup, VGHM output stays low until after XAO is released (pulled low), VGH reached power good and the capacitor on DLY1 pin past 1.25V. Then, VGHM would be dictated by the logic level on GVOFF and the cut threshold dictated by THR pin voltage. After this, if XAO is pulled low, then VGH and VGHM are shorted together as long as there is enough supply voltage to maintain the circuit operation. XAO XAO is an open-drain output that externally connects through a resistor to Vlogic. Upon startup, XAO follow VLOGIC output. When VLOGIC and VGL reaches 90% of its final output, XAO control is passed to VDET pin. When VDET sense that VIN is below desired voltage (defined by external resistor divider), XAO is pulled low immediately. Common Block Under Voltage Lockout Protection MB39A302 will shutdown when the supply voltage below 6V to prevent improper operation of the device. Over Temperature Protection When the junction temperature rises above +150°C, most of the active circuitries are shutdown to prevent damage from excessive power dissipation beyond safety limits. 10 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Power Up Sequencing January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 11 D a t a S h e e t Power Down Sequencing 12 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Symbol VDD VBOOT AVDD VLV_IN Input/Output voltage SW voltage SW peak current Power dissipation Storage temperature VLV_OUT VHV_IN VGL_OUT VGH_OUT VGH VGS VREFO VOPP VOPN VOPO SUPN VGD VLX VLX ILX ILX PD TSTG Condition IN2, INVL BST SUPP, VREF_I, VOP CLIM, SS, FB1, FB2, FBN, FBP, GVOFF, THR, DLY1, VREF_FB, EN, VDET, OUT COMP, REF, XAO, VL FSEL DRVN DRVP VGH VGHM, DRN VREF_O OPP OPN OPO SUPN GD, GD_I LX1 LX2 LX1 AC LX2 AC Ta ≤ +85°C - Rating Unit Min Max -0.3 -0.3 -0.3 +20 +25 +25 V V V -0.3 +5.5 V -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -1 -1 -0.3 -0.3 -0.3 -2 -55 +5.5 +20 +20 +25 +40 +40 +20 +25 +25 +25 +20 +25 +25 +20 4.2 3.9 1.51 +125 V V V V V V V V V V V V V V A A W °C *: When mounted on a 100mm ×100 mm: 4 layer (2S2P JEDEC). θja: 26.5°CW-1, θjc: 0.5°CW-1 WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 13 D a t a S h e e t RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Symbol Condition VIN VBOOT VSUP VSS VTHR VILIM IN2, INVL, SUPN BST SUPP, VREF_I, VOP SS, DLY1 THR CLIM FB1, FB2, FBN, FBP, VREF_FB, OUT GD, GD_I EN, GVOFF FSEL VGH OPP, OPN VDET VS: Boost DC/DC VLOGIC: Buck DC/DC VGL VGH, VGHM VREF_O: LDO (Io = 1mA to 60mA) OPO: Opamp (Io = 1mA to 25mA) XAO VS: BOOST DC VLOGIC: BUCK DC VGL DC DRN pin Peak VGH DC Vref DC: VREF_O VCOMP DC: OPO VCOMP AC: OPO GD GD_I (light load) DRVN DRVP REF LX1 LX2 BST SUPP VFB Input voltage VGD VEN VFSEL VGH VCOM VXAO VO1 VO2 VO3 VO4 Output voltage VO5 VO6 Output current REF pin output current SW inductor BOOT pin capacitor SUPP pin capacitor GD pin capacitor DRP, DRN pins capacitor SUPN pin capacitor REF pin capacitor VL pin capacitor 14 CONFIDENTIAL VOX IO1 IO2 IO3 IO4 IO4 IO5 IO6 IO6 IGD IGDI IDRVN IDRVP IREF LX1 LX2 CBOOT CSUPP CGD1, CGD2 CDRV CSUPN CREF CVL Min Value Typ 8 12*1 8 0 0 0 Max Unit - 14 19 20 5 5 5 V V V V V V 0 - 5 V 0 0 0 0 0 0 20 5 20 37 20 3.7 - 17.7 3.3 -5.5 30 - V V V V V V V V V V - 17 - V - 7.5 - V 0 0 0 0.1 5 1.5*2 1.1 0.25*3 0.1 0.25*4,*5 60 75 200 - V A A A A A mA mA mA µA mA mA mA µA µH µH µF µF -0.25 0.5 -75 -200 -100 -500 -500 -50 10 100 500 500 0 - 6.8 10 0.10 1 GD - 10 - µF DRVP, DRVN SUPN REF VL - 0.47 1 1 1 - µF µF µF µF 0.01 1.00 MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Parameter Symbol Condition Min Value Typ Max Unit CINVL INVL 1 μF INVL pin capacitor CVREFI VREFI 1 μF VREFI pin capacitor CVOP 1 μF VOP pin capacitor VOP IN2 pin capacitor CIN2 10 40 70 µF IN2 CLIM pin resistor RCLIM CLIM 60 kΩ VS output filter capacitor Cout1 60 µF VS: Boost DC/DC VLOGIC output filter capacitor Cout2 µF 2×10 VLOGIC: Buck DC/DC VGL output filter capacitor Cout3 1 20 µF NCP VGH output filter capacitor Cout4 0.47 10.00 µF PCP VGHM output capacitor Cscan 1 1000 nF In series with Rscan LDO output filter capacitor Cout5 1 4.7 10 µF VREF_O: LDO VCOMP output filter capacitor Cout6 1 10 150 µF In series with Rout VGHM output resistance Rscan 1.61 kΩ VGHM VGHM output resistance Rdrn 200 3000 Ω DRN VCOMP output filter resistance Rout6 3 10 Ω In series with Cout Charge/Discharge cycle frequency Fscan 40 70 kHz Discharge duration Tdscan 1 10 µs Operating ambient temperature Ta -30 +25 +85 °C *1: Performance is guaranteed for 12V±10% *2: Maximum current is only guaranteed if OCP is not triggered. ILIM> Vo1 × Io1max/VIN + VIN × (Vo1-VIN) /L/fosc/Vo1/2 For: VIN=8V, Iomax=1A, VIN=10V, Iomax=1.2A, VIN ≥ 12V, Iomax=1.5A *3: Maximum current is only guranteed if VIN-|Vo3|>Rdsonmax (Hiside + Loside) × 2 × Imax + 2 × Vdiode + Imax / (fosc × Cpump) (for doubler). For Vo3 = -5.5V: VIN>12V, Iomax=250mA, VIN=10V, Iomax=150mA, VIN=8V, Iomax=80mA *4: Maximum current is only guaranteed if 2 × Vo1 - Vo4 > Rdsonmax (Hiside + Loside) × 2 × Imax + 2 × Vdiode + Imax/(fosc × Cpump) (for doubler). For Vo1=17.7V: Iomax=150mA *5: Maximum current is only guaranteed if VIN+2 × Vo1 - Vo4 > Rdsonmax (Hiside + Loside) × 4 × Imax + 4 × Vdiode + 3 × Imax/(fosc × Cpump) (for Tripler) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 15 D a t a S h e e t ELECTRICAL CHARACTERISTICS (Ta=0°C to +85°C, VIN=IN2=INVL=12V, SUPP=VREF_I=VOP=17.7V. Typical values are at Ta=+25°C unless noted otherwise) Parameter REF Block [REF] Under Voltage Lockout Protection Circuit Block [UVLO] Over Temperature Protection Block [OTP] Control Block [CTL] Symbol REF output REF voltage REF load REF regulation INVL UVLO UVLOIN threshold INVL INHYS hysteresis width VL UVLO UVLOVL threshold VL hysteresis VLHYS width Stop TOTPH temperature Hysteresis width Input voltage threshold EN pulldown resistance FSEL pullup current 46 0<IREF<50µA 16,17 21 VL= 21 - 8,9,22 T junction - EN, GVOFF, FSEL ON EN, GVOFF, FSEL 8,9,22 OFF REN 9 EN IFSEL 22 FSEL INVL + IN2 standby current ISB Oscillator Block [OSC] Output frequency fosc VL Regulator [VL] VL output voltage VL load regulation General Min INVL= 16,17 VIH IQ CONFIDENTIAL IREF=0mA - VIL Condition 46 TOTPHYS INVL + IN2 quiescent current 16 Pin FB1 = FBP = 1.5V, 16,17, FBN = 0, EN = VL, 20 FSEL = H (Only LX2 switching) FB1 = FB2 = FBP = 1.5V, 16,17, FBN = 0, 20 EN = VL, FSEL = H (No switching) 13, 14 FSEL = "H" 25, 26 36, 43 FSEL = "L" VL 21 IL = 0mA VL 21 0 < IVL < 30mA Value Typ Max Unit -2% 1.25 +2% V - - 15 mV 5.3 6 6.7 V - 0.5 - V 3 3.4 3.8 V - 0.5 - V - 150* - °C - 20* - °C 2 - - V - - 0.9 V - 800 - kΩ 1.4 2.4 4.0 µA - 5 - mA - 4 - mA 630 750 870 kHz 420 500 580 kHz 4.9 5.2 5.5 V - - 300 mV MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t (Ta=0°C to +85°C, VIN=IN2=INVL=12V, SUPP=VREF_I=VOP=17.7V. Typical values are at Ta=+25°C unless noted otherwise) Parameter Line regulation Load regulation Threshold voltage Input bias current SW NMOS-Tr On resistance SW PMOS-Tr On resistance VS [Boost DC/DC] Symbol Pin Condition Vline1 Vload1 29,34 29,34 VIN=10.8V to 13.2V Io1= 150mA to 1.5A VTH1 31 IB1 31 RON1 RON1 SW PMOS-Tr Leak current ILEAK1 29 SW NMOS-Tr Leak current ILEAK1 25,26 ILIM1 25,26 Vuvp1 31 Td,uvp1 - Vovp1 34 Vscp1 Output OCP threshold Output UVP threshold Output UVP delay time Output OVP threshold Output SCP threshold Soft-start time GD clamp voltage GD discharge current Tss1 Unit -1 - 0.15 +1 %/V %/A FB1 -1% 1.25 +1% V FB1 =0V -100 0 100 nA - 120 185 mΩ - 18 36 Ω - - 10 µA - - 10 µA LX1=500mA VGS=5V GD_I=-200mA VGS=5V EN=0V GD_I=15V LX1=0V EN=0V LX1=15V LX1, RCLIM > 60kΩ A 1 1.04 V 42 50 58 ms SUPP 21 21.5 22 V 31 FB1 0.4 0.5 0.6 V 3.8 5 6 µA 24 SS: CSS>220pF SS charge current SS: CSS<220pF V(GD)-V(GD_I)> 4V to 95% VO1 - 10 - ms V(GD) - V(GD_I) -7 -6 -5 V GD 4 10 16 µA 29,30 IGD1 30 FB1 2.83.54.260.5kΩ/ 60.5kΩ/ 60.5kΩ/ RCLIM RCLIM RCLIM 0.96 VGD1 January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 25, 26 27, 28 25,26, 29 Min Value Typ Max - 17 D a t a S h e e t (Ta=0°C to +85°C, VIN=IN2=INVL=12V, SUPP=VREF_I=VOP=17.7V. Typical values are at Ta=+25°C unless noted otherwise) Parameter Vlogic [Buck DC/DC] VGL [Negative Charge Pump] 18 CONFIDENTIAL Bootstrap output Threshold voltage Input Bias current SW NMOS-Tr (upper) On resistance SW NMOS-Tr (upper) Leak current OUT to GND switch on resistance Output OVP threshold Output UVP threshold Output UVP delay time Output OCP threshold Output SCP threshold Load regulation Line regulation Soft-start time Threshold voltage Input bias current SW NMOS-Tr On resistance SW PMOS-Tr On resistance Output UVP threshold Output UVP delay time Output SCP threshold Soft start up time Symbol Pin VBST 15 FB2=5V VTH2 10 IB2 10 RON2 ILEAK2 Condition Min Value Typ Max Unit - 4.5 - V FB2 -1% 1.25 +1% V FB2=0V -100 0 +100 nA - 200 300 mΩ -10 - - µA 13,14, LX2=0.2A 16,17 VGS=5V 13,14, LX2=0V 16,17 ROUT 11 OUT 70 125 210 kΩ Vovp2 11 OUT DC 3.5 3.7 3.9 V Vuvp2 10 FB2 0.96 1.00 1.04 V Td, uvp2 - 42 50 58 ms 2.2 3.2 3.9 A 0.4 0.5 0.6 V - 3 0.5 0.1 - %/A %/V ms ILIM2 - 13, 14 LX2 Vscp2 10 FB2 Vload2 Vline2 Tss2 11 11 10 Io2=150mA to 1.1A VIN: 10.8 to 13.2V 0 to 99% VO2 VTH3 45 FBN 210 250 290 mV IB3 45 FBN=0V -100 0 +100 nA RON3 43, 44 Iout=100mA - 1.5 3 Ω RON3 42, 43 Iout=100mA - 3.5 7 Ω Vuvp3 45,46 0.768 0.800 0.832 V Td, uvp3 - 42 50 58 ms Vscp3 45,46 0.3 0.4 0.5 V Tss3 45 - 3 - ms REF-FBN REF-FBN 0% to 95% VO3 MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t (Ta=0°C to +85°C, VIN=IN2=INVL=12V, SUPP=VREF_I=VOP=17.7V. Typical values are at Ta=+25°C unless noted otherwise) Parameter VGH [Positive Charge Pump] Threshold voltage GD_I input supply current Input bias current SW NMOS-Tr On resistance SW PMOS-Tr On resistance Output UVP threshold Output UVP delay time Output SCP threshold Soft start up time Symbol Pin VTH4 38 FBP IGDI 29 FBP = 1.5V (not switching) IB4 38 FBP=0V RON4 RON4 CONFIDENTIAL 25, 26 Iout=100mA 27, 28 25, 26 Iout=100mA 27, 28 Vuvp4 38 Td,uvp4 - Vscp4 45,46 Tss4 38 January 31, 2014, MB39A302-DS405-00005-1v1-E Condition FBP FBP 90% VO1 to 95% VO4 Min Value Typ Max Unit -2% 1.25 +2% V - 0.4 - mA -100 0 +100 nA - 1.5 3 Ω - 3.5 7 Ω 0.96 1 1.04 V 42 50 58 ms 0.4 0.5 0.6 V - 3 - ms 19 D a t a S h e e t (Ta=0°C to +85°C, VIN=IN2=INVL=12V, SUPP=VREF_I=VOP=17.7V. Typical values are at Ta=+25°C unless noted otherwise) Parameter VGHM [Gate Voltage Shaping] VGH supply current Rdson charge Rdson discharge VGHM to ground discharge resistance GVOFF to VGHM rise propagation delay GVOFF to VGHM fall propagation delay DLY1 charge current DLY1 voltage threshold 39 Min Value Typ Max Unit GVOFF=0V - 0.1 - mA Rchg5 39, 40 Ichg=100mA - 5 10 Ω Rdis5 40, 41 Idischg=100mA - 20 50 Ω 10 14 20 kΩ - 60 120 ns - 280 500 ns Rvghm 40 DLY1=GND, VGHM=1V RDRN=1k, VGHM noload, GVOFF rising edge to VGHM×0.2 RDRN=1k, VGHM noload, GVOFF falling edge to VGHM×0.8 Tfall 8,40 Idly1 37 - 6 8 10 µA Vdly1 37 - 1.19 1.25 1.31 V Vslide5 33 RDRN=1kΩ, Rscan=1.6kΩ, Cscan=1.3nF 9.4 10 10.6 V/V VDET 19 VDET 1.275 1.300 1.325 V VDEThyst 19 VDET - 50 - mV VXAO5 7 - - 0.4 V IXAO 7 - - 100 nA IREFI 1 - 0.15 - mA Line regulation Vline5 48 - 0.02 - % Load regulation Threshold voltage Drop out voltage Vload5 48 VDET = GND, IXAO = 1mA VDET=1.5V, VXAO=3.3V No load, open loop, VFB=1.5V VREF_I= 13.5V to 20V Io=1mA to 30mA - 0.3 - % VTH5 47 VREF_FB - 0.5% 1.25 + 0.5% V Vload5 48 - - 500 mV - 40 (50kHz) 50 (500/ 750kHz) - dB 60 100 150 mA PSRR Output SCP protection current CONFIDENTIAL IVGH Condition 8,40 VDET threshold voltage VDET hysteresis VDET output voltage VDET output current VREF_I supply current 20 Pin Trise Slider Stop Voltage VREF [LDO] Symbol PSRR5 48 Iscp5 48 IO=60mA VREF_I=VREF_O f=50KHz/ 500KHz/750kHz, Io=10mA, 30mA, VREF_I=Vo5+0.7V, Reference to VREF_I VREF_O = 0V MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t (Ta=0°C to +85°C, VIN=IN2=INVL=12V, SUPP=VREF_I=VOP=17.7V. Typical values are at Ta=+25°C unless noted otherwise) Parameter Symbol Pin VOP supply current IVOP 2 Line regulation Vline6 6 Load regulation Vload6 6 Vdrop6 6 Vdrop6 6 Dropout voltage (sinking) Dropout voltage (sourcing) VCOM [VCOMP OPAMP] Buffer configuration, OPP=OPN=VOP/2, no load VOP 13.5V to 20V, OPP=7.5V IOP 1mA to 75mA, OPP=7.5V Min Value Typ Max Unit - 3 - mA - 0.02 - %/V -0.4 - +0.4 % IOP=-10mA 40 90 180 mV IOP=+10mA 40 90 180 mV - 10 - MHz - 20 - MHz - 60 - dB -15 - +15 mV Unit gain configuration Ro=10Ω, Co=0.1µF,Io=75mA, OPP=6V Unit gain configuration Ro=10Ω, Co=0.1µF, Io=-75mA, OPP=6V f=50KHz/ 500KHz/750kHz, Io6=10mA,100mA dynamic or Io6=30mA static, VOP=8V, reference to VOP Unit gain bandwidth (sourcing) fu66 6 Unit gain bandwidth (sinking) fu66 6 PSRR6 6 Vos6 4, 5 Vslew6 - Ro=10Ω, Co=0.1µF, OPP from 6V ↔ 8V - 40 - V/µs Iscp6 6 OPO - ±200 - mA PSRR Input offset voltage Slew rate Output short circuit current *: Standard design value January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL Condition OPO = 6 to 9V 21 D a t a S h e e t TYPICAL CHARACTERISTICS Boost Converter (Vs) Efficiency vs. Load Current Output Voltage vs. Load Current 100 18.3 Output Voltage (V) 500 kHz 95 Efficiency (%) 90 750 kHz 85 80 75 70 18.0 750 kHz 17.7 17.4 65 500 kHz 60 17.1 55 0 0.5 50 1 1.5 2 Load Current (A) 0 0.5 1 Load Current (A) 1.5 Load Transient Response (Switching Load Current=0.1A to 1.1A) L=6.8µH, Freq=750 kHz Load Transient Response (Pulsed Load Current=0.1A to 1.9A) L=6.8µH, Freq=750 kHz Heavy Load Soft-start (Load Current=0.5A) ILIM1 (ILpeak) vs. RCLIM L=6.8µH, CSS =22nF ILIM1 (ILpeak) (A) 4.0 3.5 750 kHz 3.0 500 kHz 2.5 2.0 OPEN 200 100 50 RCLIM (kΩ) 22 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Buck Converter (Vlogic) Efficiency vs. Load Current Output Voltage vs. Load Current 90 3.45 Efficiency (%) 80 Output Voltage (V) 500 kHz 85 750 kHz 75 70 65 60 3.39 500 kHz 3.33 3.27 750 kHz 3.21 55 3.15 50 0 0.5 1 1.5 Load Current (A) 0.5 1 1.5 Load Current (A) Load Transient Response Heavy-load Soft-start (Switching Load Current=0.3A to 1.8A) (Load Current=1A) L=10µH, Freq=750 kHz L=10µH, Freq=750kHz January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 0 23 D a t a S h e e t Negative Charge-pump (VGL) Normalized Line Regulation Output Voltage vs. Load Current (VIN = 12V) 0.10% 2.0 1.5 Output Voltage Erorr (%) VGL Error (%) 0.05% IVGL=0mA 0.00% IVGL=25mA -0.05% -0.10% 8 10 12 14 1.0 0.5 0 -0.5 -1.0 -1.5 16 SUPN Voltage (V) -2.0 0 50 100 150 200 250 Load Current (A) Load Transient Response Positive Charge-pump (VGH) Normalized Line Regulation (Switching Load Current=10mA to 60mA) 2 VGH Error (%) 1 Io=0A 0 Io=25mA -1 -2 12 13 14 15 16 17 SUPP Voltage (V) 18 Positive Charge-pump (VGH) Load Transient Response Output Voltage vs. Load Current (Switching Load Current = 10mA to 60mA) Output Voltage Error (%) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 50 100 150 Load Current (mA) 24 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Low Dropout regulator (LDO) Line Regulation (Load Current=20mA) Output Voltage vs. Load Current 17.4 18 16 Output Voltage (V) 17.2 Output Voltage (V) 14 17.0 16.8 16.6 17 10 8 6 4 2 18 17.5 12 0 VREF_I Voltage (V) 0 50 100 150 Load Current (mA) Op-amp (VCOM) Output Voltage vs. Load Current (Source) Output Voltage vs. Load Current (Sink) 19 Output Voltage (V) 8 Output Voltage (V) 6 4 2 15 13 11 9 7 0 0 50 100 150 200 250 Load Current (mA) Rail-to-rail Input / Output Waveforms January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 17 0 -50 -100 -150 -200 Load Current (mA) -250 Load Transient Response 25 D a t a S h e e t Large-signal Step Response Small-signal Step Response Switching Frequency vs. Input Voltage Power-up Sequence of All Supply Outputs 800 Frequency (kHz) 775 750 725 700 8 10 12 14 Input Voltage Vin (V) 16 Gate Voltage Shaping (VGHM) (VGHM with 470pF Load) 26 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Switching Frequency vs. Input Voltage VIN Supply Current vs. VIN Voltage 7 INVL Current (mA) Frequency (kHz) 800 775 750 725 700 8 10 12 14 16 Input Voltage Vin (V) All Output Swicthing 6 5 4 Buck Output Swicthing 3 2 No Output Swicthing 1 0 8 10 12 14 16 Input Voltage (V) Reference Voltage Load Regulation 1.270 Reference Voltage (V) 1.265 1.260 1.255 1.250 No Switching 1.245 1.240 1.235 Switching 1.230 0 50 100 150 Load Current (uA) 200 January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 27 D a t a S h e e t Power Dissipation PD (W) Power Dissipation vs Operating Ambient Temperature Operating Ambient Temperature Ta (°C) 28 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t SETUP 1. Setting Control Pin Pin IN2, INVL EN Channels Vlogic: Buck Converter VGL: Negative Charge Pump VS: Boost Converter VGH: Positive Charge Pump VREF_O: LDO OPO: VCOMP OP Standby operating L >6V L H 2. Setting Switching Frequency Pin Setting Internal oscillator frequency FSEL H/Float L 750kHz 500kHz 3. Protection Circuitry (1) IC Under voltage lock out protection: VIN ≤ 6V, all circuits shut down Over temperature protection: Junction Temp > +150°C, all circuits shut down (2) VS: Boost converter Over voltage protection: GD_I pin ≥ 21.5V, protection circuit active Over current protection: threshold value is set by user Short circuit protection: FB1 pin voltage < 1V for 50ms or FB1 pin voltage < 0.5V, protection circuit active. Boost, VGH, VGL are turned off (stop switching) immediately. External GDFET open. Startup short circuit protection: If VS short to ground before power on, IC would trigger protection as VIN is pulled low and disable all channels immediately (3) VLOGIC: Buck converter Over voltage protection: OUT > 3.7V, protection circuit active Over current protection: ILX2 > 3.2A, protection circuit active Short circuit protection: FB2 pin voltage < 1V for 50ms or FB2 pin voltage < 0.5V, protection circuit active. Buck, Boost, VGH, VGL are turned off (stop switching) immediately. External GDFET open. (4) VGL: Negative Charge Pump Short circuit protection: REF-FBN voltage < 0.8V for 50ms or REF-FBN voltage < 0.4V, protection circuit active. Boost, VGH, VGL are turned off (stop switching) immediately. External GDFET open. (5) VGH: Positive Charge Pump Short circuit protection: FBP pin voltage < 1V for 50ms or FBP pin voltage < 0.5V, protection circuit active. Boost, VGH, VGL are turned off (stop switching) immediately. External GDFET open. Power down: When XAO is pulled low, VGHM is shorted to VGH internally. (6) VREF_O: LDO Short current protection: Io > 100mA, protection circuit active. (7) VCOM: VCOMP OP Over current protection: Io > 200mA, protection circuit active. January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 29 D a t a S h e e t APPLICATION NOTE Boost Converter Design Boost Converter Block Diagram Output voltage selection The Boost converter output voltage VS can be set by external resistor divider as below: VS=1.25 × (1+ R3 R4 ) Feedback resistor Resistor values R3 and R4 do not have direct impact on compensation. However, to minimize noise pickup on FB1 without degrading light load efficiency, it is recommended that the equivalent values be set around 100kΩ. Compensation (COMP) Capacitor Selection The regulator compensation is adjusted by an external component connected to the COMP-pin. This pin is the output of internal trans-conductance error amplifier. By adding a resistor in series will change the internal zero to achieve a stable mid-frequency gain. The formula below give the frequency (Fz) at which the resistor increases the high-frequency gain. FZ = 1 2 × π × CC × (RC+115k) For 6.8μH inductor & 60μF output capacitor, we recommend using Cc=680pF and Rc=30kΩ, resulting in fz = 1.5kHz. 30 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Over current protection selection The Over current protection for the Boost converter limits the maximum switching current ISWMAX. The current limit value can be programmed by an external resistor RCLIM. ILIM1=3.5 - 60.5k RCLIM When RCLIM is open, the OCP will set to ILIM1=3.5A. It is recommended that RCLIM be > 60kΩ. Peak inductor current It is necessary to verify the maximum output current of this converter whether it meets the application requirements. The efficiency of the Boost converter can be read from the graph or employ a worst-case assumption of 80%. Duty cycle: D=1- Vin × η Vs Maximum output current: ISmax = (1-D) × (ISWLIM = Vin Vs × (ISWLIM - Peak switching/inductor current: ISWMAX = Vin × D 2 ×fosc × L Vin × D 2 ×fosc × L Vin × D 2 × fosc × L + ) ) ISmax 1-D Where D = Duty cycle fosc = Switching frequency [Hz] (500kHz or 750kHz) L = Inductor value [H] η = Estimated Boost converter efficiency (typically 80% minimum) ISWLIM = Minimum switch current limit of LX1-pin [A] (= 2.8A) ISmax = Maximum output current possible under minimum switch current limit of LX1-pin [A] The selected components, including the embedded switch, the inductor and external Schottky Diode must be able to handle the peak switching current. The estimation should be based on the minimum input voltage, since the switching current will be the highest in this case. Inductor Selection Typical inductor value is 6.8μH. When selects the inductor, chooses an inductor that has saturation current higher than the peak switch current (ISWMAX) as calculated below. Extra margin is required to cope with high current transients. A more conservative design is to use the maximum SW current limit of 4.2A as saturation current rating of inductor. Another parameter for choosing inductor is the DC resistance. Usually, lower the DC resistance can result in higher converter efficiency. January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 31 D a t a S h e e t Rectifier Diode Selection Schottky diode should be used to attain high efficiency. The reverse voltage rating of the diode must be higher than the maximum output voltage of the converter. The required averaged rectified forward current of the Schottky diode is the product of off-time of Boost converter and the maximum switch current at LX1 pin. The peak rectifier forward current is the same as inductor peak current, Iswmax, determined above. Off-time of Boost converter: D’=1-D = Vin Vs Average rectifier forward current: IDmax = Ismax × D’ The rectifier diode selected must have average current rating exceeding IDmax and repetitive peak current rating exceeding Iswmax. A Schottky diode with maximum rectified forward-current of 2A should be sufficient for most applications. Another requirement for Schottky diode is the power dissipation. The power dissipation can be calculated from the formula below: PD = IDMAX × VF = (1-D) × (ISWLIM - Vin × D 2 × fosc × L ) ×VF Where PD = Power dissipation of the diode [W] VF = Diode forward voltage [V] ISWLIM = Minimum over current protection of LX1-pin [A] (3A) Output Capacitor Selection Capacitors with low ESR are recommended. Ceramic capacitor which has low ESR is particularly suitable for this purpose. Typically, six 10µF ceramic capacitors connected in parallel are placed at the converter output. More capacitance can be added so as to reduce voltage drop during heavy load transients. Soft Start Capacitor Selection SS pin capacitor is used for defining the soft start time of Boost converter. The Boost converter soft start time, Tss, is determined by the user when SS pin capacitor value, Css, is higher than 220pF. And the Boost converter soft start time is determined internally when SS pin capacitor value is lower than 220pF or SS pin is open and fixed at 10ms. CSS ≤ 220pF CSS > 220pF 32 CONFIDENTIAL TSS = 10ms TSS = CSS × 1.25/5u MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Buck Converter Design Buck Converter Block Diagram Output voltage selection The Buck converter output voltage Vlogic can be set by external resistor divider as below: Vlogic = 1.25× (1+ R1 R2 ) Softstart Internal preset. The soft start starts after internal POR and UVLO checks are completed and the duration is set to 3ms. Rectifier Diode Selection Schottky diode should be used to attain high efficiency. The reverse voltage rating of the diode must be higher then the maximum output voltage of the converter. The required averaged rectified forward current of diode is the product of off-time of Buck converter and the maximum switch current at SWB pin. Off-time of Buck converter: D' = 1- Vout Vin = 1-D Maximum output current: Iavg = (1-D) × ISWLIM = (1- Vin Vout ) × ISWLIM A Schottky diode with maximum rectified forward-current of 1.5A to 2A should be sufficient for most of applications. The diode forward voltage should be less than 0.7V in order to prevent damage to IC. Another requirement for Schottky diode is the power dissipation. The power dissipation can be calculated from the formula below: PD = Iavg × VF = (1 - D) × ISWLIM × VF January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 33 D a t a S h e e t Where PD = Power dissipation of the diode [W] VF = Diode forward voltage [V] ISWLIM = Minimum over current protection of SWB-pin [A] (2.5A) Feedforward capacitor selection A feed forward capacitor (Cff1) is added parallel to the upper resistor (R1). The Cff1 sets a zero in the transfer function. This will improve the load transient response and stabilize the converter loop. The value of Cff1 is depending on the value of output inductor and capacitor used. For 10µH inductor & 20µF output capacitor, a double pole, fLC, is formed at 11 kHz. For stability, a zero, fz, is recommended to be placed at approximately 70% of fLC = 8 kHz; Cff = 1 2 × π × R1 × fZ = 1 2 × π × 2kΩ × 8kHz = 9.9nF ≈ 10nF A capacitor value close to the calculated value is chosen. A small capacitor to ground, Cfb2, can be added to FB2 node to filter out high frequency noise on the FB2 node. Ensure the low pass filtering pole formed by this R2 and Cfb2 is >> 200 kHz to not impact system stability. Inductor Selection Typical inductor value is 10μH. The current flow through the inductor must be below the saturation current rating of the inductor. The maximum current flowing through the inductor can be found from the following formula: ILMAX ≥ IOMAX + ΔIL = Vin - Vout L ΔIL 2 × Vout Vin × fosc Where: ILMAX = Maximum current through inductor [A] IOMAX = Maximum load current [A] ΔIL = Inductor ripple current peak-to-peak value [A] Vin = Input voltage [V] Vout = Output voltage [V] fosc = Switching frequency [Hz] (500kHz or 750kHz) 34 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Bootstrap Capacitor Selection Bootstrap capacitor connected to BST pin is charged by integrated synchronous diode with 4.5V internal supply. Ceramic capacitor is recommended for less leakage current. 0.1µF bootstrap capacitor is recommended for Buck converter in MB39A302. The bootstrap capacitor voltage rating is suggested to be higher than input voltage. Output Capacitor Selection This IC is designed to work best with ceramic output capacitor. Two 10μF ceramic output capacitors are recommended for most application. More capacitance can be added so as to reduce voltage drop during load transients. Negative Charge Pump Design Negative Charge Pump Block Diagram Output Voltage Selection Recall from functional description, the maximum negative output voltage is - VDRN + 2Vdiode ideally, which is -12V + 0.8V = -11.2V. Similar to Positive Charge Pump, the regulated output voltage can be set by equation below: VGL= 0.25 - R5 R6 Pumping Capacitor and Output Capacitor Selection Selection of pumping capacitor and output capacitor are similar to Positive Charge Pump design. For -5V output, ΔVDRN = |-VGL|-Vdiode = 5V - 0.4V = 4.6V. The pumping capacitor and output filtering capacitor can be estimated for required application. The minimum pumping capacitor is determined by following equation. C≥ Iout f × ΔVDRN , Where: Iout = The output current f = Switching frequency (750kHz/500kHz) ΔVDRN = Pumping clock voltage The charge stored on pumping capacitor is transferred to output capacitor cycle-by-cycle. Output capacitor determines output ripple voltage of charge pump. The ripple voltage is estimated by: Vripple = Iout 2f × Cout + Iout × ESRCout January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 35 D a t a S h e e t Where: Cout=Output filtering capacitance ESRCout = Equivalent series resistance of output filtering capacitor A small capacitor, Cfbl, can be added between FBN and REF node to filter out high frequency noise on the FBN node. A 22pF capacitor is suitable for most applications. Positive Charge Pump Design Positive Charge Pump Block Diagram D 29 << CH4 (Positive Charge Pump) >> R7 FBP 38 R8 Cfbp L priority Error Amp4 1.25V enb4 Current Control Logic Vth (1.25V±2%) Ron=(4Ω at VGS=5V) DRV SUPP 34 B DRVP 36 Ron=(1Ω at VGS=5V) CPGND 35 D VGH (30.2V/250mA) timer ppg Clk 1V 0.5V 1.1V Output Voltage Selection Theoretically, the maximum output voltage is the sum of input voltage and pumping clock voltage of a charge pump. In MB39A302, the maximum output voltage is VS (Boost converter output voltage) + VSUP - 2Vdiode which is 17.7V + 17.7V – 2 (0.4V) = 34.6V with typical setting. Due to the regulated voltage control, the output voltage can be configured by equation below: VGH = Vref × (1+ 36 CONFIDENTIAL R7 R8 ) = 1.25 × (1+ R7 R8 ) MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Pumping Capacitor and Output Capacitor Selection Ceramic capacitor is recommended for its non-polarized, more stable over temperature, low leakage and small ESR. Choosing a pumping capacitor should consider the required voltage rating and output current loading. For 30.2V output voltage setting, the pumping clock voltage is calculated below. ΔVDRP = VGH - VS + Vdiode = 30.2V - 17.7V + 0.4V = 12.9V The minimum pumping capacitor is determined by following equation. Iout C≥ f × ΔVDRP , Where: Iout = The output current f = Switching frequency (750kHz/500kHz) ΔVDRP = Pumping clock voltage The charge stored on pumping capacitor is transferred to output capacitor cycle-by-cycle. Output capacitor determines output ripple voltage of charge pump. The ripple voltage is estimated by: Iout Vripple = + Iout × ESRCout 2f × Cout Where: Cout = Output filtering capacitance ESRCout = Equivalent series resistance of output filtering capacitor A small capacitor, Cfbp, can be added between FBP and GND node to filter out high frequency noise on the FBP node. A 22pF capacitor is suitable for most applications. Low Dropout Regulator Design (LDO) Low Dropout Regulator Block Diagram <<CH5 (LDO)>> E R9 Current sense Vth 1.25V±0.5% Error Amp5 VREF_FB 47 B VREF_I (Vs) 1 Drive r R10 E VREF_O 48 1.25V VREF (17V/60mA) MB39A302 includes a voltage regulator (Low Dropout Regulator, LDO) to supply the Gamma Buffer with a very stable voltage. The LDO is designed to operate typically with a 4.7μF ceramic output capacitor (any value between 1μF and 10μF works properly) and a ceramic bypass capacitor of minimum 1μF on its input VREF_I connected to ground. The output of the Boost converter VS is usually connected to the input VREF_I. The LDO has an internal soft-start feature to limit the inrush current. Output voltage selection The Boost converter output voltage can be set by external resistor divider as below: Vref_o = 1.25 × (1+ R9 R10 ) January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 37 D a t a S h e e t VCOM Operational Amplifier VCOM Operational Amplifier Block Diagram The operational amplifier use Vs for power supply, to get better performance and smaller output noise, a 1μF filter ceramic capacitor should be placed between VOP and GND. The input pin OPP can either feed by a resistor divider from VREFO or an external voltage reference. This operational amplifier is optimized to drive the LCD backplane (VCOM), so it is not stable to drive a pure capacitor load, but series a 3 to 10 Ω small resistor with the load capacitor will provide the stable operation. VGHM: Gate Voltage Shaping Gate Voltage Shaping Block Diagram XAO 7 Rdt VDET << Gate Voltage Shaping >> 19 VGH Rdb 1.25V GVOFF VGH 39 8 CH4pg DLY1 37 Control Logic VGHM VGHM 40 1k 1.25V DRN 41 THR 33 Clamp DLY1 Capacitor Selection Refer to "Power Up Sequence" section, GateShape block power up sequence timing is set by capacitor at DLY1 pin. The delay capacitor can be estimated by following equation. Cdelay = 8μA × tdelay Vref Where: tdelay = Delay time Cdelay = Capacitor connected to DLY1-pin Vref = 1.25V 38 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t XAO The XAO threshold, VINpg, can be set via a VIN resistive divider connecting to on the VDET pin. If we select Rdb in the 10kΩ to 50kΩ range, then Rdt can be determined as: Rdt Rdb = VINpg 1.25V -1 where VINpg is the desired XAO threshold level. Note that Rdt and Rdb should be placed close to the IC. XAO pin is open drain. Please ensure it is pull up to 3.3V or 5.2V supply. VDET pin threshold voltage is 1.25V typically. When using Gate voltage shaping and XAO output, please set 1.25V <VDET < 3.7V. When not using Gate voltage shaping and XAO output, please set VDET pin to ground. Others Input capacitor Selection It is recommended to use low ESR capacitor like ceramic capacitor for the input filtering. For INVL terminal, a 1µF capacitance connected from INVL to ground is needed. For the Buck converter, use typically four 10µF and one 0.1uF ceramic capacitors connected from IN2 pin to ground. Output capacitor Selection Similarly, ceramic capacitors are recommended. For VL pin, a 1µF capacitance connected from VL to ground is recommended. For REF pin, a 1µF capacitance connected from VL to ground is recommended. PCB Layout Recommendation PCB layout is significant for power supply design. Poor layout would result in generating unwanted voltage and current spikes. This will not only affect DC output voltage, but also radiate EMI to adjacent equipment. Sufficient grounding and minimize parasitic inductance can reduce DC/DC converter switching spike noise. January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 39 TP16 GND TP6 VCOM TP21 OPO RP61 EVM3ESX50BE3 C60 0.1uF/25V/10% R22 0R/0603/1% R56 TP10 GVOFF R1 1K/0603/1% 5 R60 0R/0603/1% OP_IN- R21 C62 1uF-150uF/20V/10% R20 NC C24 10uF/25V/10% C23 10uF/25V/10% TP18 GND D2 R4 0R/0805/1% R5 62K/0603/1% VIN GND VIN VIN R11 200K/0603/1% TP8 VIN FB2 OUT R26 NC C26 NC MB39A302 TP12 GND TP2 VO2(Vlogic) VLOGIC L2 10uH R24 0R/0603/1% JP1 12 11 EN GVOFF XAO OPO OPN OPP OGND VOP VREF C32 22pF/50V/5% C71 R8 3 2 1 JP2 LX1_1 LX1_2 PGND_1 PGND_2 GD_I GD FB1 COMP THR SUPP CPGND DRVP 25 26 27 28 29 30 31 32 33 34 35 36 VGH TP7 VGHM TP17 GND LX1 L1 6.8uH R7 0R/0603/1% AVDD_FB TP14 GND D1 MBRA340T3 C17 NC C16 10nF/50V/10% 680 pF /50V/10% C40 1uF/50V/10% C7 NC R17 30.9K/0603/1% C15 C41 0.47uF/25V/10% AVDD_THR C70 10nF/50V/10% 1.5nF/50V/5% 1.61K/0603/1% VGH_FB R78 0R/0603/1% C11 C21 10nF/50V/10% 0R/0603/1% R3 10 9 8 7 OP_OUT 6 4 OP_GND 3 OP_IN+ VLOGIC R2 0R/0603/1% VL 1 U1 27.4R/0603/1% R53 0R/0603/1% OP_VCC 2 R54 0R/0603/1% LDO_IN VO1(Vs) TP20 REF R55 TP4 VO4(VGH) C80 10uF/25V/10% C22 68pF/50V/10% C53 NC R63 10K/0603/1% TP22 XAO VLOGIC R62 10R/1206/1% R51 10.5K/0603/1% 806R/0603/1% R50 MBR0540T1 D31 C81 10uF/25V/10% 19.6R/0603/1% 1.2K/0603/1% 2K/0603/1% R23 TP9 OPP_IN VREF R65 0R/0603/1% TP15 GND TP5 LDO(VREF) R61 15.8K/0603/1% 1 2 3 49 PGND VREF LX2_1 TP13 GND VREF_O 48 604K/0603/1% VREF_FB 47 LX2_2 0R/0603/1% REF 46 BST MBR0540T1 D30 FBN 45 IN2_1 42 R32 IN2_2 44 GND2 41 R31 DRVN 43 AGND R64 19.6K/0603/1% 13 C61 1uF/50V/10% 14 C50 10uF/25V/10% 15 C55 0.1uF/25V/10% 16 C54 1uF/50V/10% 17 LDO_OUT 18 C51 NC SUPN 10uF/25V/10% VDET 10uF/25V/10% 39 C35 VGH C34 C33 1uF/50V/10% VGHM 47K/0603/1% 37 R34 R35 0R/0603/1% 38 C31 0.47uF/25V/10% FSEL C30 1uF/50V/10% 19 D41 MBR0540T1 22 1.5K/1206/1% FBP R33 105K/0603/1% C46 0.47uF/25V/10% LDO_+5V_VCC 20 R73 40 1.5K/1206/1% R72 DRN R74 NC INVL R75 NC VL R76 NC 4 3 2 1 R12 0R/0805/1% 5 G D1 6 S3 D2 7 S2 D3 8 S1 D4 AM4835P TP19 VBST Q1 Default X2 X2 D42 MBR0540T1 VIN JP3 Q2 AO3403/NC D40 MBR0540T1 X3 VO1(Vs) D43 MBR0540T1 VLOGIC 0R/0603/1% R45 C44 22pF/50V/5% 20.5K/0603/1% R42 VGH_FB VO1(Vs) R71 R79 340K/0603/1% 9.76K/0603/1% 120R/0603/1% AVDD_THR 0R/0603/1% R13 TP1 VO1(Vs) TP11 GND LX1 C47 0.47uF/25V/10% R41 475K/0603/1% R44 NC 3 2 1 R40 0R/0603/1% R43 0R/0603/1% C45 0.47uF/25V/10% VLLDO_+5V 21 R77 NC DLY1 CONFIDENTIAL R46 47K/0603/1% CLIM C43 NC SS C42 1uF/50V/10% R70 Current Limit 23 AVDD_FB C18 NC 24 40 VGH TP3 VO3(VGL) D a t a S h e e t CIRCUIT DIAGRAM MB39A302 EVB-01 Rev2.0 R14 R15 R16 392K/0603/1% 29.4K/0603/1% 383R/0603/1% R19 47K/0603/1% C86 10uF/25V/10% C85 10uF/25V/10% C84 10uF/25V/10% C83 10uF/25V/10% C82 NC C14 10uF/25V/10% C13 10uF/25V/10% C12 10uF/25V/10% R18 NC C19 NC 22nF/50V/10% C52 1uF/50V/10% C2 1uF/16V/10% R52 0R/0603/1% R6 10K/0603/1% C20 0.1uF/25V/10% C1 0.1uF/25V/10% MBRA340T3 C6 10uF/25V/10% R25 47K/0603/1% C5 10uF/25V/10% C25 NC C4 10uF/25V/10% C3 10uF/25V/10% MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Part List Count Designator 1 U1 4 C1, C20, C55, C60 1 C2 18 C3, C4, C5, C6, C12, C13, C14, C23, C24, C34, C35, C50, C80, C81, C83, C84, C85, C86 1 C11 1 C15 2 C16, C21 1 C22 7 5 2 1 1 1 2 6 3 Item Specification IC, Power supply of LCD panel 1608, 10%, X7R, 50V, 100nF 1608, 20%, X5R, 16V, 1µF 3216, 10%, X5R, 25V, 10µF 1608, 10%, X7R, 50V, 22nF 1608, 5%, NPO, 50V, 680pF 1608, 10%, X7R, 50V, 10nF 1608, 5%, NPO, 50V, 68pF C30, C33, 3216,10%,X7R,50V, C40, C42, C52, 1µF C54, C61 C31, C41, C45, 3216,10%,X7R,50V, C46, C47 470nF 1608,5%,NPO,50V, C32, C44 22pF 3216,10%,X7R,50V, C62 1µF 1608,10%,X7R,50V, C70 10nF 1608,10%,X7R,50V, C71 1.5nF Diode, Schottky D1, D2 Rectifier, 3A, 40V D30, D31, Diode, Schottky, D40, D41, 500mA, 40V D42, D43 JP1, JP2, JP3 Jumper Inductor, SMT, 4.4A, 35mΩ Inductor, SMT, 4.4A, 35mΩ Part Value Package Part number Vendor Description MB39A302 QFN-48 MB39A302 Spansion Power IC 0.1µF 0603 CC0603KRX7R9BB104 Yageo Capacitor 1µF 0603 CC0603KRX5R7BB105 Yageo Capacitor 10µF 1206 CC1206KKX5R8BB106 Yageo Capacitor 22nF 0603 CC0603KKX7R9BB223 Yageo Capacitor 680pF 0603 CC0603JRNPO9BN681 Yageo Capacitor 10nF 0603 CC0603KRX7R9BB103 Yageo Capacitor 68pF 0603 CC0603JRNPO9BN680 Yageo Capacitor 1µF 1206 CC1206KKX7R9BB105 Yageo Capacitor 0.47µF 1206 CC1206KKX7R9BB474 Yageo Capacitor 22pF 0603 CC0603JRNPO9BN220 Yageo Capacitor 1µF 1206 CC1206KKX7R9BB105 AVX TanCapacitor 10nF 0603 CC0603KRX7R9BB103 Yageo Capacitor 1.5nF 0603 CC0603KRX7R9BB152 Yageo Capacitor MBRA340T3G SMA-403 D MBRA340T3 OnSemi Diode MBR0540T1G SOD-123 MBR0540T1G OnSemi MBR0540T1G - HDR1X3 Standard - HEADER1X3 6.8µH 10.3×10.5 SDCS104R-6R8 Chilisin Inductor 10µH 10.3×10.5 SDCS104R-100 Chilisin Inductor 1 L1 1 L2 1 Q1 MOSFET P-ch AM4835P SO-8 AM4835P Analog Power MOSFET P-ch 1 RP61 Potentiometer,chip, 1% EVM3ESX50BE3 Standard EVM3ESX50BE3 Panasonic Potentiometer 1 R1 Resistor, Chip, 1% 1K 0603 RC0603FR_1KL Yageo Resistor 8 R2, R35, R43, R53, R54, R60, R65, R78 Resistor, Chip, 1% 0R 0603 RC0603FR_0RL Yageo Resistor 1 R5 Resistor, Chip, 1% 62K 0603 RC0603FR_62KL Yageo Resistor 2 R6, R63 Resistor, Chip, 1% 10K 0603 RC0603FR_10KL Yageo Resistor 1 R8 Resistor, Chip, 1% 1.61K 0603 RC0603FR_1K61L Yageo Resistor 1 R11 Resistor, Chip, 1% 200K 0603 RC0603FR_200KL Yageo Resistor 1 R14 Resistor, Chip, 1% 392K 0603 RC0603FR_392KL Yageo Resistor 1 R15 Resistor, Chip, 1% 29.4K 0603 RC0603FR_29K4L Yageo Resistor 1 R16 Resistor, Chip, 1% 383R 0603 RC0603FR_383RL Yageo Resistor 1 R17 Resistor, Chip, 1% 30.9K 0603 RC0603FR_30K9L Yageo Resistor 4 R19, R25, R34, R46 Resistor, Chip, 1% 47K 0603 RC0603FR_47KL Yageo Resistor January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 41 D a t a S h e e t Count Designator Item Specification Part Value Package Part number Vendor Description 1 R21 Resistor, Chip, 1% 2K 0603 RC0603FR_2KL Yageo Resistor 1 R22 Resistor, Chip, 1% 1.2K 0603 RC0603FR_1K2L Yageo Resistor 1 R23 Resistor, Chip, 1% 19.6R 0603 RC0603FR_19R6L Yageo Resistor 1 R32 Resistor, Chip, 1% 604K 0603 RC0603FR_604KL Yageo Resistor 1 R33 Resistor, Chip, 1% 105K 0603 RC0603FR_105KL Yageo Resistor 1 R41 Resistor, Chip, 1% 475K 0603 RC0603FR_475KL Yageo Resistor 1 R42 Resistor, Chip, 1% 20.5K 0603 RC0603FR_20K5L Yageo Resistor 1 R45 Resistor, Chip, 1% 0R 0603 RC0603FR_0RL Yageo Resistor 1 R50 Resistor, Chip, 1% 10.5K 0603 RC0603FR_10K5L Yageo Resistor 1 R51 Resistor, Chip, 1% 806R 0603 RC0603FR_806RL Yageo Resistor 1 R55 Resistor, Chip, 1% 27.4R 0603 RC0603FR_27R4L Yageo Resistor 1 R61 Resistor, Chip, 1% 15.8K 0603 RC0603FR_15K8L Yageo Resistor 1 R62 Resistor, Chip, 1% 10R 1206 RC1206FR_10RL Yageo Resistor 1 R64 Resistor, Chip, 1% 19.6K 0603 RC0603FR_19K6L Yageo Resistor 1 R70 Resistor, Chip, 1% 340K 0603 RC0603FR_340KL Yageo Resistor 1 R71 Resistor, Chip, 1% 9.76K 0603 RC0603FR_9K76L Yageo Resistor 2 R72, R73 Resistor, Chip, 1%, 1/4W 1.5K 1206 RC1206FR_1K5L Yageo Resistor 1 R79 Resistor, Chip, 1% 120R 0603 RC0603FR_120RL Yageo Resistor Connecting pins - - - - Pins Connecting pins - - - - Test Pad - - - - - Capacitor 10µF 1206 CC1206KKX5R8BB106 Yageo Capacitor 1µF 1206 CC1206KKX7R9BB105 Yageo Capacitor Resistor, Chip, 1% 0R 0603 RC0603FR_0RL Yageo Resistor - - - - - Resistor Resistor, Chip, 1% 1.5K 1206 RC1206FR_1K5L Yageo Resistor MOSFET P-ch AO3403 sot23 AO3403 Alpha & Omega MOSFET P-ch - - - - - - - - - - - - TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, 19 TP12, TP13, TP14, TP15, TP16, TP17, TP18, TP19 TP20, TP21, 3 TP22 Not C7, C17, C18, Mounted C19, C26, C53 Not C25, C51, C82 Mounted Not C43 Mounted Not R3, R44 Mounted Not R18, R26 Mounted Not R74, R75, R76, Mounted R77 Not Q2 Mounted Pattern R4, R12 Short R7, R13, R20, Pattern R24, R31, R40, Short R52, R56 3216, 10%, X5R, 25V, 10µF 3216, 10%, X7R, 50V, 1µF Spansion: Spansion Inc. Yageo: YAGEO Corporation AVX: AVX Corporation OnSemi: ON Semiconductor Chilisin: Chilisin Electronics Corp. AnalogPower: Analog Power Panasonic: Panasonic Corporation Alpha & Omega: Alpha & Omega Semiconductor 42 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t LAND PATTERN The MB30A302 has an exposed thermal pad zone on the bottom side of the IC. This area has to be soldered onto the PCB board to enhance heat dissipation. The via should be placed in the thermal pad. These via assist heat dissipation towards the bottom layer of the PCB. Via and copper pad size may be adjusted according to PCB constraints. January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 43 D a t a S h e e t USAGE PRECAUTION 1. Never use setting exceeding maximum rated conditions. Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 2. Use the devices within recommended conditions It is recommended that devices be operated within recommended conditions. Exceeding the recommended operating condition may adversely affect devices reliability. Nominal electrical characteristics are warranted within the range of recommended operating conditions otherwise specified on each parameter in the section of electrical characteristics. 3. Design the ground line on printed circuit boards with consideration of common impedance. 4. Take appropriate static electricity measures. Containers for semiconductor materials should have anti-static protection or be made of conductive material. After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. Work platforms, tools, and instruments should be properly grounded. Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground. 5. Do not apply negative voltages. The use of negative voltages below -0.3 V may activate parasitic transistors on the device, which can cause abnormal operation. 44 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t ORDERING INFORMATION Part number Packege MB39A302WQN 48-pin plastic QFN (LCC-48P-M11) Remarks EV BOARD ORDERING INFORMATION EV board number EV board version No. Remarks MB39A302-EVB-01 MB39A302 EVB-01 Rev1.2 QFN-48 Exposed PAD January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 45 D a t a S h e e t RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION The LSI products of Spansion with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE). A product whose part number has trailing characters “E1” is RoHS compliant. MARKING FORMAT (Lead Free version) Lead-free version INDEX 46 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t LABELING SAMPLE (Lead free version) Lead-free mark JEITA logo The part number of a lead-free product has the trailing characters "E1". January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL JEDEC logo "ASSEMBLED IN CHINA" is printed on the label of a product assembled in China. 47 D a t a S h e e t MB39A302 RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL [Spansion Recommended Mounting Conditions] Item Condition Mounting Method Mounting times IR (infrared reflow), warm air reflow 2 times Before opening Please use it within two years after manufacture. From opening to the 2nd reflow Less than 8 days Storage period Please process within 8 days after baking When the storage period after (125°C ± 3°C, 24hrs + 2H/-0H) opening was exceeded Baking can be performed up to two times.* Storage conditions 5°C to 30°C, 70% RH or less (the lowest possible humidity) *: When taping is used as the shipping form, baking should be performed individually. [Parameters for Each Mounting Method] IR (infrared reflow) 260 °C 255 °C 170 °C to 190 °C (b) RT (a) H rank: 260°C Max (a) Temperature Increase gradient (b) Preliminary heating (c) Temperature Increase gradient (d) Actual heating (d’) (e) Cooling (c) (d) (e) (d') : Average 1°C/s to 4°C/s : Temperature 170°C to 190°C, 60s to 180s : Average 1°C/s to 4°C/s : Temperature 260°C Max; 255°C or more, 10s or less : Temperature 230°C or more, 40s or less or Temperature 225°C or more, 60s or less or Temperature 220°C or more, 80s or less : Natural cooling or forced cooling Note : Temperature : the top of the package body JEDEC standard: Moisture Sensitivity Level 3 (IPC/JEDEC J-STD-020D) 48 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Recommended manual soldering (partial heating method) Item Condition Before opening Storage period Storage conditions Mounting conditions Between opening and mounting Within two years after manufacture. Within two years after manufacture. (No need to control moisture during the storage period because of the partial heating method.) 5°C to 30°C, 70% RH or less (the lowest possible humidity) Temperature at the tip of a soldering iron: 400°C max Time: Five seconds or below per pin* *: Make sure that the tip of a soldering iron does not come in contact with the package body. January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 49 D a t a S h e e t PACKAGE DIMENSIONS 48-pin plastic QFN Lead pitch 0.50 mm Package width × package length 7.00 mm × 7.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.12 g (LCC-48P-M11) 48-pin plastic QFN (LCC-48P-M11) 7.00±0.10 (.276±.004) 4.40±0.15 (.173±.006) 7.00±0.10 (.276±.004) 4.40±0.15 (.173±.006) INDEX AREA +0.05 0.25 –0.07 (.010 +.002 –.003) 0.50(.020) 0.50±0.05 (.020±.002) 1PIN CORNER (C0.30(C.012)) (TYP) 0.75±0.05 (.030±.002) +0.03 0.02 –0.02 +.001 (.001 –.001 ) C (0.20(.008)) 2009-2010 FUJITSU SEMICONDUCTOR LIMITED C48064S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 50 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t Major Changes Page Revision 1.0 Revision 1.1 - Section - Initial release - Company name and layout design change January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL Change Results 51 D a t a S h e e t 52 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014 D a t a S h e e t January 31, 2014, MB39A302-DS405-00005-1v1-E CONFIDENTIAL 53 D a t a S h e e t Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2012-2014 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM, ORNANDTM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 54 CONFIDENTIAL MB39A302-DS405-00005-1v1-E, January 31, 2014